JPH0425916A - Reset circuit - Google Patents

Abstract

PURPOSE:To secure an operation at the time of hitting by inputting one output from an output port to an input port, supervising an output signal level and resetting input/output ports when a supervisory result is abnormal in a communication controller consisting of a processor and peripheral input/output ports. CONSTITUTION:A one shot circuit 5 for resetting the output port 11, and the input port 12 is provided. The output signal 8 of the output port 11 is set to be one input of the input port 12. When a power supply hits and the power supply voltage is restored to the normal one, the processor 10 controls the output signal 8 and inputs the output to the processor 10 through the input port 12. The processor 10 decides the signal level. When it is not normal, a trigger signal 9 is supplied to the one shot circuit 5. It generates the reset signal 6 and initializes the output port 11 and the input port 12 by a port reset signal 7 through an OR gate 20.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a reset circuit, and more particularly to a reset circuit at power-on of a communication control device having a processor and peripheral input and output ports.

[Conventional technology]

FIG. 2 is a circuit diagram showing an example of a conventional reset circuit.

In the reset circuit of this example, the output of a charge/discharge circuit 100 consisting of a resistor 1, a capacitor 3, and a diode 2 is connected to a gate 4.
The signal output until the threshold level of 4 is exceeded is used as a reset signal.

[Problem to be solved by the invention]

The conventional reset circuit described above is only a charging/discharging circuit that includes a resistor and a capacitor, so when the power supply is turned on and is in normal operation, the power supply voltage may momentarily rise to a certain value due to input power fluctuations or momentary power interruptions. When the power supply voltage drops and returns to the normal power supply voltage value, if the lowered voltage value is higher than the threshold level of the gate of the reset circuit and lower than the guaranteed operation voltage of the IC or LSI, the reset signal is Since this does not occur, there is a drawback that the operation of peripheral input/output port LSIs, etc. that require sequential mode setting is not guaranteed, and there is a possibility of abnormal operation.

[Means to solve the problem]

The reset circuit of the present invention is a communication control device having a processor and peripheral input and output ports, and includes a one-shot circuit that generates a reset signal under the control of the processor, a reset signal of a charge/discharge circuit output, and a one-shot circuit that generates a reset signal under the control of the processor. a gate that logically ORs the output with a reset signal, one of the output ports is connected to one of the input ports, and the processor monitors the level of the output signal to one of the output ports and The one-shot circuit is driven when the level of the input signal to one of the input ports differs, and the output port is initialized by the output signal of the OR gate.

〔Example〕 Next, the present invention will be explained with reference to FIG.

FIG. 1 is a block diagram showing one embodiment of the reset circuit of the present invention.

After the reset signal 21 at power-on is released, the processor 10 sets the mode of the peripheral output port 11 and input port 12 via the address bus 14 and data bus 15, and sets the decoder 13 in the normal communication control mode. Output signal 1 by output port select signals 16 and 17
8 and inputs an input signal 19. here,
One output signal 8 of this output port 11 is input to input port 1.
It is received as one of the inputs in step 2.

In this state, if a momentary interruption of the input power supply to this communication control device occurs and the power supply voltage on the secondary side drops momentarily and then returns to the normal voltage, a reset signal is sent so that the voltage drop does not fall below the threshold level of gate 4. 21 is not turned on, and due to the voltage drop, the peripheral output ports 11. The operation of the LSI etc. used in the input port 12 is not guaranteed.

Also, when the power supply voltage returns to normal, the processor 10
controls the output signal 8 of the output port 11 to output "I" and "O", and the output is directly input to the processor 10 via the input port 12. Processor 10 determines whether the signal level of this signal input via data bus 15 is the level set for output signal 8, and if a normal signal level is not recognized, address bus 14. A trigger signal 9 is sent to the one-shot circuit 5 via the decoder 13.
, the one-shot circuit 5 generates a reset signal 6 under the control of the processor 10, and the port reset signal 7 via the OR gate 20 causes the output port 11. The input port 12 is forcibly initialized, the mode setting is restarted, and the communication control mode is set.

〔Effect of the invention〕

As explained above, the present invention adds a one-shot circuit controlled by a processor and a logical sum of the reset signal output from the charging/discharging circuit and the output of the one-shot circuit to the conventional reset circuit using a charging/discharging circuit of a resistor and a capacitor. By inputting one output of the output port to the input port and monitoring the output signal level to that output port, IC, LSI This has the effect of allowing immediate recovery from a situation in which operation is not guaranteed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a reset circuit of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional reset circuit. 1...Resistor, 2...Diode, 3...Capacitor, 4...Gate, 5...One-shot circuit, 7...
- Port reset signal, 8... One output signal of output port 11, 9... Trigger signal, 10... Processor, 11... Output port, 12... Input port, 13
...Decoder, 14...Address bus, 15...Data bus,)

Claims (1)

[Claims] 1. In a communication control device having a processor and peripheral input and output ports, a one-shot circuit that generates a reset signal under the control of the processor, a reset signal of the charging/discharging circuit output, and the one-shot circuit. a gate that logically ORs a circuit output with a reset signal, one of the output ports is connected to one of the input ports, and the processor monitors an output signal level to one of the output ports. A reset circuit that drives the washot circuit when the input signal level to one of the input ports is different from the level of the input signal. 2. The reset circuit according to claim 1, wherein said input and output ports are initialized by an output signal of said OR gate.