JP2530002B2 - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JP2530002B2 JP2530002B2 JP63158666A JP15866688A JP2530002B2 JP 2530002 B2 JP2530002 B2 JP 2530002B2 JP 63158666 A JP63158666 A JP 63158666A JP 15866688 A JP15866688 A JP 15866688A JP 2530002 B2 JP2530002 B2 JP 2530002B2
- Authority
- JP
- Japan
- Prior art keywords
- chip
- metal coating
- die attach
- paste
- die
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
- H01L2224/29298—Fillers
- H01L2224/29299—Base material
- H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/29339—Silver [Ag] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01042—Molybdenum [Mo]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
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- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Description
【発明の詳細な説明】 〔概要〕 半導体チップ（以下ICチップ）を搭載する、セラミッ
クパッケージに関し、 インナーリードへの、銀（Ag）ペースト中の樹脂成分
の、広がりを防ぎながら、ダイアタッチ部分の、高価な
金属被膜を大部分削除して、セラミックパッケージの、
コストを下げることを課題とし、 セラミックパッケージ２と該セラミックパッケージ２
のチップ１が搭載されるダイアタッチ３上に、Agペース
ト４を介して直接取りつけられた半導体チップ１と、該
セラミックパッケージ２の表面に設けられ、前記半導体
チップ１と導電体を介して接続されるインナーリード６
とを有する半導体装置において、前記半導体チップ１が
搭載されたダイス付け部位10の周囲と、前記インナーリ
ード６の内側にリング状に金属被膜８を施すように構成
する。DETAILED DESCRIPTION OF THE INVENTION [Outline] Regarding a ceramic package on which a semiconductor chip (hereinafter referred to as an IC chip) is mounted, a resin component in a silver (Ag) paste on an inner lead is prevented from spreading and a die attach portion is prevented. Of the ceramic package, removing most of the expensive metal coating
To reduce the cost, a ceramic package 2 and the ceramic package 2
The semiconductor chip 1 directly attached via the Ag paste 4 on the die attach 3 on which the chip 1 is mounted, and is provided on the surface of the ceramic package 2 and is connected to the semiconductor chip 1 via the conductor. Inner lead 6
In the semiconductor device having the above, the metal coating 8 is formed in a ring shape around the die attaching portion 10 on which the semiconductor chip 1 is mounted and inside the inner lead 6.
〔産業上の利用分野〕 本発明は、ICチップを搭載する、セラミックパッケー
ジに関する。近年、半導体装置の、低価格化の要求に伴
い、製造コストを下げることが必要である。[Field of Industrial Application] The present invention relates to a ceramic package on which an IC chip is mounted. 2. Description of the Related Art In recent years, it has been necessary to reduce the manufacturing cost with the demand for lower prices of semiconductor devices.
第４図のように、従来の半導体装置（以下IC）におい
ては、ICチップ１は、金／シリコン（Au/Si）共晶体，
金／錫（Au/Sn）共晶体，鉛／錫（Pb/Sn）共晶体といっ
た、ダイス付け材料14を溶融して、ダイアタッチ３に、
固着していた。前記ダイス付け材料14を溶融して、ダイ
アタッチ３に取りつけるため、ダイス付け材料14と、ダ
イアタッチ３との接合性を良くする必要がある。そのた
めに、Auメッキや、ニッケル（Ni）メッキといった金属
被膜18を、下地として、セラミックのダイアタッチの上
に施していた。As shown in FIG. 4, in the conventional semiconductor device (hereinafter referred to as IC), the IC chip 1 is a gold / silicon (Au / Si) eutectic,
The die-attaching material 14 such as a gold / tin (Au / Sn) eutectic and a lead / tin (Pb / Sn) eutectic is melted, and then the die attach 3 is formed.
It was stuck. Since the die attaching material 14 is melted and attached to the die attach 3, it is necessary to improve the bondability between the die attaching material 14 and the die attach 3. Therefore, a metal coating 18 such as Au plating or nickel (Ni) plating is applied as a base on the ceramic die attach.
ところが、最近ダイス付け材料として、銀（Ag）ペー
ストが、開発された。このAgペーストは、前記各共晶体
に比べ、ヤング率が低いため、前記各共晶体より弾性に
優れ、ICチップ１に加わる応力を、緩和する効果が大き
い。このため、ICチップの微細なパターンの断線を防止
できる等、ICの信頼性を向上させることができる。However, recently, a silver (Ag) paste has been developed as a die attachment material. Since this Ag paste has a lower Young's modulus than each eutectic, it is more elastic than each eutectic and has a large effect of relaxing the stress applied to the IC chip 1. For this reason, it is possible to improve the reliability of the IC, such as preventing the breakage of a fine pattern of the IC chip.
さらに優れた点は、このAgペーストは、ICチップ１
を、ダイアタッチ３に取りつけるのに、溶融を必要とし
ない。従って、第５図のように、ICチップの背面７とダ
イアタッチ３との間に、電気的導通が必要ない場合（例
えば、CMOS型IC）は、第４図の従来例と違い、ダイス付
け材料が、溶融を必要としないので、ダイアタッチ３に
NiメッキやAuメッキといった、下地にする金属被膜を、
施す必要がなくなった。従って、このような高価な金属
のメッキの削除が可能となった。What is even better is that this Ag paste is used for IC chip 1
Does not require melting to attach to the die attach 3. Therefore, as shown in FIG. 5, when electrical conduction is not required between the back surface 7 of the IC chip and the die attach 3 (for example, CMOS type IC), unlike the conventional example of FIG. Since the material does not require melting,
Ni plating or Au plating such as a metal film to be the base,
It is no longer necessary to apply. Therefore, it is possible to eliminate such expensive metal plating.
ところが、第５図のように、ダイアタッチ３に、金属
被膜を施さないで、セラミックパッケージ２のセラミッ
クが、露出したダイアタッチ３では、次のような、課題
を生じていた。However, as shown in FIG. 5, in the die attach 3 in which the ceramic of the ceramic package 2 is exposed without applying the metal coating to the die attach 3, the following problems occur.
第５図のように、金属被膜を施さない、表面がセラミ
ックのままのダイアタッチ３に、ICチップ１を取り付け
るのには、まずAgペースト４を、直接セラミックのダイ
アタッチ３の上に取り付ける。次に、ICチップ１を固着
させるために、Agペースト４を乾燥させる。As shown in FIG. 5, in order to attach the IC chip 1 to the die attach 3 which is not coated with a metal film and whose surface is still ceramic, the Ag paste 4 is first attached directly on the ceramic die attach 3. Next, the Ag paste 4 is dried in order to fix the IC chip 1.
この時、Agペースト中の樹脂成分11は、粒子にほとん
ど隙間のない、金属の表面よりも、粒子の隙間が大き
い、セラミックの表面を広がりやすく、毛細管現象等に
より、セラミックの絶縁部９を這い上がり、インナーリ
ード６にまで達する。インナーリード６は、後にワイヤ
ボンディングされるのだが、この場合は、インナーリー
ド６と、ワイヤ５との間に、前記樹脂成分11が、入り込
むことになってしまう。このように、ワイヤ５と、イン
ナーリード６との間に、不純物があると、ワイヤボンデ
ィングする時に、ワイヤ５と、インナーリード６との間
の表面で、起こるはずの金属反応が起こらなくなり、ワ
イヤボンディングが、できなくなる。At this time, the resin component 11 in the Ag paste crawls the insulating portion 9 of the ceramic due to a capillary phenomenon or the like because the resin component 11 in the Ag paste has almost no gaps between the particles, the gap between the particles is larger than the surface of the metal, the surface of the ceramic easily spreads. Go up and reach the inner lead 6. The inner lead 6 is wire-bonded later, but in this case, the resin component 11 will enter between the inner lead 6 and the wire 5. Thus, if there is an impurity between the wire 5 and the inner lead 6, a metal reaction that would otherwise occur on the surface between the wire 5 and the inner lead 6 does not occur during wire bonding, and Bonding becomes impossible.
従って、ダイス付け材料として、Agペーストを、使用
する場合においても、この樹脂成分の広がりを防ぐた
め、ダイアタッチ部分のNiやAuといった、高価な金属被
膜の削除は、出来ないといった課題を生じていた。Therefore, even when using an Ag paste as a die-bonding material, in order to prevent the spread of this resin component, it is impossible to remove expensive metal coatings such as Ni and Au in the die attach portion, which is a problem that cannot be done. It was
本発明は、インナーリードへの、Agペースト中の樹脂
成分の広がりを防ぎながら、ダイアタッチ部分の、高価
な金属被膜を大部分削除して、セラミックパッケージ
の、コストを下げることを目的とする。It is an object of the present invention to reduce the cost of a ceramic package by preventing the resin component in the Ag paste from spreading to the inner leads and removing most of the expensive metal coating on the die attach portion.
第１図は、本発明の構成を説明する図である。 FIG. 1 is a diagram for explaining the configuration of the present invention.
ダイアタッチ３上に、直接Agペースト４で取り付けら
れたICチップ１のダイス付け部位10の周囲であって、イ
ンナーリード６の内側にリング状に、金属被膜８を施す
ものである。The metal coating 8 is applied in a ring shape on the die attach 3 around the die attaching portion 10 of the IC chip 1 directly attached with the Ag paste 4 and inside the inner lead 6.
本発明では、第１図のように、インナーリード６と、
ダイス付け部位10の間にのみ、金属被膜８を部分的にリ
ング状に施すことにより、この金属被膜８が、堤防の役
割を果たし、Agペースト４の乾燥時に、Agペースト４か
ら出る、樹脂成分の広がりを、防ぐことができる。In the present invention, as shown in FIG.
By partially applying the metal coating 8 in a ring shape only between the die-attached portions 10, the metal coating 8 plays a role of a bank, and the resin component that comes out of the Ag paste 4 when the Ag paste 4 is dried. Can be prevented from spreading.
従って、ダイアタッチ３の部分の、高価な金属被膜の
大部分が削除でき、セラミックパッケージ、ひいては、
IC本体のコストを下げるのに、大きく貢献する。Therefore, most of the expensive metal coating of the die attach 3 part can be removed, and the ceramic package, and by extension,
It greatly contributes to reducing the cost of the IC body.
〔実施例１〕 以下、図面に従って、本発明の実施例を説明する。Example 1 An example of the present invention will be described below with reference to the drawings.
第１図はICの断面を示している図である。第１図に示
すように、金属被膜８は、インナーリード６と、ダイア
タッチ３の間のセラミックの絶縁部９に、部分的に形成
したものである。この金属被膜８は上から見ると、リン
グ状になっている。この金属被膜８は、ダイアタッチ３
から、最大でも、絶縁部９の半分程度の高さまで形成す
れば、十分な効果が得られる。FIG. 1 is a diagram showing a cross section of an IC. As shown in FIG. 1, the metal coating 8 is partially formed on the inner lead 6 and the ceramic insulating portion 9 between the die attach 3. The metal coating 8 has a ring shape when viewed from above. This metal coating 8 is a die attach 3
Therefore, a sufficient effect can be obtained if the insulating portion 9 is formed to have a height which is about half that of the insulating portion 9 at the maximum.
このように、目的とする場所に、選択的に金属被膜を
施さなくてはならない。そのための方法は、まず金属被
膜を施す場所に、タングステン（Ｗ）や、モリブデン
（Mo）といった、焼結されたメタライズ層を、セラミッ
クパッケージの、セラミックの上に形成する。これは、
従来周知のスクリーン印刷で、自由に描くことができ
る。そして、このメタライズ層の上に、NiやAuをメッキ
するか、もしくは蒸着して、これらの金属膜を形成すれ
ば、目的とする場所に、選択的に、金属被膜を形成する
ことができる。例えば、Niをメッキして金属被膜とする
場合、前記メタライズ層の上に、ニッケルを無電解メッ
キし、さらに二層目として、ニッケルを電解メッキし
て、Niの金属被膜とする。In this way, the metal coating must be selectively applied to the intended place. As a method therefor, first, a sintered metallization layer of tungsten (W) or molybdenum (Mo) is formed on the ceramic of the ceramic package at the place where the metal coating is applied. this is,
Conventionally known screen printing can be used to draw freely. Then, by plating or vapor-depositing Ni or Au on the metallized layer to form these metal films, a metal film can be selectively formed at a desired place. For example, when Ni is plated to form a metal coating, nickel is electrolessly plated on the metallized layer, and nickel is electrolytically plated as a second layer to form a Ni metal coating.
以上のように、金属被膜８を形成した後、ダイアタッ
チ３の上にAgペースト４を付ける。Agペースト４は、Ag
と、ポリイミドやエポキシといった樹脂と、これらを薄
めるための希釈剤からできている。次に、ダイアタッチ
３の上に付けた、Agペースト４の上に、ICチップ１を付
けて、150℃で１時間程度、Agペースト４を乾燥させ
る。そうすると、Agペースト４は固まり、ダイアタッチ
３とICチップ１は、完全に固着される。金属被膜８が堤
防の役割を果たし、Agペースト４中の樹脂成分は、イン
ナーリード６まで達しない。よって、この後ICチップ１
と、インナーリード６とを、ワイヤ５でワイヤボンディ
ングすればよい。インナーリード６は、セラミックパッ
ケージ２を貫いて、リードピン13に接続する。その後、
キャップ12をセラミックパッケージ２の上に接着し、IC
の内部を密封する。After forming the metal coating 8 as described above, the Ag paste 4 is applied onto the die attach 3. Ag paste 4 is Ag
And a resin such as polyimide or epoxy, and a diluent for diluting them. Next, the IC chip 1 is attached on the Ag paste 4 attached on the die attach 3 and the Ag paste 4 is dried at 150 ° C. for about 1 hour. Then, the Ag paste 4 is hardened and the die attach 3 and the IC chip 1 are completely fixed. The metal coating 8 functions as a bank, and the resin component in the Ag paste 4 does not reach the inner leads 6. Therefore, after this, IC chip 1
And the inner lead 6 may be wire-bonded with the wire 5. The inner lead 6 penetrates the ceramic package 2 and is connected to the lead pin 13. afterwards,
Adhere the cap 12 on the ceramic package 2 and
Seal the inside of the.
〔実施例２〕 第２図に示すように、金属被膜８は、ダイアタッチ３
の外周に、形成したものである。この金属被膜８は、ほ
んのわずかの幅で、十分な効果が得られる。金属被膜の
形成方法や、その後の処理は、実施例１と同様である。
なお、図面は説明に必要な部分だけ描いてある。[Embodiment 2] As shown in FIG.
It is formed on the outer periphery of. The metal coating 8 has a very small width and a sufficient effect can be obtained. The method of forming the metal coating and the subsequent treatment are the same as in Example 1.
It should be noted that only the parts necessary for the description are drawn in the drawings.
〔実施例３〕 第３図に示すように、この場合金属被膜８は、ICチッ
プの背面７とダイアタッチ３の電気的導通をとるため
に、ICチップ１の外周から、ダイアタッチ３の外周にか
けて、施してある。こうすれば、ダイアタッチ３の中央
部分に、余計な金属被膜を施す必要がない。金属被膜の
形成方法や、その後の処理は、実施例１と同様である。
なお、図面は説明に必要な部分だけ描いてある。[Embodiment 3] As shown in FIG. 3, in this case, the metal coating 8 is provided from the outer periphery of the IC chip 1 to the outer periphery of the die attach 3 in order to establish electrical continuity between the back surface 7 of the IC chip and the die attach 3. It has been given over. By doing so, it is not necessary to apply an extra metal coating to the central portion of the die attach 3. The method of forming the metal coating and the subsequent treatment are the same as in Example 1.
It should be noted that only the parts necessary for the description are drawn in the drawings.
以上本発明を実施例により説明したが、本発明はその
趣旨を逸脱しない範囲で、種々の変形が考えられるが、
実施例により本発明から、これらを排除するものではな
い。Although the present invention has been described above with reference to the embodiments, the present invention can be modified in various ways without departing from the spirit of the invention.
The examples do not exclude these from the invention.
以上説明したように、ICチップの背面７と、ダイアタ
ッチ３との間に、電気的導通が必要ない場合、本発明に
よれば、ダイアタッチ部分の、高価な金属被膜の大部分
は、削除できる効果を奏する。As described above, when electrical conduction is not required between the back surface 7 of the IC chip and the die attach 3, according to the present invention, most of the expensive metal coating on the die attach portion is deleted. There is an effect that can be done.
これにより、ICの全メタライズにおいて、20％ものコ
ストが削減でき、IC製造の低コスト化に、寄与するとこ
ろが大きい。As a result, the cost can be reduced by as much as 20% in the total metallization of ICs, which contributes greatly to the low cost of IC manufacturing.
第１図は、本発明の構成を説明する図であり、 第２図，第３図は、本発明の実施例の説明図であり、 第４図，第５図は、従来例である。 １……半導体チップ（ICチップ） ２……セラミックパッケージ ３……ダイアタッチ ４……銀（Ag）ペースト ５……ワイヤ ６……インナーリード ７……ICチップの背面 ８と18……金属被膜 ９……絶縁部 10……ダイス付け部位 11……Agペースト中の樹脂成分 12……キャップ 13……リードピン 14……ダイス付け材料 FIG. 1 is a diagram for explaining the configuration of the present invention, FIGS. 2 and 3 are explanatory diagrams of an embodiment of the present invention, and FIGS. 4 and 5 are conventional examples. 1 ... Semiconductor chip (IC chip) 2 ... Ceramic package 3 ... Die attach 4 ... Silver (Ag) paste 5 ... Wire 6 ... Inner lead 7 ... IC chip back surface 8 and 18 ... Metal coating 9 ... Insulation part 10 ... Die attachment part 11 ... Resin component in Ag paste 12 ... Cap 13 ... Lead pin 14 ... Die attachment material
Claims (1)
れるダイアタッチ（３）上に、銀ペースト（４）を介し
て直接取りつけられた半導体チップ（１）と、 該セラミックパッケージ（２）の表面に設けられ、前記
半導体チップ（１）と導電体を介して接続されるインナ
ーリード（６）とを有する半導体装置において、 前記半導体チップ（１）が搭載されたダイス付け部位
（10）の周囲であって、前記インナーリード（６）の内
側にリング状に金属被膜（８）を施すことを特徴とする
半導体装置。1. A semiconductor package (2) directly mounted on a die attach (3) on which a chip (1) of the ceramic package (2) is mounted via a silver paste (4). 1) and a semiconductor device having an inner lead (6) provided on the surface of the ceramic package (2) and connected to the semiconductor chip (1) through a conductor, wherein the semiconductor chip (1) is A semiconductor device, characterized in that a ring-shaped metal coating (8) is applied to the inside of the inner lead (6) around the mounted die attachment portion (10).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63158666A JP2530002B2 (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63158666A JP2530002B2 (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH027534A JPH027534A (en) | 1990-01-11 |
| JP2530002B2 true JP2530002B2 (en) | 1996-09-04 |
Family
ID=15676699
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63158666A Expired - Fee Related JP2530002B2 (en) | 1988-06-27 | 1988-06-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2530002B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0525735U (en) * | 1991-09-09 | 1993-04-02 | 株式会社村田製作所 | Hybrid integrated circuit device |
| JP5894047B2 (en) * | 2012-06-26 | 2016-03-23 | 京セラ株式会社 | Electronic component storage package |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61104629A (en) * | 1984-10-29 | 1986-05-22 | Fujitsu Ltd | Semiconductor device |
| JPS63155733A (en) * | 1986-12-19 | 1988-06-28 | Fujitsu General Ltd | Method for charging semiconductor chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5455268U (en) * | 1977-09-27 | 1979-04-17 |
-
1988
- 1988-06-27 JP JP63158666A patent/JP2530002B2/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61104629A (en) * | 1984-10-29 | 1986-05-22 | Fujitsu Ltd | Semiconductor device |
| JPS63155733A (en) * | 1986-12-19 | 1988-06-28 | Fujitsu General Ltd | Method for charging semiconductor chip |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH027534A (en) | 1990-01-11 |
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