JP2526886B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to a solid-state image pickup device adopting an interline transfer system and provided with an electronic shutter mechanism.

[Outline of Invention]

The present invention is a solid-state imaging device that adopts an interline transfer system and is provided with an electronic shutter mechanism, and in the vertical blanking period, the electric charge accumulated in the light receiving unit by the exposure up to that time is used as unnecessary electric charge in the vertical register unit. Read to
Then, a drive pulse for high-speed reverse transfer is supplied to the vertical register section to drive the vertical register section at high-speed reverse transfer, thereby sweeping out unnecessary charges to the drain region, and thereafter, removing the unnecessary charges as vertical charges. The charges accumulated in the light receiving part by exposure after being read out to the register part are read out to the vertical register part as signal charges, and subsequently the charges to be the signal charges are transferred to the charge detection part through the vertical register part and the horizontal register part. In the solid-state imaging device configured to do so, after the unnecessary charges are swept out to the drain region, the high-speed positive transfer drive pulse is supplied to the vertical register before the signal charges are read to the vertical register. As a result, the vertical register section is driven at a high speed for positive transfer, so that the potential variations existing in the charge transfer area of the vertical register section are Image defects resulting due to or potential dip, that is, that the manner of occurrence of extraneous bright spots in the captured image can be greatly reduced.

[Conventional technology]

Conventionally, as a solid-state image pickup device adopting the interline transfer system and provided with an electronic shutter mechanism, there has been proposed a solid-state image pickup device whose schematic configuration is shown in FIG.

This solid-state imaging device has a normal mode and an electronic shutter mode as an exposure time mode, can set one field period as the exposure time, and can set a required time within the vertical blanking period as the exposure time. A solid-state image pickup device section (1) and a timing generator (3) which is driven by receiving a predetermined synchronization signal from a synchronization signal generation circuit (2) are provided.

In this case, the solid-state image pickup device portion (1) is provided with light receiving portions (5), (5), ... (5) formed of photodiodes in a matrix on one main surface side of the P-type silicon substrate (4), and
In order to transfer the charges accumulated in these light receiving portions (5) (5) ... (5) in the vertical direction (upward or downward on the paper surface) for each row of these light receiving portions (5) (5). Vertical register parts (6), (6), ... (6) of the light receiving parts (5), (5) ,.
Adjacent to (5), the read gate section (7) (7)
Provided via (7), and also vertical register section (6) (6)
... These vertical register parts (6) on one end side of (6)
(6) A horizontal register section (8) is provided for horizontally transferring the charges transferred from (6) downward in the plane of the drawing, and this horizontal register section (8) is also provided. A charge detector (9) for detecting charges transferred from the horizontal register (8) is provided on the output side of
A video signal can be obtained from the output terminal (10) derived from the charge detection unit (9), and
A drain region portion (12) is provided on the other end side of the vertical register portions (6), (6), ... (6) through the sweep gate portions (11), (11) ,. The charges transferred from the vertical register sections (6) (6) ... (6) can be swept out as unnecessary charges.

As shown in FIG. 5, the light receiving part (5) is provided with a charge storage region (13) consisting of an N type region on one main surface side of the P type silicon substrate (4) and the charge storage region (13). )above
It is configured by providing an insulating layer (14) made of a SiO ₂ layer. still,
Although not shown in FIG. 4, (15), (16) and (17) respectively indicate an overflow control gate region composed of a P type region, an overflow drain region composed of an N ⁺ region and a P ⁺ type region. It is the channel stop area.

Further, as shown in FIGS. 5 and 6, the vertical register portion (6) includes an N-type region close to the charge storage region (13) on one main surface side of the P-type silicon substrate (4). A transfer region (18) is provided and a transfer electrode (19) made of polycrystalline silicon is provided on the charge transfer region (18) via an insulating layer (14).
A ₁ ) (19A ₂ ) (19A ₃ ) (19A ₄ ) (19A ₁ ) ... (19A ₄ ). In this case, these transfer electrodes (19A ₁ )
(19A ₂ ) (19A ₃ ) (19A ₄ ) (19A ₁ ) ... (19A ₄ ) is a four-phase drive for normal speed forward transfer for transferring charges toward the horizontal register section (8) at normal speed. Pulse φv ₁ , φv ₂ , φ
v ₃ , φv ₄ and 4-phase drive pulse φ for high-speed reverse transfer for transferring charges toward the drain region (12) at high speed
v ′ ₁ , φv ′ ₂ , φv ′ ₃ and φv ′ ₄ are selectively supplied. A P ⁺ type region (20) for preventing smear is provided below the charge transfer region (18).

Further, the read gate section (7) provided between the light receiving section (5) and the vertical register section (6), as shown in FIG.
A read gate region (21) is provided between the charge storage region (13) and the charge transfer region (18), and a read gate electrode (22) is provided on the read gate region (21) via an insulating layer (14). It is provided and configured. In this case, in the read gate electrode (22), one end of the transfer electrodes (19A ₁ ) (19A ₃ ) of the vertical register section (6) is read gate region (21).
The readout gate electrode (2
The charge accumulated in the charge accumulation region (13) of the light receiving part (5) by selectively supplying the unnecessary charge read pulse P ₁ and the signal charge read pulse P ₂ to the vertical charge register part (6). The charge transfer area (18) can be read out.

The horizontal register section (8) is provided with a charge transfer area (23) consisting of an N-type area connected to the charge transfer area (18) of the vertical register section (6) as shown in FIG. Transfer electrodes (24) (24) (...) (2) made of polycrystalline silicon on the charge transfer region (23) via an insulating layer (14).
4) is provided and configured. In this case, transfer electrodes (24) (2
4) (24) are arranged so that the horizontal register section (8) can be driven by the two-layer drive pulses φH ₁ and φH ₂ .
Incidentally, (40) is a channel stop region.

Although not shown in detail, the charge detection unit (9) is composed of, for example, a floating diffusion amplifier.

Further, as shown in FIG. 6, the sweep-out gate section (11) is provided with a sweep-out gate area (25) consisting of an N-type area connected to the charge transfer area (18) of the vertical register section (6) and this sweep-out gate area ( 25), a sweep gate electrode (26) made of polycrystalline silicon is provided on the insulating layer (14). In this case, the sweep gate electrode (26) is grounded.

In addition, the drain region (12) is the sweep gate region (2
Adjacent to 5), an N ⁺⁺ region (27) formed by diffusing N-type impurities at a high concentration is provided.

Further, the timing generator (3) includes the unnecessary charge read pulse P ₁ and the signal charge read pulse P ₂ supplied to the read gate sections (7), (7), ... (7), and the vertical register section (6) (6). 1577 kHz supplied to (6)
(F _sc / 227, where f _sc = 3.58 MHz) 4-phase drive pulse for normal speed positive transfer φv ₁ , φv ₂ , φv ₃ , φv ₄ and 557 kHz (f _sc /
6) High-speed reverse transfer 4-phase drive pulse φv ′ ₁ , φv ′ ₂ ,
Supply φv ′ ₃ and φv ′ ₄ to the horizontal register section (8)
It is configured to generate 9.5 MHz two-phase drive pulses φH ₁ and φH ₂ .

The conventional solid-state imaging device configured as described above operates as follows.

First, when the normal mode is selected as the exposure time mode, that is, the mode in which the exposure time is one field period is selected, as shown in FIG. 7B, signal charges are generated at required time points within the vertical blanking period for each field. The read pulse P ₂ is supplied to the read gate sections (7), (7), ... (7),
Light-receiving part (5) (5) by exposure for one field period
The charges accumulated in (5) are read out as signal charges into the vertical register sections (6), (6), ... (6). Then, as shown in FIG. 7C, the read gate sections (7), (7), ...
Following the supply of the signal charge read pulse P ₂ to (7), a 15.77 kHz four-phase drive pulse φv ₁ for normal speed positive transfer,
φv ₂ , φv ₃ , and φv ₄ are terminals (28A ₁ ) (28A ₂ ) (28A ₃ ) (28
The charges supplied to the vertical register sections (6), (6), ... (6) via A ₄ ) and read as signal charges are transferred to the horizontal register section (8). The horizontal register section (8) is supplied with 9.5 MHz two-phase drive pulses φH ₁ and φH ₂ via terminals (29A ₁ ) and (29A ₂ ), and the charges read as signal charges are Each horizontal line is transferred to the charge detection unit (9), and a video signal based on this charge is output to the output terminal (10). Incidentally, FIG. 7A shows a vertical synchronizing signal.
Indicates V _SYNC .

Further, when the electronic shutter mode, that is, the mode in which the exposure time is the required time set in the vertical blanking period is selected, as shown in FIG. P ₁ is supplied to the read gate sections (7), (7), ... (7), and the charges accumulated in the light receiving sections (5), (5) ,. 6) (6) ... (6) is read. Then, as shown in FIG. 7E, 557 kHz four-phase drive pulses for high-speed reverse transfer φv ′ ₁ , φv ′ ₂ , φv ′ ₃ ,
.phi.v _'4 is supplied to the vertical register section (6) (6) ‥‥ (6), is read as unnecessary charges charge is swept out to the drain region (12) between the 8 horizontal period. Next, as shown in FIG. 7D, after the required time in the vertical blanking period has elapsed, the signal charge read pulse P ₂ is read by the read gate sections (7), (7) ,. 7)
, And the charges accumulated in the light receiving sections (5), (5), ... (5) after the unnecessary charge reading pulse P _{1 is} supplied to the vertical register sections (6), (6) ,. Subsequently, as shown in FIG. 7E, the 15.77 kHz four-phase drive pulses for normal speed positive transfer φv ₁ , φv ₂ , φv ₃ , and φv ₄ are applied to the vertical register section (6).
(6) The charges supplied to (6) and read as signal charges are transferred to the horizontal register section (8). Therefore, in this case, the required time within the vertical blanking period, that is, the period from the supply of the unnecessary load reading pulse P _{1 to the} supply of the signal charge reading pulse P ₂ , for example, 1/1800 seconds as the exposure time is the light receiving unit ( 5) (5) ... A video signal based on the charges accumulated in (5) is output to the output terminal (10).

As described above, the solid-state image pickup device having such an electronic shutter mechanism can pick up an object moving at high speed without an afterimage without providing a mechanical shutter mechanism. There is an advantage that the size of the video camera can be reduced.

[Problems to be solved by the invention]

However, in such a conventional solid-state imaging device,
There is an inconvenience that an image defect that does not occur when such an electronic shutter mechanism is not provided, that is, a bright spot unrelated to the captured image may appear on the reproduction screen.

As a result of experiments and studies by the inventor, such an image defect was found to be a potential barrier or potential dip in the charge transfer regions (18), (18), ... (18) of the vertical register sections (6), (6). Was found to occur due to these.

An example of the case where such an image defect occurs will be described with reference to FIG. FIG. 8 is a potential model diagram showing a potential state of a part of the charge transfer region (18) of the vertical register section (6). The solid line (30) shows the potential level and the convex section (31) shows the potential barrier. , And the recess (32) shows a potential dip. That is, in this example, the potential barrier (31) and the potential dip (32) are present in the charge transfer region below the transfer electrode (19A ₃ ′), and the potential dip (32) is particularly the transfer electrode (19A ₄ ′). ) In the vicinity of the charge transfer region.

First, FIG. 8A shows the charges (unnecessary charges) read to the vertical register section (6) by the unnecessary charge read pulse P ₁ .
(33) is a four-phase drive pulse φv ′ ₁ , φ for high-speed reverse transfer
Based on v ′ ₂ , φv ′ ₃ and φv ′ ₄ , the drain region (1
2) Shows the state at a certain point during the transfer,
This state changes as shown in FIG. 8B at the next time point.
In this case, a part of the unnecessary charge (33) is trapped in the potential dip and is accumulated at the one side of the potential barrier (31), that is, the horizontal register section (8) side due to the high speed transfer. I will end up. Then, after a required time, for example, 8 horizontal periods, the unnecessary charges (33) are swept out to the drain region (12), and four-phase drive pulses φv ′ ₁ , φv ′ ₂ , φv ′ ₃ , φv for high-speed reverse transfer. The supply of ′ ₄ ends. In this case, as shown in FIG. 8C, both the unnecessary charge (34) accumulated on one side of the potential barrier (31) and the unnecessary charge (35) trapped in the potential dip (32) remain. Thereafter, the signal charge read pulse P ₂ is supplied to the read gate section (7), and the charges accumulated in the light receiving section (5) after the unnecessary charge read pulse P _{1 is} supplied are read out to the vertical register section (6) as signal charge. Be done. FIG. 8D shows this read-out state. In this case, unnecessary charges (34) accumulated on one side of the potential barrier (31) and unnecessary charges (35) trapped in the potential dip (32). Are mixed in the signal charge (36). Then, four-phase drive pulses for normal speed positive transfer φv ₁ , φv ₂ , φv ₃ , and φv ₄ are supplied to the vertical register section (6), and signal charges (36) mixed with unnecessary charges (34) and (35) are supplied. ) Is integrated with the adjacent signal charge (37) and
The data is transferred to the horizontal register unit (8) through the process shown in FIG. E and FIG. 8F. In this case, since the vertical register part (6) is driven at a normal speed, the other side of the potential barrier (31), that is, the drain region part (12).
No signal charge is accumulated on the side, and the potential dip (32) is crushed by the influence of the edge electric field from the adjacent transfer electrode (19A ₄ ′) in the process shown in FIG. 8F. Therefore, the signal charge is not trapped in this potential dip (32).

As described above, in the conventional solid-state imaging device, a part of the unnecessary charge is mixed in the signal charge, and a bright spot as an image defect appears on the reproduction screen.

 The present invention aims to eliminate such inconvenience.

[Means for solving problems]

A solid-state imaging device according to the present invention is, for example, shown in FIGS.
As shown in the figure, during the vertical blanking period, the charges accumulated in the light receiving portions (5), (5), ... (5) by the exposures up to that time are regarded as unnecessary charges, and the vertical register portions (6), (6) ,. ...
Read to (6), then this vertical register (6)
(6) ..... (6) with drive pulse φv ″ ₁ for high-speed reverse transfer,
By supplying φv ″ ₂ , φv ″ ₃ , and φv ″ ₄ to drive the vertical register portions (6) (6) ... (6) at high-speed reverse transfer, unnecessary charges are transferred to the drain region (12). The charges accumulated in the light receiving parts (5), (5), ... (5) by the exposure after the sweeping out and the reading of the unnecessary charges into the vertical register parts (6), (6), ... (6) are performed. The vertical register section (6) (6) (6) ... (6) is read as signal charge, and subsequently the charge to be the signal charge is read in the vertical register section (6).
(6) ... In the solid-state imaging device configured to transfer to the charge detection unit (9) via the horizontal register unit (8) and the horizontal register unit (8), sweep out unnecessary charges to the drain region (12). Drive signal φ for high-speed positive transfer to the vertical register units (6) (6) (6) (6) before reading the signal charges into the vertical register units (6) (6) (6) (6).
By supplying v ₁ , φv ₂ , φv ₃ , and φv ₄ , the vertical register sections (6), (6), ... (6) are driven at high speed forward transfer.

[Action]

In the present invention, after the unnecessary charges are swept out to the drain region (12) and before the charges to be signal charges are read out to the vertical register units (6) (6). The vertical register sections (6), (6), ... (6) are supplied to the register sections (6), (6), ... (6) by supplying the drive pulses φv ₁ , φv ₂ , φv ₃ , φv ₄ for high-speed positive transfer. Since the high-speed forward transfer drive is performed, the vertical register sections (6) (6) ...
(6) Drive pulses for high-speed reverse transfer φv ″ ₁ , φv ″ ₂ ,
Supplying φv ″ ₃ and φv ″ ₄ to this vertical register section (6)
(6) ... When (6) is driven by high-speed reverse transfer, vertical register sections (6) (6) ... as shown in Fig. 3, for example.
Charge transfer regions (18) (18) of (6) ... Unnecessary charges (34) and potential dips accumulated in the potential barrier (31) of (18), especially transfer electrodes adjacent to the horizontal register (8) side. Unnecessary charges (35) trapped in the potential dip (32) existing in the vicinity of the charge transfer region below the are transferred at high speed to the horizontal register section (8),
These unnecessary charges (34) and (35) are read out as signal charges and do not mix with the charges.

Therefore, in the present invention, the vertical register section (6)
(6) Charge transfer area of (6) (18) (18) (1)
The bright spots, which are image defects appearing on the playback screen due to the potential dip of the potential barrier existing in 8), are greatly reduced.

〔Example〕

An embodiment of the solid-state image pickup device of the present invention will be described below with reference to FIGS. 1 to 3, parts corresponding to those in FIGS. 4 to 8 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1, the solid-state image pickup device of this example has a light receiving section (5) (5) ... On the one main surface side of a P-type silicon substrate (4).
(5), read gate sections (7), (7), ... (7), vertical register sections (6), (6), ... (6), horizontal register section (8), charge detection section (9) and drain area The solid-state imaging device section (1) including a section (12) and the like, and a timing generator (38) driven by receiving a predetermined synchronization signal from the synchronization signal generation circuit (2).

In this case, the solid-state image pickup device section (1) is constructed similarly to the conventional example shown in FIG.

The timing generator (38) also includes the unnecessary charge read pulse P ₁ and the signal charge read pulse P ₂ supplied to the read gate sections (7), (7), ... (7), and the vertical register sections (6) and (6). 1577 kHz supplied to (6)
(F _SC / 227, where f _SC = 3.58 MHz) 4-phase drive pulse for normal speed forward transfer φv ₁ , φv ₂ , φv ₃ , φv ₄ , 895 kHz (f _SC / 4) 4-phase drive for high-speed reverse transfer Pulse φv ″ ₁ , φv ″ ₂ , φ
v ″ ₃ , φv ″ ₄ and 1790kHz (f _SC / 2) for high speed positive transfer 4
Phase drive pulses φv ₁ , φv ₂ , φv ₃ , φv ₄ ,
It is constructed so that it can generate two-phase drive pulses φH ₁ and φH ₂ of 9.5 MHz to be supplied to the horizontal register section (8), and operates as described below.

First, the normal mode is selected, that is, the exposure time is set to one field period, and the light receiving unit (5) is set during this one field period.
(5) In the case of obtaining a video signal based on the charges accumulated in (5), as shown in FIG. 2B, the signal charge is generated at a required time point within the vertical blanking period for each field. Read out the read pulse P ₁ (7) (7)
(7) is supplied to the vertical register sections (6), (6), ... (6), and the charges accumulated in the light receiving sections (5), (5) ,. . Then, as shown in FIG. 2C, the read gate sections (7), (7) ...
Following the supply of the signal charge read pulse P ₂ to (7), a 15.77 kHz four-phase drive pulse φv ₁ for normal speed positive transfer,
φv ₂ , φv ₃ , and φv ₄ are vertical register units (6) (6).
It is supplied to (6) and the electric charges are transferred to the horizontal register section (8). Here, the horizontal register (8) is always 2 9.5MHz.
The phase drive pulses φH ₁ and φH ₂ are supplied so that the charges transferred from the vertical register sections (6) (6) (6) (6) are transferred to the charge detection section (9) for each horizontal line, A video signal based on this charge is output to the output terminal (10).
Incidentally, FIG. 2A shows the vertical synchronizing signal V _SYNC .

When the electronic shutter mode is selected, that is, the required time within the vertical blanking period is set as the exposure time,
In order to obtain a video signal based on the charges accumulated in the light receiving portions (5), (5), ... (5) during this exposure time, as shown in FIG. 2D, during the vertical blanking period. Then, the unnecessary charge read pulse P ₁ is supplied to the read gate sections (7), (7), ... (7), and the charges accumulated in the light receiving sections (5), (5) ,. The vertical registers (6), (6), ... (6) are caused to read out as unnecessary charges. Subsequently, as shown in FIG. 2E, a four-phase drive pulse φv ″ ₁ , φv ″ ₂ , φv ″ ₃ , φv ″ ₄ for high-speed reverse transfer of 895 kHz.
Are supplied to the vertical register sections (6), (6), ... (6), and the charges read as unnecessary charges are swept out to the drain region section (12) during the 6.1 horizontal period. Next, as shown in FIG. 2E, a four-phase drive pulse φv ₁ for high-speed positive transfer of 1790 kHz,
φv ₂ , φv ₃ , and φv ₄ are vertical register units (6)
(6) Supply to (6), vertical register (6)
(6) ... (6) is driven at high speed forward transfer for 2.7 horizontal periods. Next, as shown in FIG. 2D, as in the case of FIG. 2B, the signal charge read pulse P ₂ is supplied to the read gate sections (7), (7) ,. _The vertical register sections (6) and (6) use the charges accumulated in the light receiving sections (5), (5), ...
(6) Read it. Then, as shown in Fig. 2E.
15.77kHz four-phase drive pulse for normal speed positive transfer φv ₁ , φv ₂ ,
.phi.v _3, and supplied to the vertical register section _{φv 4 (6) (6)} ‥‥ (6), to transfer the charges read as a signal charge to the horizontal register section (8). In this case, the period from the supply of the unnecessary charge reading pulse P _{1 to the} supply of the signal charge reading pulse P ₂ , for example, 1/1800 seconds is stored as an exposure time in the light receiving units (5), (5), ... (5). A video signal based on the generated charges is output to the output terminal (10).

Others are the same as those of the conventional example shown in FIG. 4 (FIGS. 5 and 6).

In the solid-state imaging device of this example configured as above,
As shown in FIG. 3, even if the potential barrier (31) and the potential dip (32) are present at the same positions as in the conventional example of FIG. 4, the image defect caused by these does not occur. Hereinafter, this point will be described with reference to FIG.

FIG. 3A shows the charges (unnecessary charges) (33) read to the vertical register section (6) by the unnecessary charge reading pulse P ₁ .
Are high-speed reverse transfer 4-phase drive pulses φv ″ ₁ , φv ″ ₂ , φ
A state at a certain point in the process of being transferred to the drain region (12) based on v ″ ₃ and φv ″ ₄ is shown. This state changes to the state shown in FIG. 3B at the next point in time, Further, the unnecessary charges (33) are swept out to the drain region (12) through a predetermined process (not shown). In this case, as shown in FIG. 3B, some of the unnecessary charges are accumulated on one side of the potential barrier (31), that is, on the horizontal register section (8) side, and are trapped in the potential dip (32). Fig. 3C
As shown in, four-phase drive pulses φv ₁ and φv for high-speed positive transfer
_It remains even after the supply of ₂ , φv ₃ and φv ₄ is completed. However, in this example, 4 for high-speed reverse transfer is used.
Supply of phase drive pulses φv ″ ₁ , φv ″ ₂ , φv ″ ₃ , φv ″ ₄ followed by four-phase drive pulses φv ₁ , φ for high-speed positive transfer
Since v ₂ , φv ₃ and φv ₄ are supplied and the vertical register section (6) is driven so as to transfer the charges to the horizontal register section (8) side, the transfer electrode (19
The potential dip (32) near the charge transfer region below A ₄ ′) is crushed by the influence of the edge electric field from the transfer electrode (19A ₄ ′) side and trapped unwanted charges (35)
Are discharged to the charge transfer region below the transfer electrode (19A ₄ ′), and thereafter, the unnecessary charges (35) are removed from the horizontal register section (8).
Barrier transferred to (31)
When the unnecessary charges (34) accumulated on one side are also transferred to the horizontal register section (8) and the supply of the four-phase drive pulses φv ₁ , φv ₂ , φv ₃ , φv ₄ for high-speed positive transfer is completed. Then, as shown in FIG. 3E, the unnecessary charges (35) trapped in the potential dip (32) and the unnecessary charges (34) accumulated in the potential barrier (31) are completely stored in the horizontal register section (8). Will be transferred to. After that, in this example, as shown in FIG. 3F, the signal charge read pulse P ₂ is applied to the read gate sections (7) (7).
The charges accumulated in the light receiving portions (5), (5), ... (5) after being supplied to (7) and the unnecessary charge reading pulse P ₁ are read out to the vertical register portion (6) as signal charges. Since the unnecessary charges (34) and (35) do not remain, the unnecessary charges (34) and (35) do not mix with the signal charges. After that, the normal-phase positive transfer four-phase drive pulses φv ₁ , φv ₂ , φv ₃ , and φv ₄ are supplied to the vertical register section (6), and the charges read as signal charges are shown in FIG. The data is transferred to the horizontal register section (8) through the process shown in FIG. 3H. In this case, since the vertical register section (6) is driven at a normal speed, the signal charge is not accumulated on the other side of the potential barrier (31), that is, the drain region section (12) side, and the potential dip (32 ) Is crushed by the influence of the edge electric field from the transfer electrode (19A ₄ ′) side adjacent to the horizontal register section (8) side in the process as shown in FIG. 3H, the potential dip (32) The signal charge is not trapped in.

As described above, in the solid-state imaging device of this example, the potential barrier (eg, potential barrier (31) exists below the transfer electrode (19A ₃ ′) in the charge transfer region (18) of the vertical register section (6), and the high speed Even if some of the unnecessary charges may be accumulated on one side of the potential barrier (31) during reverse transfer, the unnecessary charges (34) are transferred to the horizontal register section (8) before reading the signal charges. Because it will be done
It is possible to prevent image defects (generation of bright spots) caused by such unwanted charges (34) being mixed in the signal charges.

Further, even if there is a potential dip and unnecessary charges are trapped in this potential dip, this potential dip is in the vicinity of the charge transfer region below the transfer electrode adjacent to the horizontal register section (8) side. When, for example, at the position shown in FIG. 3 described above, the signal charge (35) trapped in the potential dip (32) is stored in the horizontal register section (8) before the signal charge is read out. Since they are transferred, it is possible to prevent image defects (generation of bright spots) caused by mixing the unnecessary charges (35) with the signal charges.

Therefore, according to the solid-state imaging device of this example, image defects (generation of bright spots) caused by potential barriers and potential dips existing in the charge transfer region (18) of the vertical register section (6) are significantly reduced. There is a benefit that can be reduced.

In the above embodiment, the frequencies of the four-phase drive pulses φv ″ ₁ , φv ″ ₂ , φv ″ ₃ , φv ″ ₄ for high-speed reverse transfer are set to 85.
9kHz, 4-phase drive pulse for high speed positive transfer φv ₁ , φv
_Although the case where the frequencies of ₂ , φv ₃ , and φv ₄ are set to 1790 kHz has been described, these frequencies are not limited to this, and
Various values can be taken.

Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, even if there is a potential barrier in the charge transfer region of the vertical register portion and a part of unnecessary charges may be accumulated on one side of this potential barrier during high-speed reverse transfer, this unnecessary Since the charges are prevented from being mixed with the signal charges, it is possible to prevent an image defect (generation of bright spots) caused by mixing the unnecessary charges with the signal charges. In addition, even if there is a potential dip and unnecessary charges are trapped in this potential dip at the time of high-speed reverse transfer, this potential dip causes the charge transfer area below the transfer electrode adjacent to the horizontal register section side Since the unnecessary charges are prevented from being mixed with the signal charges when they are in the vicinity, it is possible to prevent image defects (generation of bright spots) caused by mixing the unnecessary charges with the signal charges.

Therefore, according to the present invention, there is an advantage that image defects (generation of bright spots) caused by potential barriers and potential dips existing in the charge transfer region of the vertical register portion can be significantly reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the solid-state imaging device of the present invention, FIG. 2 is a waveform diagram used for explaining the example of FIG. 1, and FIG. 3 is a potential model diagram used for explaining the example of FIG. , 4th
FIG. 5 is a schematic configuration diagram showing a conventional solid-state image pickup device, FIG. 5 is a sectional view taken along line VV 'of FIG. 4, and FIG. 6 is VI-VI' of FIG.
FIG. 7 is a waveform diagram for explaining the example of FIG. 4, and FIG. 8 is a potential model diagram for explaining the example of FIG. (1) is a solid-state image sensor section, (3) and (38) are timing generators, (5) is a light receiving section, (6) is a vertical register section, (7) is a reading gate section, and (8) is horizontal. A register section, (9) is a charge detection section, (11) is a sweep gate section, (12) is a drain area section, and (18) is a charge transfer area of a vertical register section.

Claims (1)

(57) [Claims] 1. Within the vertical blanking period, the charges accumulated in the light receiving unit by the exposures up to that time are read as unnecessary charges into the vertical register unit, and then a drive pulse for high speed reverse transfer is supplied to the vertical register unit. By sweeping the vertical register section at high speed in reverse, the unnecessary charge is swept out to the drain area, and then the unnecessary charge is stored in the light receiving section by exposure after being read out to the vertical register section. In the solid-state imaging device configured to read the generated charges as signal charges to the vertical register unit, and subsequently transfer the charges to be the signal charges to the charge detection unit via the vertical register unit and the horizontal register unit, After sweeping the unwanted charge into the drain region, and before reading the signal charge into the vertical register, The solid-state imaging device being characterized in that the manner is fast forward transfer driving the vertical register section supplies a fast forward transfer drive pulses to the register unit.