JP2526895B2 - Solid-state imaging device - Google Patents

Description

The present invention relates to an interline transfer type solid-state imaging device having an electronic shutter mechanism.

[Outline of Invention]

The present invention is an interline transfer type solid-state imaging device having an electronic shutter mechanism, wherein during the vertical blanking period, the charges accumulated in the light receiving unit by the exposure up to that time are read to the vertical register unit as unnecessary charges, Subsequently, the vertical register section is driven at a high speed reverse transfer to sweep out unnecessary charges to the drain region section, and then the unnecessary charges are read out to the vertical register section and then accumulated in the light receiving section by exposure. In the solid-state imaging device configured to read out electric charges as signal charges to the vertical register unit and then transfer the charges to be the signal charges to the charge detection unit via the vertical register unit and the horizontal register unit, the drain of the vertical register unit A charge storage unit is provided on the side of the region to store a part of the unnecessary charges swept out to the drain region, or from the drain region Allows injection of charges into the direct register section, sweeps out unnecessary charges to the drain area, and then drives the vertical register section at high speed forward transfer to inject from the charge accumulated in the charge accumulation section or the drain area. Even if there is a potential dip in the charge transfer region of the vertical register by transferring the generated charge to the horizontal register and then reading out the signal charge from the light receiving unit to the vertical register. The potential dips are set so that the signal charges are not trapped so that black dots, which are image defects, do not appear.

[Conventional technology]

Conventionally, an interline transfer type solid-state imaging device having an electronic shutter mechanism has been proposed as shown in FIG.

This solid-state imaging device has a normal mode and an electronic shutter mode as an exposure time mode, can set one field period as the exposure time, and can set a required time within the vertical blanking period as the exposure time. As shown in FIG. 9, it comprises a solid-state image sensor (1) and a timing generator (3) which is driven by a supply of a predetermined synchronizing signal from a synchronizing signal generating circuit (2).

In this case, the solid-state imaging device (1) is provided with light receiving portions (5) made of photodiodes in a matrix on one main surface side of the P-type silicon substrate (4), and the charges accumulated in these light receiving portions (5). A vertical register unit (6) for transferring each of the light receiving units (5) in the vertical direction (upward or downward of the paper surface) is provided via the read gate unit (7), and the vertical register unit (6) A horizontal register unit (8) for horizontally transferring the electric charges transferred downward from the vertical register unit (6) for each horizontal line is provided at one end side, and the horizontal register unit (8) is also provided. A charge detection unit (9) for detecting charges transferred from the horizontal register unit (8) is provided on the output side of 8),
A video signal is obtained at the output terminal (10) derived from the charge detection section (9), and a vertical gate section (6) and a sweep gate section (11) on the other end side are provided.
The drain region portion (12) is provided via the via so that the electric charges transferred to the vertical register portion (6) upward in the drawing can be swept out as unnecessary electric charges.

As shown in FIG. 10, the light receiving part (5) is provided with a charge storage region (13) consisting of an N-type region on one main surface side of the P-type silicon substrate (4) and the charge storage region (13). )above
It is configured by providing an insulating layer (14) made of a SiO ₂ layer. still,
(15), (16) and (17) are not shown in FIG.
The overflow control gate region is a P-type region, the overflow drain region is an N ⁺ region, and the channel stop region is a P ⁺ -type region.

Further, as shown in FIG. 10 and FIG. 11, the vertical register portion (6) is composed of an N-type region close to the charge storage region (13) on one main surface side of the P-type silicon substrate (4). A transfer region (18) is provided and a transfer electrode (19) made of polycrystalline silicon is provided on the charge transfer region (18) via an insulating layer (14).
A ₁ ) (19A ₂ ) (19A ₃ ) (19A ₄ ) are provided. In this case, these transfer electrodes (19A ₁ ) (19A ₂ ) (19A ₃ ) (19
A ₄ ) includes four-phase drive pulses φ _V1 , φ _V2 , φ _V3 , φ _V4 for normal speed positive transfer for transferring the charges to the horizontal register section (8) at the normal speed, and the charges in the drain area section. (12)
High-speed reverse transfer four-phase drive pulse for high speed transfer toward ▲ φ ^′ _V1 ▼, ▲ φ ^′ _V2 ▼, ▲ φ ^′ _V3 ▼, ▲ φ ^′
_V4 and are selectively supplied. Charge transfer area (18)
A P ⁺ type region (20) for preventing smear is provided below the.

Further, as shown in FIG. 10, the read gate section (7) provided between the light receiving section (5) and the vertical register section (6) has a charge storage area (13) and a charge transfer area (18). A read gate region (21) is provided therebetween, and a read gate electrode (22) is provided on the read gate region (21) via an insulating layer (14). In this case, the read gate electrode (22) is formed by extending one end of the transfer electrodes (19A ₁ ) (19A ₃ ) of the vertical register section (6) over the read gate region (21). The unnecessary charge read pulse P ₁ and the signal charge read pulse P ₂ are selectively supplied to the electrode (22) to charge the charges accumulated in the charge accumulation region (13) of the light receiving unit (5) to the vertical register unit. The data can be read out to the charge transfer area (18) of (6).

The horizontal register section (8) is provided with a charge transfer area (23) consisting of an N-type area connected to the charge transfer area (18) of the vertical register section (6) as shown in FIG. A transfer electrode (24) made of polycrystalline silicon is provided on the charge transfer region (23) via an insulating layer (14). In this case, the transfer electrode (24) is a two-layer drive pulse φ _H2
And φ _H2 , a plurality of them are arranged so that this horizontal register unit (8) can be driven. Incidentally, (40) is a channel stop region.

Although not shown in detail, the charge detection unit (9) is composed of, for example, a floating diffusion amplifier.

Further, as shown in FIG. 11, the sweep-out gate section (11) is provided with a sweep-out gate area (25) consisting of an N-type area connected to the charge transfer area (18) of the vertical register section (6), and the sweep-out gate area (25 25), a sweep gate electrode (26) made of polycrystalline silicon is provided on the insulating layer (14). In this case, the sweep gate electrode (26) is grounded.

In addition, the drain region (12) is the sweep gate region (2
Adjacent to 5), an N ⁺⁺ type region formed by diffusing N type impurities in a high concentration is provided.

Further, the timing generator (3) supplies unnecessary charge read pulse P ₁ and signal charge read pulse P ₂ to the read gate section (7) and 15.77 kHz (f sc / 227, fsc / 227, which is supplied to the vertical register section (6). However, f sc = 3.58MHz)
4 phase drive pulse for normal speed positive transfer of φ _V1 , φ _V2 , φ _V3 , φ _V4
And 557kHz (f sc / 6) 4-phase drive pulse for high-speed reverse transfer ▲
Φ ^′ _V1 ▼, ▲ φ ^′ _V2 ▼, ▲ φ ^′ _V3 ▼, ▲ φ ^′ _V4 ▼ and two-phase drive pulses φ _H1 and φ _{H2 of} 9.5 MHz to be supplied to the horizontal register section (8) Is composed of.

The conventional solid-state imaging device configured as described above operates as follows.

First, when the normal mode is selected as the exposure time mode, that is, the mode in which the exposure time is one field period is selected, as shown in FIG. 12B, the signal charge is generated for each field in the required time within the vertical blanking period. The read pulse P ₂ is supplied to the read gate section (7), and the charges accumulated in the light receiving section (5) during the exposure for one field period are read out to the vertical register section (6) as signal charges. Then, the 12th
As shown in Fig. C, the 15.77 kHz four-phase drive pulses for normal speed positive transfer φ _V1 , φ _V2 , φ _V3 , and φ _V4 are applied to the terminals (27A ₁ ) (27A ₂ ) (27A
₃ ) The charges supplied to the vertical register unit (6) via (27A ₄ ) and read as signal charges are transferred to the horizontal register unit (8). Here in the horizontal register section (8)
Two-phase drive pulses φ _H1 and φ _{H2 of} 9.5 MHz are supplied via terminals (28A ₁ ) and (28A ₂ ), and the charges read out as signal charges are stored in the charge detection unit (9 ), And the video signal based on this charge is output to the output terminal (10).
Is output to Incidentally, FIG. 12A shows the vertical synchronizing signal V _{SY NC} .

Further, when the electronic shutter mode, that is, the mode in which the exposure time is the required time set in the vertical blanking period is selected, the unnecessary charge read pulse is generated in the vertical blanking period as shown in FIG. 12D. P ₁ is supplied to the read gate section (7), and the electric charge accumulated up to that time in the light receiving section (5) is read out to the vertical register section (6) as unnecessary charge. Then, as shown in FIG. 12E, 557 kHz four-phase drive pulse for high-speed reverse transfer ▲ φ ^′ _V1 ▼, ▲ φ ^′ _V2 ▼, ▲
The φ ^′ _V3 ▼ and ▲ φ ^′ _V4 ▼ are supplied to the vertical register section (6), and the charges read as unnecessary charges are swept out to the drain region section (12) during 8 horizontal periods. Next, as shown in FIG. 12D, after the required time in the vertical blanking period has elapsed, the signal charge read pulse P ₂ is supplied to the read gate section (7) in the same manner as shown in FIG. The electric charges accumulated in the light receiving section (5) after the read pulse P _{1 is} supplied are read out to the vertical register section (6). Then twelfth
As shown in FIG. E, 15.77 kHz four-phase drive pulses for normal speed positive transfer φ _V1 , φ _V2 , φ _V3 , φ _V4 are supplied to the vertical register section (6), and the charges read as signal charges are horizontally It is transferred to the register unit (8). Therefore, in this case, the required time within the vertical blanking period, that is, the period from after the unnecessary charge read pulse P _{1 is} supplied to before the signal charge read pulse P _{2 is} supplied, for example, 1/1800 seconds is the exposure time,
A video signal based on the charges accumulated in the light receiving section (5) during this exposure time is output to the output terminal (10).

A solid-state imaging device including such an electronic shutter mechanism can image a moving object at high speed without an afterimage without providing a mechanical shutter mechanism. Therefore, when applying this to, for example, a video camera, There is an advantage that it can be downsized.

[Problems to be solved by the invention]

However, in such a conventional solid-state imaging device,
There is an inconvenience that black dots unrelated to the captured image may appear on the reproduction screen.

As a result of experiments and studies by the present inventor, such image defects are
It has been found that when the potential dip exists in the charge transfer region (18) of the vertical register section (6), it occurs due to this.

An example of the case where such an image defect occurs will be described with reference to FIG. FIG. 13 is a potential model diagram showing a potential state of a part of the charge transfer region (18) of the vertical register portion (6), the solid line (29) shows the potential level, and the recessed portion (30) shows the potential dip. ing. That is, in this example, the transfer electrode (19
A ₃ ') potential dip (30 to the charge transfer region below the) and if there is, in particular transfer electrode (19A _2')
This is the case where the potential dip (30) exists near the charge transfer region side below the.

First, FIG. 13A shows the charges (unnecessary charges) read to the vertical register section (6) by the unnecessary charge reading pulse P ₁ .
(31) is a four-phase drive pulse for high-speed reverse transfer ▲ φ ^′ _V1 ▼, ▲ φ
Fig. 13 shows the state at a certain point during the transfer to the drain region (12) based on ^′ _V2 ▼, ▲ φ ^′ _V3 ▼, ▲ φ ^′ _V4 ▼. It changes as shown in B. In the state shown in FIG. 13A, a part (31A) of the unnecessary charge (31) is trapped in the potential dip (30), but when the state shown in FIG. 30) is crushed under the influence of the edge electric field from the transfer electrode (19A ₂ ′), and the unwanted charges (31A) trapped in this potential dip (30) are below the transfer electrode (19A ₂ ′). Will be swept out to the charge transfer area. Therefore, the unnecessary charges (31) are swept out to the drain region (12), and four-phase drive pulses for high-speed reverse transfer ▲ φ ^′ _V1 ▼, ▲ φ ^′ _V2 ▼, ▲ φ ^′ _V3 ▼, ▲ φ ^′ _V4 ▼
When the supply of C is completed, the potential dip (30) becomes an empty state in which no charge is trapped, as shown in FIG. 13C. Thereafter, the signal charge read pulse P ₂ is supplied to the read gate section (7), and the charges accumulated in the light receiving section (5) after the unnecessary charge read pulse P _{1 is} supplied are read out to the vertical register section (6) as signal charge. Be done. Fig. 13D
Shows the read state, but in this case, a part (32A) of the signal charge (32) is trapped in the potential dip (30). After that, the four-phase drive pulses for normal speed positive transfer φ _V1 , φ _V2 , φ _V3 , and φ _V4 are applied to the vertical register section (6).
Signal charge (32) is supplied to the adjacent signal charge (33)
Then, the data is transferred to the horizontal register section (8) through a process as shown in FIGS. 13E and 13F, which shows a part of the process. In this case, as shown in FIG. 13E, since the potential dip (30) and the transfer electrode (19A ₄ ′) are considerably separated from each other, the potential dip (30) is located at this transfer electrode (19A ₄ ′).
It is not crushed by the edge electric field from A ₄ ′),
The electric charge (32A) trapped in the potential dip (30) remains in the potential dip (30) as it is as shown in FIG. 13F.

As described above, in the conventional solid-state imaging device, a part (32A) of the signal charge (32) is trapped in the potential dip (30), and a black spot as an image defect appears on the reproduction screen.

It is an object of the present invention to provide a solid-state imaging device that eliminates such inconvenience.

[Means for solving problems]

In the solid-state imaging device according to the present invention, as shown in, for example, FIG. 1 to FIG. 8, a vertical register is used in which a charge accumulated in the light receiving unit (5) during the vertical blanking period is used as unnecessary charge. (6) is read out, and then the vertical register section (6) is driven at high speed reverse transfer to sweep out the charges to be the unnecessary charges to the drain region section (12), and thereafter the charges to be the unnecessary charges are changed to the vertical register section. The charges accumulated in the light receiving section (5) by the exposure after being read out to (6) are read out to the vertical register section (6) as signal charges, and subsequently the charges to be the signal charges are set to the vertical register section (6) and the horizontal register. In the solid-state imaging device configured to transfer to the charge detection unit (9) via the unit (8), the vertical register unit (6)
The charge accumulation part (34) is provided on the drain region part (12) side to accumulate a part of the unnecessary charges swept out into the drain region part (12), or the drain register part (12) to the vertical register part (6). After the charges to be injected into the drain region (12) have been swept out, the vertical register (6) is driven at high-speed positive transfer and accumulated in the charge accumulator (34). Alternatively, the charges injected from the drain region part (12) are transferred to the horizontal register part (8), and then the charges used as signal charges from the light receiving part (5) are added to the vertical register part (6).
It is designed to be read out.

[Action]

In the present invention, after sweeping out unnecessary charges to the drain region (12), the vertical register (6)
The high-speed positive transfer drive is performed to transfer the charges accumulated in the charge accumulating portion (34) or the charges injected from the drain region portion (12) to the horizontal register portion (8). Even if there is a potential dip (30) in (18), this potential dip (30) is the charge or drain region part (12) accumulated in the charge accumulation part (34).
It is filled with the electric charge injected from. Therefore, after that, when the charge as the signal charge is read out and transferred to the horizontal register section (8), the charge as the signal charge is not trapped in the potential dip (30). Therefore, in the present invention, a black dot which is an image defect due to the potential dip (30) existing in the charge transfer region (18) of the vertical register section (6) does not appear.

〔Example〕

An embodiment of the solid-state imaging device of the present invention will be described below with reference to FIGS. 1 to 7, parts corresponding to those in FIGS. 9 to 13 are designated by the same reference numerals, and detailed description thereof will be omitted.

As shown in FIG. 1, the solid-state imaging device of this example has a light receiving part (5), a reading gate part (7), a vertical register part (6), a horizontal part on a main surface side of a P-type silicon substrate (4). A solid-state image sensor (1) including a register section (8), a charge detection section (9), a drain region section (12), etc. and a synchronization signal generation circuit (2) are supplied with a predetermined synchronization signal for driving. Timing generator (35).

In this case, the solid-state imaging device (1) is provided with a terminal (26A) as shown in FIGS. 1 and 2, and a charge injection pulse generated by a timing generator (35) described later through this terminal (26A). P ₃ can be supplied to the sweep gate electrode (26) of the sweep gate section (11), and the others are configured in the same manner as in the conventional example of FIG.

 The timing generator (35) also has a readout
Unnecessary charge read pulse P supplied to the gate section (7)₁as well as
Signal charge read pulse P₂And in the vertical register section (6)
Supply 15.77kHz (f sc / 227, but f sc = 3.58MHz)
Normal-speed positive transfer 4-phase drive pulse φ_V1, φ_V2, φ_V3, φ_V4, 89
4kHz drive pulse for high-speed reverse transfer of 5kHz (f sc / 4) ▲ φ^″ _V1
▼, ▲ φ^″ _V2▼, ▲ φ^″ _V3▼, ▲ φ^″ _V4▼ and 1790kHz
(F sc / 2) 4-phase drive pulse for high-speed forward transfer ▲ φ _V1▼ 、
▲ φ _V2▼, ▲ φ _V3▼, ▲ φ _V4▼, Horizontal register
Two-phase drive pulse φ of 9.5MHz supplied to (8)_H1And φ_H2
To be able to occur. In this case, 4 phases for normal speed forward transfer
Drive pulse φ_V1, φ_V2, φ_V3, φ_V4, 4 phase drive for high speed reverse transfer
Motion pulse ▲ φ^″ _V1▼, ▲ φ^″ _V2▼, ▲ φ^″ _V3▼, ▲ φ^″
_V4▼ and 4-phase drive pulse for high-speed forward transfer ▲ φ _V1▼, ▲ φ
_V2▼, ▲ φ _V3▼, ▲ φ _V4▼ is Fig. 3 and Fig. 4, respectively
And has a waveform as shown in FIG. Furthermore,
This timing generator (35) has a specified positive voltage value.
Charge injection pulse P with₃Is generated as shown in Fig. 2.
As shown, this charge injection pulse P₃Sweep out gate electrode
Supply to (26) and sweep out gate area (25) potency
Local level to the potential level of the drain region (12).
The depth of the drain region (12) to sweep out the electric charge.
This sweep gate area through the gate area (25)
Transfer electrode (19A) adjacent to (25)_Four) Lower charge transfer area
Allows injection into (18A) and operates as described below
Let

First, the normal mode is selected, that is, the exposure time is set to one field period, and the light receiving unit (5) is set during this one field period.
In order to obtain a video signal based on the charges accumulated in the signal charge reading pulse P ₂ at a required time point within the vertical blanking period for each field, as shown in FIG. 6B.
Is supplied to the reading gate section (7) to cause the vertical register section (6) to read the charge accumulated in the light receiving section (5) during the exposure for one field period. Then, as shown in FIG. 6C, 1
4.77kHz normal-speed positive transfer 4-phase drive pulse φ _V1 , φ _V2 , φ
_V3 and φ _V4 are supplied to the vertical register section (6) to transfer the charges to the horizontal register section (8). Here, the horizontal register section (8) is always supplied with the two-phase drive pulses φ _H1 and φ _H2 of 9.5 MHz, and the charge transferred from the vertical register section (6) is detected in each horizontal line. The video signal based on this charge is output to the output terminal (10). Note that FIG. 6 A shows a vertical synchronization signal V _{SY NC.}

 If you select the electronic shutter mode,
Set the required time within the ranking period as the exposure time,
Based on the charge accumulated in the light receiving part (5) during this exposure time,
In case of trying to obtain the following video signal, it is shown in FIG. 6D.
Unnecessary charges are read out during the vertical blanking period
Pulse P₁Is supplied to the reading gate section (7),
At this time, the charges accumulated in the light receiving part (5) are dropped as unnecessary charges.
The direct register unit (6) reads it. Then in Figure 6E.
As shown, 895kHz 4-phase drive pulse for high-speed reverse transfer ▲ φ^″
_V1▼, ▲ φ^″ _V2▼, ▲ φ^″ _V3▼, ▲ φ^″ _V4▼ vertical cash register
Charges supplied to the star unit (6) and read out as unnecessary charges
Swept out into the drain region (12) during the 6.1 horizontal period
Let Next, as shown in FIG. 6F, a charge injection pulse P₃Sweep out
Supply to discharge gate electrode (26) and sweep out gate area
The potential level of (25) is the same as that of the drain region (12).
Deeper than the potential level, drain region (1
Sweep a certain amount of charge from 2) and adjoin the gate area (25)
Contact transfer electrode (19A_Four) Note the lower charge transfer area (18A)
Let in. Next, as shown in FIG.
4-phase drive pulse for transfer ▲ φ _V1▼, ▲ φ _V2▼, ▲ φ
_V3▼, ▲ φ _V4Supply ▼ to the vertical register section (6) and
Direct register drive (6) for 2.7 horizontal periods, high-speed forward transfer
The charge injected from the drain region (12) is moved horizontally.
Transfer to the register unit (8). However, the output based on this charge
The signal available at the input terminal (10) should not be used as an image signal.
Try not to. Next, as shown in FIG. 6D, as shown in FIG. 6B.
Signal charge read pulse P₂Read gate
Unnecessary charge read pulse P supplied to the section (7)₁After supply
The charges accumulated in the light receiving section (5) are used as signal charges for vertical recording.
The read is performed by the register unit (6). Then shown in FIG. 6E.
Similarly, a 4-phase drive pulse φ for normal speed positive transfer of 15.77 kHz_V1, φ
_V2, φ_V3, φ_V4Is supplied to the vertical register section (6),
Transfer the charge read as a load to the horizontal register section (8)
Let In this case, unnecessary charge read pulse P₁Supply
After that, the signal charge read pulse P₂Period before supply, for example
For example, the exposure time is 1/1800 seconds and it is accumulated in the light receiving part (5).
The video signal based on the stored charge is output to the output terminal (10).
You.

 Others are the same as those of the conventional example shown in FIG.

In the solid-state imaging device of this example configured as above,
As shown in FIG. 7, even if the potential dip (30) exists at the same position as that shown in FIG. 13, the image defect caused by these does not occur. Hereinafter, this point will be described with reference to FIG.

 FIG. 7A shows an unnecessary charge read pulse P₁By vertical
Electric charge (unnecessary electric charge) read by the transistor (6) (31)
Is a 4-phase drive pulse for high-speed reverse transfer ▲ φ^″ _V1▼, ▲ φ
^″ _V2▼, ▲ φ^″ _V3▼, ▲ φ^″ _V4▼ based on drainage
The state at a certain point during the transfer to the area (12)
This state will change to the state shown in Fig. 7B at the next time.
Unnecessary charge (31)
Are swept out to the drain region (12). Figure 7 here
In the state shown in A, part of the unnecessary charge (31) (13A) is
It will be trapped by the social dip (30),
7 When the state shown in Fig. B is reached, this potential di
Up (30) is the transfer electrode (19A₂′)
It was received and crushed, this potential dip
Unwanted charge (31A) trapped in (30) is transferred.
Pole (19A₂It will be swept up to the charge transfer area under ′).
U Therefore, unnecessary charges (31) are generated in the drain region (12).
Swept out, four-phase drive pulse for high-speed reverse transfer ▲ φ
^″ _V1▼, ▲ φ^″ _V2▼, ▲ φ^″ _V3▼, ▲ φ^″ _V4▼ supply
When finished, as shown in Fig. 7C, the potential
The tip (30) will be empty with no charge trapped.
You. However, in this example, the charge injection pulse
Space P₃Is supplied to the swept gate electrode (26)
The charge (36) is swept out and transferred to the gate area (25).
Sending electrode (19A_Four′) Injected into the lower charge transfer region (18A)
4 phase drive pulse for high speed positive transfer ▲ φ _V1▼ 、
▲ φ _V2▼, ▲ φ _V3▼, ▲ φ _V4▼ is the transfer electrode (19
A₁) (19A₂) (19A₃) (19A_Four) Supplied by this injected
The accumulated charge (36) is transferred to the charge transfer area (18) in the horizontal register section.
Transferred to (8). At this time, FIG. 7D and
Injected to show part of the process in Figure 7E.
Part of the charge (36) (36A) is the potential dip (3A).
Trapped in 0), this potential dip (30)
The inside is filled with this trapped charge (36A)
You. afterwards. In this example, as shown in FIG.
Signal charge read pulse P₂Is supplied to the read gate section (7)
Unnecessary charge readout pulse P supplied₁Light receiving part after supply
The charge accumulated in (5) is used as a signal charge in the vertical register.
44 phase drive for normal speed forward transfer
Pulse φ_V1, φ_V2, φ_V3, φ_V4In the vertical register section (6)
The charges supplied and read out as signal charges are shown in FIG. 7G.
Then, the horizontal registration is performed through the process shown in FIG. 7H.
It is transferred to the star unit (8). In this case, the potential
The inside of the tip (30) is filled with electric charge (36A)
So the signal charge is due to the potential dip (30)
It will not be trapped. In this way
In the solid-state imaging device, the charge of the vertical register unit (6)
There is a potential dip (30) in the transfer area (18)
Even if this is the case, there is no signal on this potential dip (30).
Since it is designed so that the load is not trapped, this potato
The image defect caused by the internal dip (30)
Does not happen.

 In the above embodiment, the sweep gate electrode (2
6) Charge injection pulse P₃To supply a predetermined amount of charge.
Swept out from the in area (12) and adjacent to the gate area (25)
Transfer electrode (19A_Four) Injection into the lower charge transfer area (18A)
And transfer it to the horizontal register section (8)
However, instead of this, it is shown in FIG.
The transfer electrode (19 adjacent to the sweep-out gate region (25)
A_Four) Lower charge transfer region with a relatively high concentration of N-type impurities
Spread to N⁺The mold region (34) and the transfer electrode (19
A_Four) Is a low level voltage, this charge transfer
Potential level of region (34) is swept out and gate region
Make it deeper than the potential level of (25).
This is unnecessary when sweeping out the required charges to the drain region (12)
Make sure that part of the charge remains in this charge transfer region (34).
The charge transfer area (34) of the
High-speed positive transfer pulse for charges accumulated in the transfer area (34) ▲ φ
_V1▼, ▲ φ _V2▼, ▲ φ _V3▼, ▲ φ _V4By ▼
The data may be transferred to the horizontal register section (8).
In this case also, the same effect as described above can be obtained.

 Further, in the above-described embodiment, four-phase drive for high speed reverse transfer
Pulse ▲ φ^″ _V1▼, ▲ φ^″ _V2▼, ▲ φ^″ _V3▼, ▲ φ^″ _V4
The frequency of ▼ is set to 895kHz and 4-phase drive pulse for high-speed positive transfer
▲ φ _V1▼, ▲ φ _V2▼, ▲ φ _V3▼, ▲ φ _V4▼ circumference
The case where the wave number was set to 1790 kHz was described.
The wave number is not limited to this and may take various values.
it can.

Further, the present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.

〔The invention's effect〕

According to the present invention, even if there is a potential dip in the charge transfer region of the vertical register section, the signal charges are not trapped in this potential dip, so that the black dot as an image defect due to this potential dip There is a benefit of not showing up.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the solid-state image pickup device of the present invention, FIG. 2 is a sectional view taken along the line II-II ′ of FIG. 1, and FIG. 3 is a four-phase drive pulse for normal speed positive transfer. Waveform diagram, FIG. 4 is a waveform diagram of a 4-phase drive pulse for high-speed reverse transfer, FIG. 5 is a waveform diagram of a 4-phase drive pulse for high-speed forward transfer, and FIG. 6 is a waveform diagram used to explain the example of FIG. FIG. 7 is a potential model diagram for explaining the example of FIG. 1, FIG. 8 is a sectional view of a main part showing another embodiment of the present invention, and FIG. 9 is a schematic configuration diagram showing a conventional solid-state imaging device. FIG. 10 is a sectional view taken along the line XX ′ in FIG. 9, FIG. 11 is a sectional view taken along the line XI-XI ′ in FIG. 9, and FIG. 12 is a waveform diagram used for explaining the example of FIG. The figure is a potential model diagram for explaining the example of FIG. (1) is a solid-state image sensor, (3) and (35) are timing generators, (5) is a light receiving section, (6) is a vertical register section, (7) is a read gate section, and (8) is a horizontal register. , (9) is a charge detection part, (11) is a sweep gate part, (12) is a drain region part, and (18) is a charge transfer region of a vertical register part.

Claims (1)

(57) [Claims] 1. In the vertical blanking period, the charges accumulated in the light receiving portion by the exposures up to that time are read as unnecessary charges into the vertical register unit, and then the vertical register unit is driven at high speed reverse transfer, thereby eliminating the unnecessary charge. Sweep the charges to be the charges to the drain region, and then read the charges to be the unnecessary charges to the vertical register unit, and read the charges accumulated in the light receiving unit by exposure as signal charges to the vertical register unit, Then, in the solid-state imaging device configured to transfer the charges to be the signal charges to the charge detection unit via the vertical register unit and the horizontal register unit, a charge accumulation unit is provided on the drain region side of the vertical register unit. A part of the unnecessary charge that is provided and swept out to the drain region is accumulated, or the drain region is charged to the vertical register. After the unnecessary charges are swept out to the drain region, the vertical register unit is driven at high speed positive transfer to be injected from the charge accumulated in the charge accumulation unit or the drain region. The solid-state imaging device is characterized in that the charges are transferred to the horizontal register section, and then the charges to be the signal charges are read out from the light receiving section to the vertical register section.