JP2525470Y2 - Semiconductor device - Google Patents

Semiconductor device

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Publication number
JP2525470Y2
JP2525470Y2 JP1990074944U JP7494490U JP2525470Y2 JP 2525470 Y2 JP2525470 Y2 JP 2525470Y2 JP 1990074944 U JP1990074944 U JP 1990074944U JP 7494490 U JP7494490 U JP 7494490U JP 2525470 Y2 JP2525470 Y2 JP 2525470Y2
Authority
JP
Japan
Prior art keywords
source
drain
power mosfet
overcurrent
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP1990074944U
Other languages
Japanese (ja)
Other versions
JPH0432543U (en
Inventor
宰 大岡
弘和 河越
Original Assignee
関西日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 関西日本電気株式会社 filed Critical 関西日本電気株式会社
Priority to JP1990074944U priority Critical patent/JP2525470Y2/en
Publication of JPH0432543U publication Critical patent/JPH0432543U/ja
Application granted granted Critical
Publication of JP2525470Y2 publication Critical patent/JP2525470Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Electronic Switches (AREA)
  • Amplifiers (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

【考案の詳細な説明】 〔産業上の利用分野〕 本考案は半導体装置に関し、詳しくは過電流検出回路
を内蔵した出力用パワーMOS電界効果トランジスタ（以
下、単にパワーMOSFETと称す。）に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial application field] The present invention relates to a semiconductor device, and more particularly, to an output power MOS field effect transistor (hereinafter simply referred to as a power MOSFET) having a built-in overcurrent detection circuit. is there.

〔従来の技術〕[Conventional technology]

例えば、第３図に示すように、出力段に用いられるパ
ワーMOSFET（Ｑ1）においてソース（Ｓ1）とドレイン
（Ｄ1）の間に流れる過電流（ＩO）を検出して保護する
場合、ソース（Ｓ1）に抵抗（ＲO）を接続し、抵抗（Ｒ
O）の両端に発生する電圧降下（ＶO）を検出して過電流
（ＩO）を検出すればよい。ところが、上記検出手段に
よれば、外付けの抵抗（ＲO）による電流損失が大き
く、又、その外付けスペースが必要となって機器が大型
化し、更に抵抗（ＲO）をパワーMOSFET（Ｑ1）と同一素
子に内蔵しても素子が大きくなる。そこで、近年、自動
車用電子部品を用いられるICのように過電流等の異常検
出と共に自己診断や制御機能をIC自身に内蔵したインテ
リジェントICが知られてきている。For example, as shown in FIG. 3, if protected by detecting the overcurrent (I O) flowing between the source in the power MOSFET (Q 1) to be used in the output stage (S 1) and drain (D 1) , The source (S 1 ) is connected to a resistor (R O ), and the resistor (R
O ) may be detected by detecting the voltage drop (V O ) occurring at both ends of O ). However, according to the detection means, the current loss due to the external resistor (R O ) is large, and the external space is required, the device becomes large, and the resistance (R O ) is further reduced by the power MOSFET (QO). Even if built in the same element as in 1 ), the element becomes large. Therefore, in recent years, intelligent ICs have been known which incorporate self-diagnosis and control functions in the ICs themselves as well as detecting abnormalities such as overcurrent, such as ICs using electronic components for automobiles.

上記インテリジェントICにおいてその過電流を検出す
る際、第４図に示すように、検出用のセンスMOSFET（Ｑ
2）を用いる。上記センスMOSFET（Ｑ2）は、多数の単位
MOSFET素子（以下、セルと称す。）と並列・配置して各
セルのソース、ゲート、ドレインを並列結合して単一素
子のパワーMOSFET（Ｑ1）を形成する際、そのセル中か
らいくつかを選択的に取り出したもので、セル数をパワ
ーMOSFET（Ｑ1）に対して例えば1/100に設定する。そし
て、センスMOSFET（Ｑ2）のゲート（Ｇ2）とドレイン
（Ｄ2）をそれぞれパワーMOSFET（Ｑ1）のゲート
（Ｑ1）とドレイン（Ｄ1）に接続すると共に、ソース
（Ｓ2）を検出用抵抗（ＲS）を介してソース（Ｓ1）に
接続し、パワーMOSFET（Ｑ1）とセンスMOSFET（Ｑ2）と
でカレントミラー回路を形成する。When detecting the overcurrent in the intelligent IC, as shown in FIG. 4, a sense MOSFET (Q
2 ) is used. The sense MOSFET (Q 2 ) has a large number of units
When a single element power MOSFET (Q 1 ) is formed by connecting and arranging the source, gate and drain of each cell in parallel by arranging them in parallel with a MOSFET element (hereinafter referred to as a cell), some of the cells are Are selectively extracted, and the number of cells is set to, for example, 1/100 of the power MOSFET (Q 1 ). The gate (G 2 ) and drain (D 2 ) of the sense MOSFET (Q 2 ) are connected to the gate (Q 1 ) and drain (D 1 ) of the power MOSFET (Q 1 ), respectively, and the source (S 2 ) Is connected to the source (S 1 ) via the detection resistor (R S ), and the power MOSFET (Q 1 ) and the sense MOSFET (Q 2 ) form a current mirror circuit.

そこで、パワーMOSFET（Ｑ1）に過電流（ＩO）が流
れ、その1/100（カレントミラー比）の電流（ＩS）がセ
ンスMOSFET（Ｑ2）及び抵抗（ＲS）を流れると、抵抗
（ＲS）の両端に発生する電圧（ＶS）を比較器（CM2）
を含む検出回路により検出して過電流（ＩO）を検出
し、更にその検出信号よりパワーMOSFET（Ｑ1）を遮断
する。Then, when an overcurrent (I O ) flows through the power MOSFET (Q 1 ) and a current (I S ) of 1/100 (current mirror ratio) flows through the sense MOSFET (Q 2 ) and the resistor (R S ), resistance across the voltage generated by the (R S) (V S) to the comparator (CM 2)
The overcurrent (I O ) is detected by the detection circuit including the above, and the power MOSFET (Q 1 ) is cut off from the detection signal.

〔考案が解決しようとする課題〕[Problems to be solved by the invention]

ところで、上述したインテリジェントICのセンスMOSF
ET（Ｑ2）を用いた過電流検出回路によれば、検出に伴
う電流損失はないが、間接的に出力用のパワーMOSFET
（Ｑ1）に流れる過電流（ＩO）を検出しており、又、セ
ンスMOSFET（Ｑ2）のソース（Ｓ2）に検出用抵抗
（ＲS）を接続している分、そのドレイン・ソース電圧
がパワーMOSFET（Ｑ1）のドレイン・ソース電圧よりも
低くなり、理想的なカレントミラー回路を構成すること
が困難で、検出精度及び感度が低下するという不具合が
あった。By the way, the sense MOSF of the intelligent IC mentioned above
According to the overcurrent detection circuit using ET (Q 2 ), there is no current loss due to detection, but the output power MOSFET indirectly
The overcurrent (I O ) flowing through (Q 1 ) is detected, and the detection resistor (R S ) is connected to the source (S 2 ) of the sense MOSFET (Q 2 ). Since the source voltage is lower than the drain-source voltage of the power MOSFET (Q 1 ), it is difficult to form an ideal current mirror circuit, and the detection accuracy and sensitivity are reduced.

〔課題を解決するための手段〕[Means for solving the problem]

本考案は、多数の単位MOS電界効果トランジスタ素子
の並列配置すると共に、上記単位素子の各ソース、ゲー
ト、ドレインをそれぞれ配線により並列結合してソー
ス、ゲート、ドレインを導出し、単一素子を形成した出
力用パワーMOS電界効果トランジスタと、上記単位素子
の各ソース又はドレインの並列結合によって配線に生じ
るソース又はドレインの配線抵抗の両端の電圧降下を検
出して上記パワーMOSFETに流れる過電流を検出する過電
流検出回路部とを同一素子内に形成したことを特徴とす
る。According to the present invention, a large number of unit MOS field-effect transistor elements are arranged in parallel, and the source, gate, and drain of the unit elements are connected in parallel by wiring to derive the source, gate, and drain to form a single element. The output power MOS field-effect transistor and the voltage drop across the wiring resistance of the source or drain generated in the wiring due to the parallel connection of each source or drain of the unit element are detected to detect the overcurrent flowing in the power MOSFET. The overcurrent detection circuit and the overcurrent detection circuit are formed in the same element.

〔作用〕[Action]

上記技術的手段によれば、出力用パワーMOSFETのソー
ス又はドレインの配線抵抗を検出抵抗としてその両端に
発生する電圧からパワーMOSFETに流れる過電流を検出す
る。According to the above technical means, an overcurrent flowing through the power MOSFET is detected from a voltage generated at both ends of the output power MOSFET by using a source or drain wiring resistance as a detection resistor.

〔実施例〕〔Example〕

本考案の実施例を第１図及び第２図を参照して以下に
説明する。第１図は本考案に係る半導体装置としてのIC
（ICO）の要部であるパワーMOSFET（Ｑ1）の素子の平面
図、第２図はIC（ICO）の内部を示す等価回路図で、
（Ｒ1）はパワーMOSFET（Ｑ1）のソースの内部抵抗、
（Ａ）は比較器（CM2）を含む過電流検出回路部であ
る。上記IC（ICO）はパワーMOSFET（Ｑ1）及び過電流検
出回路部（Ａ）を同一素子内に有する。パワーMOSFET
（Ｑ1）は、多数のセル（ＱO）…を並列・配置すると共
に、上記セル（ＱO）…の各ソース、ゲート、ドレイン
をそれぞれ配線により並列結合してソース（Ｓ1）、ゲ
ート（Ｇ1）、ドレイン（Ｄ1）を導出して単一素子を形
成する。ソース配線抵抗（Ｒ1）はセル（ＱO）…の各ソ
ースの配線抵抗を並列結合したものである。過電流検出
回路部（Ａ）は、ソース配線抵抗（Ｒ1）の両端に正逆
相の２入力を接続した比較器（CM2）と、比較器出力よ
り過電流の有無を検出する検出回路（Ａ1）と、検出回
路（Ａ1）の出力からパワーMOSFET（Ｑ1）のON、OFFを
制御すると共に、診断信号（DIAG信号）を出力する論理
回路（Ａ2）と、論理回路（Ａ2）の出力よりパワーMOSF
ET（Ｑ1）を駆動するドライブ回路（Ａ3）とを具備す
る。An embodiment of the present invention will be described below with reference to FIG. 1 and FIG. Fig. 1 shows an IC as a semiconductor device according to the present invention.
FIG. 2 is a plan view of an element of a power MOSFET (Q 1 ) which is a main part of (IC O ), and FIG. 2 is an equivalent circuit diagram showing the inside of IC (IC O ).
(R 1 ) is the internal resistance of the source of the power MOSFET (Q 1 ),
(A) is an overcurrent detection circuit section including a comparator (CM 2 ). The IC (IC O ) has a power MOSFET (Q 1 ) and an overcurrent detection circuit (A) in the same element. Power MOSFET
(Q 1), together with parallel-arranged number of cell (Q O) ..., the cell (Q O) ... each source, gate, parallel coupled to the source by the respective lines and the drain of the (S 1), the gate (G 1 ) and the drain (D 1 ) are derived to form a single element. The source wiring resistance (R 1 ) is obtained by connecting the wiring resistance of each source of the cell (Q O ). The overcurrent detection circuit section (A) includes a comparator (CM 2 ) having two positive and negative phases connected to both ends of a source wiring resistance (R 1 ), and a detection circuit for detecting the presence or absence of an overcurrent from the output of the comparator. (A 1 ), a logic circuit (A 2 ) that controls ON / OFF of the power MOSFET (Q 1 ) from the output of the detection circuit (A 1 ), and outputs a diagnostic signal (DIAG signal); Power MOSF from the output of A 2 )
And a drive circuit (A 3 ) for driving the ET (Q 1 ).

上記構成に基づき本考案の動作を次に説明する。ま
ず、パワーMOSFTE（Ｑ1）のソース（Ｓ1）、ドレイン
（Ｄ1）間に通常の電流（Ｉ1）が流れると、ソース配線
抵抗（Ｒ1）の両端に発生する電圧（Ｖ1）はしきい値以
下となって比較器出力はロウレベルとなる。次に、ソー
ス（Ｓ1）、ドレイン（Ｄ1）間に過電流（ＩO）が流れ
ると、上記電圧（Ｖ1）はしきい値以上になってハイレ
ベルとなる。そこで、比較器（CM2）の出力から検出回
路（Ａ1）にて過電流（ＩO）の有無を検出し、更に検出
信号より論理回路（Ａ2）とドライブ回路（Ａ3）にてパ
ワーMOSFET（Ｑ1）のON、OFFを駆動制御する。The operation of the present invention based on the above configuration will now be described. First, the source of the power MOSFTE (Q 1) (S 1 ), the drain (D 1) normal current (I 1) is the flow between the voltage (V 1) generated at both ends of the source wiring resistance (R 1) Becomes lower than the threshold value, and the comparator output becomes low level. Next, when an overcurrent (I O ) flows between the source (S 1 ) and the drain (D 1 ), the voltage (V 1 ) becomes higher than the threshold and goes to a high level. Therefore, the detection circuit (A 1 ) detects the presence or absence of the overcurrent (I O ) from the output of the comparator (CM 2 ), and furthermore, the logic circuit (A 2 ) and the drive circuit (A 3 ) from the detection signal. Controls ON / OFF of the power MOSFET (Q 1 ).

〔考案の効果〕[Effect of the invention]

本考案によれば、出力用パワーMOSFETのソース又はド
レインの配線抵抗を検出抵抗としてパワーMOSFETに流れ
る過電流を検出するようにしたから、特別の検出抵抗が
不要となって大きな電流損失を伴うことなく、検出精度
及び感度を上げることができる。According to the present invention, since the overcurrent flowing through the power MOSFET is detected by using the wiring resistance of the source or drain of the output power MOSFET as a detection resistance, a special detection resistor is not required and a large current loss is involved. In addition, detection accuracy and sensitivity can be increased.

【図面の簡単な説明】[Brief description of the drawings]

第１図と第２図は本考案に係る半導体装置の実施例を示
す要部のパワーMOSFET素子の平面図と等価回路図、第３
図と第４図は従来の半導体装置の各具体例を示す各等価
回路図である。 （ICO）……半導体装置、（Ｑ1）……パワーMOS電界効
果トランジスタ、（Ｒ1）……ソース配線抵抗、（Ａ）
……過電流検出回路部。1 and 2 are a plan view and an equivalent circuit diagram of a main part of a power MOSFET device showing an embodiment of a semiconductor device according to the present invention.
FIG. 4 and FIG. 4 are equivalent circuit diagrams showing specific examples of the conventional semiconductor device. (IC O ) Semiconductor device, (Q 1 ) Power MOS field-effect transistor, (R 1 ) Source wiring resistance, (A)
... Overcurrent detection circuit section.

Claims (1)

(57)【実用新案登録請求の範囲】(57) [Scope of request for utility model registration] 【請求項１】多数の単位MOS電界効果トランジスタ素子
を並列配置すると共に、上記単位素子の各ソース、ゲー
ト、ドレインをそれぞれ配線により並列結合してソー
ス、ゲート、ドレインを導出し、単一素子を形成した出
力用パワーMOS電界効果トランジスタと、 上記単位素子の各ソース又はドレインの並列結合によっ
て配線に生じるソース又はドレインの配線抵抗の両端の
電圧降下を検出して上記パワーMOS電界効果トランジス
タに流れる過電流を検出する過電流検出回路部とを同一
素子内に形成したことを特徴とする半導体装置。A plurality of unit MOS field-effect transistor elements are arranged in parallel, and the source, gate, and drain of the unit element are connected in parallel by wiring to derive the source, gate, and drain, and a single element is formed. A voltage drop across the source or drain wiring resistance caused by parallel connection of the formed output power MOS field effect transistor and each source or drain of the unit element is detected, and the voltage flowing through the power MOS field effect transistor is detected. A semiconductor device wherein an overcurrent detection circuit for detecting a current is formed in the same element.
JP1990074944U 1990-07-13 1990-07-13 Semiconductor device Expired - Lifetime JP2525470Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1990074944U JP2525470Y2 (en) 1990-07-13 1990-07-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990074944U JP2525470Y2 (en) 1990-07-13 1990-07-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH0432543U JPH0432543U (en) 1992-03-17
JP2525470Y2 true JP2525470Y2 (en) 1997-02-12

Family

ID=31615086

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990074944U Expired - Lifetime JP2525470Y2 (en) 1990-07-13 1990-07-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2525470Y2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10023950A1 (en) * 2000-05-16 2001-11-22 Bosch Gmbh Robert Semiconductor component with power switch connectable to load
JP4237654B2 (en) * 2004-02-20 2009-03-11 ウチヤ・サーモスタット株式会社 Safety device and overcurrent cutoff system using the same
JP2015050907A (en) * 2013-09-04 2015-03-16 株式会社東芝 Overcurrent protective device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0350762A (en) * 1989-07-19 1991-03-05 Hitachi Ltd Current detecting circuit

Also Published As

Publication number Publication date
JPH0432543U (en) 1992-03-17

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