JP2547104Y2 - Current detection circuit - Google Patents

Description

[Detailed description of the invention]

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current mirror type current detecting circuit for use in an overcurrent protection circuit of an electronic device.

[0002]

2. Description of the Related Art In an overcurrent protection circuit of an electronic device, a current detection circuit based on a current mirror system is often used.

As shown in FIG. 4, a conventional current detecting circuit based on the current mirror system has a plurality of M-modes having the same characteristics.
A parallel circuit of OSFETs Q1 to Qn is connected in series to a load RL, and a gate terminal G of these MOSFETs Q1 to Qn is shared to form a current mirror circuit. These MOSFETs Q1 to Q1
A detection resistor r is connected in series to the source terminal S of the MOSFET Q1 set for detection in n, and the load current is detected based on the voltage drop at the detection resistor r. . That is, since the MOSFETs Q1 to Qn have a common gate voltage by the current mirror circuit, the drain currents are also equal to each other. Therefore, if the drain current is measured by the voltage drop at the detecting resistor r connected to the detecting MOSFET Q1, the load current flowing through the load RL can be detected by multiplying the drain current by n. Moreover, since thousands to tens of thousands of MOSFETs Q1 to Qn are connected in parallel, a large current can be detected by a voltage drop due to a small current of several thousand to several tens of thousands. Current detection with low power and low loss becomes possible.

[0004]

[Problems to be Solved by the Invention] However, M for detection
OSFET Q1 and other MOSFETs Q2 to Qn
It is not easy to completely match these characteristics, and in practice, the threshold voltage VT is slightly different. Therefore, if the switching of the detection MOSFET Q1 to ON is slightly earlier than the others, as shown in FIG. 5, when the gate voltage Vi input to the gate terminal G rises, this MOSFET Q1 , A current transiently flows through the detection resistor r, and the detection voltage Vd at the detection resistor r becomes momentarily high.

For this reason, in the conventional current detecting circuit, a slight difference in the threshold voltage V.sub.T causes a MOSFET for detection to be used.
A problem has arisen in that the current flowing instantaneously only in Q1 is erroneously detected as an excessive current flowing in the load RL, and the overcurrent detection circuit may malfunction.

[0006]

Means for Solving the Problems To solve the above problems, the invention according to claim 1 is directed to a plurality of transformers connected in parallel.
Transistors and these transistors via detection resistors
A parallel circuit having a detection transistor connected in parallel is connected in series to a load, and a plurality of transistors and
Constitute a current mirror circuit control terminal of the transistor for detection as a common, in the current detection circuit for detecting a load current based on the voltage drop across the resistor detect a delay circuit a control terminal of the transistor for the detection Through multiple
It is characterized in that it is connected to a control terminal of a transistor .

Further, the invention of claim 2 is directed to a parallel-connected
Number of MOSFETs and detection resistors in these MOSFETs
And a detection MOSFET connected in parallel via a parallel connection. A parallel circuit is connected in series to the load, and a plurality of MOSFETs are connected.
In the current detection circuit constitute a current mirror circuit, for detecting a load current based on the voltage drop for detect resistance of the gate terminal as a common and MOSFET for detecting an FET, the resistance of the gate terminal of the MOSFET for the detection Through
To connect to the co <br/> to the gate terminals of a plurality of MOSFET and is characterized in that connected between the gate terminal of the MOSFET for detecting this resistance to a power supply via a capacitor.

[0008]

According to the above arrangement, the detection transistor includes:
A control voltage is applied via a delay circuit (in the case of a FET [field effect transistor]) or a control current flows in (in the case of a bipolar transistor). Then, the operation of the detection transistor is definitely delayed as compared with the other transistors constituting the current mirror circuit. Therefore, even if the threshold voltage VT of this detection transistor is slightly lower than that of the other transistors, when the control voltage or the control current rises, a current flows only through this transistor first and a large voltage drop occurs in the detection resistor. Will not occur.

According to the invention of claim 2, the transistor is M
A case where an OSFET is used and an integration circuit (charge / discharge circuit, low-pass filter) including a resistor and a capacitor is used as a delay circuit will be described. In this case, the change in the voltage at the gate terminal is transmitted with a delay for the detection MOSFET because the capacitor is charged or discharged via the resistor. This capacitor is connected between the power supply VDD and the ground power supply GN.
And D. Therefore, the operation of the detection MOSFET is more reliably delayed than the other MOSFETs when the gate voltage rises, so that an erroneous detection of an overcurrent does not occur.

[0010] According to the present invention, a MOSFE for detection is used.
If the application of the gate voltage to T is delayed, the OFF operation may be delayed even when the gate voltage falls. Therefore, in such a case, a diode for extracting a current from the capacitor without passing through a resistor may be connected so that the operation at the time of the fall of the gate voltage is not delayed.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

FIGS. 1 and 2 show an embodiment of the present invention. FIG. 1 is a circuit diagram of a current detection circuit, and FIG. 2 shows a change in a detection voltage Vd when a gate voltage rises and falls. It is a time chart shown.

The current detecting circuit according to the present embodiment is a current detecting circuit constituted by n-channel MOSFETs Q1 and Q2. The MOSFET Q2 has a drain terminal G and a source terminal S of thousands to tens of thousands of MOSFETs connected in parallel, and has a common gate terminal. I have.

The MOSFET Q1 for detection also has these M
The one connected in parallel with the OSFET Q2 and having the same characteristics is used. However, the source terminal S of the detection MOSFET Q1 is connected to the MOSFET
It is connected to the source terminal S on the Q2 side. This MOSF
A capacitor C is connected between the gate terminal G and the drain terminal D of ET · Q1. This capacitor C
May be connected between the gate terminal G of MOSFET Q1 and ground power supply GND as shown in FIG.
It may be connected to the source of SFET Q2. The gate terminal G of the MOSFET Q1 is connected to the gate terminal G of the MOSFET Q2 via a parallel circuit of a resistor R and a diode D.

The MOSFETs Q1, Q1,
The drain terminal D of Q2 is connected to the power supply VDD. These source terminals S are connected to a ground power supply GND via a load RL. However, M for detection
The source terminal S of the OSFET Q1 is connected to the load RL via the detection resistor r as described above. Further, a gate terminal G of the MOSFET Q1 and a MOSFET via a parallel circuit of a resistor R and a diode D
The gate terminal G of Q2 is connected together so that the gate voltage Vi is input. Therefore, the capacitor C and the resistor R serve as an integrating circuit for delaying a change in the gate voltage Vi applied to the MOSFET Q1. The diode D is for rapidly drawing a current from the capacitor C.

The current detection circuit having the above-described configuration operates with the gate voltage V
When i is applied, each of the MOSFETs Q1 and Q2 is turned on, and a load current can be supplied from the power supply VDD to the load RL. A MOSFET Q2 consisting of thousands to tens of thousands of MOSFETs and a detection MOSFET Q1
Since the gate terminals G constitute a common current mirror circuit, the respective drain currents become equal. Therefore, if the voltage drop at the detection resistor r connected to the source terminal S of the MOSFET Q1 is detected as the detection voltage Vd, the load current can be measured. That is, the detection voltage Vd is divided by the resistance value of the detection resistor r to obtain MO
The drain current of the SFET Q1 is found,
The load current flowing through the load RL can be calculated by multiplying the number obtained by adding 1 to the number of MOSFETs in ET · Q2. In addition, this load current is
Since detection can be performed only by the drain current flowing through Q1, low-power, low-loss detection is possible.

When the gate voltage Vi rises,
Since this gate voltage Vi is directly applied to the gate terminal G of the MOSFET Q2, many MOSFETs are simultaneously turned on. However, with respect to the MOSFET Q1 for detection, a current first flows into the capacitor C via the resistor R. That is, in the case of FIG. 1, the discharge of the capacitor C causes the terminal voltage to gradually decrease, and the voltage at the gate terminal G of the MOSFET Q1 increases accordingly. Also, in the case of FIG.
, The terminal voltage gradually increases, and the voltage of the gate terminal G of the MOSFET Q1 also increases accordingly. Therefore, this MOSFET
With respect to Q1, the timing at which the connection between the drain terminal D and the source terminal S is turned on by turning on the MOSFET Q
2) Slower than each MOSFET. Then, as shown in FIG. 2, the detection voltage Vd does not become abnormally high when the gate voltage Vi rises. The delay time of the MOSFET Q1 can be arbitrarily set according to the time constant of the capacitor C and the resistor R. However, the MOSFET Q1 is designed so that the detection sensitivity of the current detection circuit is not unnecessarily reduced. Q1 and MOSFET
It should be slightly longer than the error range of the characteristics of each MOSFET in Q2.

When the gate voltage Vi falls, the MOS
Each MOSFET of the FET Q2 is immediately turned off.
Also, in the MOSFET Q1, since the current is drawn from the capacitor C by the diode D, the voltage at the gate terminal G is quickly reduced, and the MOSFET Q1 can be turned off without delay by the MOSFET Q2. Therefore, even when the gate voltage Vi falls, as shown in FIG.
There is no fear that the detection voltage Vd becomes high.

In the above embodiment, the detection resistor r
May be inserted between the drain terminal D of the MOSFET Q1 and the power supply VDD.
1, Q2 can be inserted between the current mirror circuit and the power supply VDD. In the above embodiment, the transistor of the current mirror circuit is an n-channel MOSFET.
・ Although it is composed of Q1 and Q2, MO of p channel
Of course, it is possible to use an SFET, and also to use another FET or a bipolar transistor.

[0020]

As is clear from the above description, in the current detection circuit of the present invention, the operation of the detection transistor is delayed by the delay circuit, so that the threshold voltage VT of the detection transistor changes the current mirror circuit. Even when the transistor is lower than the other transistors, the overcurrent can be prevented from being erroneously detected.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a current detection circuit according to an embodiment of the present invention.

FIG. 2 is a time chart showing an embodiment of the present invention and showing a change in a detection voltage Vd when a gate voltage Vi rises and falls.

FIG. 3 is a circuit diagram of a current detecting circuit according to another embodiment of the present invention.

FIG. 4 shows a conventional example and is a circuit diagram of a current detection circuit.

FIG. 5 is a time chart showing a conventional example and showing a change in a detection voltage Vd when a gate voltage Vi rises.

[Explanation of symbols]

Q1 MOSFET for detection Q2 MOSFET G Gate terminal C Capacitor R Resistance RL Load VDD Power supply GND Ground power supply Utility model registration Applicant Kansai NEC Corporation

Claims (2)

(57) [Scope of request for utility model registration] 1. A plurality of transistors connected in parallel and a plurality of transistors connected in parallel
These transistors are connected in parallel via a detection resistor.
A parallel circuit having an output transistor is connected in series to a load, and the plurality of transistors and a detection transistor are connected .
A current mirror circuit comprising a common control terminal for the transistor and a current mirror circuit for detecting a load current based on a voltage drop of the detection resistor, wherein a control terminal of the detection transistor is connected via a delay circuit;
A current detection circuit connected to control terminals of the plurality of transistors . 2. A plurality of MOSFETs connected in parallel and the MOSFETs
These MOSFETs are connected in parallel via a detection resistor.
A parallel circuit having an output MOSFET is connected in series to a load, and the plurality of MOSFETs and an M
A current mirror circuit comprising a gate terminal common to the OSFET and a current mirror circuit configured to detect a load current based on a voltage drop of the detection resistor, wherein a gate terminal of the detection MOSFET is connected via a resistor.
Wherein when connected to the gate terminals of a plurality of MOSFET co <br/>, current detection circuit, characterized in that connected between the gate terminal of the MOSFET for the detection and the resistor to the power source via a capacitor.