JPH06289087A - Circuit for intelligent power switch - Google Patents

Abstract

PURPOSE:To provide a circuit of an intelligent power switch, which can output a status signal for directly detecting the abnormalities of the short-circuit and opening of a load. CONSTITUTION:A switching means 1, which is connected between a power supply terminal T1 to which a DC power is supplied and an output terminal T2, is turned ON in response to the input of a control signal to a control-signal input terminal T3. The power is supplied into a load, which is connected to the output terminal. An abnormal signal, which becomes an H level during the period when the load is shorted and the control signal is inputted, is generated with a load-short detecting circuit 4. The abnormal signal, which becomes H level during the period when the load is opened and the control signal is inputted, is generated with a load-opened detecting circuit 5. The abnormal signals from the circuit 4 and the circuit 5 are outputted from the status output terminal T3. A fall-down delay circuit 7, which delays the fall-clown of the abnormal signal, is provided for the output of the circuit 4 or the circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an intelligent power switch circuit suitable for integration which can detect a short circuit or open circuit of a load and output a status signal.

[0002]

2. Description of the Related Art Conventionally, as this type of circuit, an IC having the structure shown in the block diagram of FIG. 4 has been used. In the figure, reference numeral 1 denotes an output field effect transistor (FET) that functions as a switching unit, which is connected between a power supply terminal T1 to which a DC power supply is connected and an output terminal T2 to which a load or the like is connected, and which is connected to its control electrode. Is connected to the control signal input terminal T3 via the charge pump 2 and the amplifier 3.

Reference numeral 4 is a load short circuit detecting circuit for monitoring the state of the output terminal T1 to detect a short circuit state of the load, and 5 is a load open detecting circuit for detecting the open state of the load, the input of which is the output of the output FET1. Are connected and the output thereof is connected to the status output terminal T4 via the OR gate 6. Incidentally, T5 is a ground terminal.

More specifically, as shown in FIG. 5, the output FET1 is a small current type FET1 ₁ having a source connected to a power supply terminal T1, a drain connected to an output terminal T2, and a gate connected to a charge pump 2. Thousands, for example, of 1 to 1 _n are arranged in parallel to control a current of several A in total. Further, there is provided a detection FET ₁₀ whose source is connected to the power supply terminal T, whose gate is connected to the charge pump 2 and whose drain is connected to the ground via the resistor Rs. For example, if the detection FET _{1 0} and each of the FETs _{1 1} to 1 _{n form} a current mirror circuit and the ratio of the number of them is 1: 2000, the detection FET _{1 0} at the time of output 2A has 1/2000. Current of 1 mA flows.

If a current of 5 A flows when the load connected to the output terminal T2 is short-circuited, the FE for detection is detected.
To flow a current of 2.5mA to T1 _0. Therefore, the load short circuit can be detected by monitoring the potential difference across the resistor Rs. Further, the voltage of the output terminal T2 changes with respect to the voltage of the power supply terminal T1 when the load is normal and when the load is open, and becomes smaller when the load is open than when it is normal. Therefore, the load open can be detected by monitoring the voltage difference between the power supply terminal T1 and the output terminal T2.

Therefore, the non-inverting input and the inverting input of the comparator 4a forming the load short-circuit detection circuit 4 for detecting a load short circuit are connected to both ends of the resistor Rs, respectively. As shown in FIG. 6, the comparator 4a has a small potential difference generated at both ends of the resistor Rs during normal operation in response to the input of the ON control signal to the control signal input terminal T3, and its output is at the L level as shown in (c). Although the output terminal T2 is turned off as shown in (b) during short-circuiting, the potential difference generated across the resistor Rs is large and its output becomes the H level as shown in (d). To work.

Further, the inverting input and the non-inverting input of the comparator 5a forming the load open circuit 5 for detecting the open of the load are connected to the power supply terminal T1 and the output terminal T2, respectively. The comparator 5a, as shown in FIG.
The potential difference generated between the power supply terminal T1 and the output terminal T2 is large during normal operation, and the output is at the L level as shown in (c), but when open, the output terminal T2 is at (b).
Although it is turned on as shown in (4), the potential difference generated between the power supply terminal T1 and the output terminal T2 is small, and the output thereof works so as to be at the H level.

The intelligent power switch (IPS) described above outputs the same H-level status signal when the load is short-circuited and when the load is open, without distinguishing between the two.

[0009]

However, the above-mentioned IP
For example, as shown in FIG. 7A, S is connected to the load L and the manual switch SW between the output terminal T2 and the ground,
As in the case where the control unit CU and the load L are connected between the output terminal T2 and the ground as shown in (b), the same operation as the opening of the load L is performed depending on the states of the manual switch SW and the control unit CU. When a condition occurs, it is necessary to detect only shorts.

In order to distinguish between the short circuit and the open circuit, as shown in FIG. 8, the states of the control signal input terminal T3, the status output terminal T4 and the output terminal T2 of the IPS are operated according to a predetermined control program. Monitored by a microcomputer (CPU), input terminal T3
And status output terminal T4 are both turned on and output terminal T2
It is only necessary to detect that the load L is short-circuited when is off, and that the load L is open when both the input terminal T3 and the status output terminal T4 are on and the output terminal T2 is on. This method has a problem that the number of monitoring points increases.

Therefore, in view of the above-mentioned conventional problems, it is an object of the present invention to provide an intelligent power switch circuit capable of outputting a status signal capable of directly detecting an abnormality of load short circuit and open circuit.

[0012]

SUMMARY OF THE INVENTION To achieve the above object, an intelligent power switch circuit according to the present invention is connected between a power supply terminal to which a DC power is supplied and an output terminal to control a control signal input terminal. A switching means that is turned on in response to the input of a signal to supply a power source to a load connected to the output terminal; and an abnormal signal that is at an H level while the control signal is being input when the load is short-circuited. A load short-circuit detection circuit that generates, a load open detection circuit that generates an abnormal signal that is at H level during the period when the control signal is input when the load is open, the load short-circuit detection circuit, and the load open detection circuit In the circuit for intelligent power switch that outputs the abnormal signal from the circuit from the status output terminal, The output of the load short-circuit detection circuit or the open load detection circuit, is characterized in that a fall delay circuit for delaying the falling edge of the abnormal signal.

[0013]

With the above structure, the output of the load short-circuit detecting circuit or the load open detecting circuit is provided with the falling delay circuit for delaying the falling of the abnormal signal. The abnormal signal output by the detection circuit has a slower falling edge than the abnormal signal output by the detection circuit not provided with the fall delay circuit, so the status signal at the status output terminal is monitored,
By detecting whether or not the status output terminal is at the H level even after the control signal disappears, it is possible to distinguish and determine whether the abnormality is a short circuit or an open circuit.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. 1 shows an embodiment of a circuit for an intelligent power switch according to the present invention. In FIG. 1, the same parts as those described above with reference to FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted. In this embodiment, a fall delay circuit 7 is provided between the output of the load short circuit detection circuit 4 and the OR gate 6. In the fall delay circuit 7, when the load is in a short-circuited state, the output of the load short-circuit detection circuit 4 rises from the L level to the H level in response to the turning on of the control signal to the input terminal T3, and in response to the turning off of the control signal. Even if the status signal falls from the H level to the L level, the status signal does not immediately fall, and as shown in FIG. 2 (c), the status signal maintains the H level for a certain period of time T and then falls to the L level.

Therefore, by detecting that the status signal remains at H level for a certain period of time after the control signal input terminal T3 is turned off, the short-circuit state of the load can be detected separately from the open state. it can.

As the fall delay circuit 7, specifically, the one having the structure as shown in FIG. 3 can be applied, and the output of the load short circuit detection circuit 4 is connected to the base of the NPN switching transistor 7b via the resistor 7a. And the ground of the transistor 7b is connected to the ground via the capacitor 7c, and the base of the transistor 7b is connected to the ground via the resistor 7d. The emitter of the transistor 7b is connected to the ground, and the collector is connected to the DC power supply via the resistors 7e and 7f. The connection point of the resistors 7e and 7f is connected to the base of a PNP switching transistor 7h whose emitter is connected to the DC power supply and whose collector is connected to the ground via the resistor 7g. And transistor 7
The connection point between the collector of h and the resistor 7g is connected as an output to one input of the OR gate 6.

In the falling delay circuit 7, when the output of the load short circuit detecting circuit 4 rises from L level to H level, the capacitor 7c is rapidly charged, and in response to this, the switching transistor 7b is turned on and the resistance 7e from the DC power source. And 7f and the transistor 7b cause a current to flow to the ground, and accordingly, the transistor 7h turns on and a current flows from the direct current power supply through the transistor 7h and the resistor 7g, so that the voltage at the connection point between the collector of the transistor 7h and the resistor 7g is increased. It starts to rise from L to H level. Then, when the output of the load short-circuit detection circuit 4 falls from H level to L level, the electric charge charged in the capacitor 7c is discharged to the ground through the resistors 7a and 7d. As a result, the transistor 7b is kept in the ON state until a predetermined time when the charging voltage of the capacitor 7c reaches a predetermined level, and accordingly, the transistor 7h is also kept in the ON state and then turned off. As described above, the trailing edge of the status signal is delayed for a fixed time.

In the embodiment, the fall delay circuit 7 is provided between the load short circuit detection circuit 4 and the OR gate 6, but instead it is provided between the load open detection circuit 5 and the OR gate 6. You may do it.

[0019]

As described above, according to the present invention, it is possible to output a status signal which can directly detect an abnormality of load short circuit and open circuit. Therefore, the status signal can be monitored and the status signal can be output even after the control signal disappears. By detecting whether or not it is at the H level, it is possible to distinguish and determine whether a short circuit or an open circuit has occurred.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a circuit for intelligent power switch according to the present invention.

FIG. 2 is a timing chart showing the state of each part of FIG.

FIG. 3 is a diagram showing a specific circuit example of a falling delay circuit in FIG.

FIG. 4 is a diagram showing an example of a conventional intelligent power switch circuit.

5 is a diagram showing a specific circuit example of the circuit of FIG.

FIG. 6 is a timing chart showing the state of each part of FIG.

FIG. 7 is a diagram showing a usage example of a conventional intelligent power switch.

FIG. 8 is a diagram showing another example of use of the conventional intelligent power switch.

[Explanation of symbols]

 1 output FET (switching means) 4 load short detection circuit 5 load open detection circuit 7 fall delay circuit T1 power supply terminal T2 output terminal T3 control signal input terminal T4 status output terminal

Claims (1)

[Claims] 1. A switching device which is connected between a power supply terminal to which a DC power supply is supplied and an output terminal and which is turned on in response to a control signal input to a control signal input terminal to supply the power supply to a load connected to the output terminal. Means, a load short-circuit detection circuit that generates an abnormal signal that is at H level during the period when the control signal is input when the load is short-circuited, and the control signal is input when the load is open A load open detection circuit that generates an abnormal signal that is at H level for a certain period of time, and an intelligent power switch circuit that outputs an abnormal signal from the load short circuit detection circuit and the load open detection circuit from a status output terminal. A falling edge that delays the falling edge of the abnormal signal at the output of the load short detection circuit or the load open detection circuit. Intelligent power switch circuit characterized in that provided extending circuit.