JP2508245B2 - Semiconductor memory device - Google Patents

Description

The present invention relates to a semiconductor memory device having a multi-bit configuration,
In particular, it relates to the pattern layout of the data bus.

[Conventional technology]

FIG. 2 is a schematic top view showing a pattern layout in a conventional multi-bit semiconductor memory device. In the figure, (1) is a memory cell area, (2) is a peripheral circuit area, (3) is a read-only data bus, (4) is a write-only data bus, and these data buses (3) and (4) are Also adopts a so-called single-ended type signal line configuration. (5) is a semiconductor memory cell device.

In the conventional multi-bit semiconductor memory device, the write-only data bus (4) is a write-only data bus (4) as shown in the figure, and the read-only data bus (3).
Are either laid out so that the read-only data buses (3) are adjacent to each other, or the same bus line is used for read and write.

The reason is that sharing the data bus for read and write reduces the number of wirings, and even when the data bus is not shared, the read-only data bus (3) and the write-only data bus (4) are connected to each other. Even if the layouts are arranged close to each other, no trouble occurs.

Therefore, in the conventional semiconductor memory device having a multi-bit configuration, the read and write data buses are shared, or the read-only data buses (3) and the write-only data buses (4) are arranged close to each other. Was.

[Problems to be Solved by the Invention]

As the integration of semiconductor memory devices increases and the distance between data buses formed by metal lines becomes shorter, the capacity between metal lines becomes larger and the speed of memory becomes faster. The data delay due to the capacity between them greatly affects the access time.

By the way, since the write-only data bus and the read-only data bus in the conventional semiconductor memory device are laid out as described above, the signals of the adjacent data buses change in phase. That is, for example, in a group of write-only data buses, since each data bus is in charge of signal transmission of each bit, a change in signal level in the group of data buses (for example, “H” → “L” or “L”). "→" H ") are performed simultaneously with each other. When changing in phase, especially when the signal on one data bus changes from "H" to "L" and the signal on the other adjacent data bus changes from "L" to "H". Substantially operates as if there is a capacity close to twice the provisional capacity (mirror capacity), which greatly increases the data delay time on the data bus and greatly affects the access time. There was a problem.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor memory device which is not affected by the mirror capacitance due to the interference between data buses.

[Means for solving the problem]

In the semiconductor memory device according to the present invention, the conventional read-only data buses are arranged adjacent to each other, the line-only data buses are arranged adjacent to each other, and the write-only data buses are arranged adjacent to each other. Alternate with data bus (sandwich)
It is laid out.

[Action]

In the data bus according to the present invention, the read-only data bus and the write-only data bus are laid out alternately (in a sandwich form) to reduce the mirror capacitance between the data bus metal wirings and speed up the semiconductor memory device.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic top view showing a pattern layout of a semiconductor memory device. In the figure, (1) to (5) are equivalent to those shown in the conventional example of FIG. The read-only data bus (3) is connected to the write-only data bus (4) that communicates data provided from the outside of the semiconductor memory cell device (5) to the memory cell area (1) through the peripheral circuit area (2). They are laid out alternately (sandwich-like) one by one.

 Next, the operation will be described.

The data bus is divided into a read-only data bus (3) and a write-only data bus (4), and the read-only data bus (3) and the write-only data bus (4) are laid out in a sandwich. Since the spacing between the metal wirings is the same as that of the data bus in the conventional semiconductor memory device, the apparent capacitance between the metal wirings is not changed.

Generally, it acts as if it has a capacitance larger than the actual capacitance between metal lines only when signals of metal lines arranged in parallel change in phase. This is generally called a mirror capacitance.

Therefore, in the layout of the data bus in the conventional semiconductor memory device, the signals of the adjacent data buses change in phase, so that the mirror capacitance works and the delay in the data bus increases.

However, in the layout of the data bus of the semiconductor memory device according to the present invention, the write-only data bus (4) is laid out next to the read-only data bus (3), and further next to the write-only data bus (4). Has a read-only data bus (3) laid out. Also,
Read operation and write operation are executed at different times,
Moreover, since both data buses (3) and (4) employ single-ended signal lines, the signal between one signal line and another signal line adjacent thereto is eventually It is certain that it will never change to the same phase. Therefore, the problem that the capacitance between the lines becomes larger than the apparent value and the access time is delayed is eliminated, and the access speed can be increased.

〔The invention's effect〕

As described above, according to the present invention, the read-only data bus and the write-only data bus are alternately (sandwiched) laid out, so that the delay in the data bus due to the mirror capacity can be eliminated, and the semiconductor memory device can operate at high speed. Can be converted.

[Brief description of drawings]

FIG. 1 is a schematic top view showing a pattern layout of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 is a schematic top view showing a pattern layout of a conventional semiconductor memory device. In the figure, (1) is a memory cell area, (2) is a peripheral circuit area, (3) is a read-only data bus, (4) is a write-only data bus, and (5) is a semiconductor memory cell device. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A semiconductor memory device having a multi-bit structure, wherein a plurality of single-end type write-only data buses and read-only data buses are laid out in parallel according to the number of bits. A semiconductor memory device, wherein one read-only data bus and one read-only data bus are alternately laid out.