JPH0793359B2 - Semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a semiconductor integrated circuit device, and more particularly to a signal line for propagating a signal such as a clock signal supplied to various parts of the device. The present invention relates to a semiconductor integrated circuit device having the same.

(Prior Art) As a semiconductor integrated circuit device having a signal line for propagating a signal supplied to various parts of the device such as a clock signal,
For example, a semi-custom semiconductor integrated circuit device based on a standard cell system or a gate array system has been conventionally known.

A pattern plan view of such a conventional semiconductor integrated circuit device is shown in FIG. The semiconductor integrated circuit device having the pattern plane shown in FIG. 7 is disclosed in the specification and drawings attached to Japanese Patent Application No. 62-213545.

Referring to FIG. 7, reference numeral 50 denotes an IC chip body, and in the chip body 50, a plurality of cell rows 51 in which a plurality of standard cells are arranged are provided. In these cell rows 51, signal connection cells 52 are arranged at positions that are in a straight line between the cell rows. The signal connecting cells 52 are connected to each other via inter-cell wiring 53 having a wide wiring width. Also, the chip body
A plurality of I / O cells 54 are provided around the periphery of 50, and of these I / O cells 54, 54A is a clock driver cell to which a clock signal is input. The inter-cell wiring 53 is connected to the clock driver cell 54A.

In the semiconductor integrated circuit device configuration as described above, the inter-cell wiring 53 for propagating the clock signal output from the clock driver cell 54A has (1) a wide width in which the wiring resistance can be ignored.

(2) The minimum wiring length in the chip can be obtained by arranging the signal connection cells 52 in a straight line.

As a result, the capacitance of the inter-cell wiring 53 can be reduced, and the respective arrival times of the clock signal entering each cell row 51, especially the clock signal entering the input end of each amplifier 55, can be made substantially equal.

Therefore, the occurrence of the phase shift of the clock signal in each cell row 51 is suppressed, the rounding of the waveform at the terminal end of the signal line through which the clock signal is propagated is reduced, and the problems such as clock skew are solved.

In addition, in the device shown in FIG. 7, an amplifier 55 is provided in the signal connecting cell 52. This amplifier 55
The input end of is connected to the inter-cell wiring 53, while the output end is connected to the cell row wiring 56. By doing so, it is possible to further improve the cell drive capability of the clock signal supplied to each cell row 51.

Now, the load capacitance of this amplifier 55 depends on the number of flip-flops (fanout) per cell row 51, and the cell row wiring.
And the wiring length of 56.

However, the number of flip-flops (fanout) is
It is customary for each cell row 51 to be different, and the wiring length of the cell row wiring 56 also differs for each cell row 51 depending on the number of flip-flops or the arrangement state thereof.

Therefore, the load capacitance of the amplifier 55 is different for each cell row 51.

If the load capacitance of the amplifier 55 is different for each cell row 55 in this way, a phase difference occurs in the clock signal at each output terminal of each amplifier 55.

As a result, the phase difference generated at each output end of each amplifier 55 causes a new clock skew.

(Problems to be Solved by the Invention) The present invention has been made in view of the above points, and particularly when an amplifier is provided in a signal connection cell, a clock generated at the output end of the amplifier. An object of the present invention is to provide a semiconductor integrated circuit device capable of reducing the phase difference between signals and further reducing the problem of clock skew.

[Structure of the Invention] (Means for Solving the Problems) A semiconductor integrated circuit device according to the present invention is provided in a cell row group for arranging standard cells and a plurality of cell rows. The signal-connecting cell group having the built-in amplifiers arranged in a straight line and each of the plurality of cell rows are provided on the right side of the signal-connecting cell, and are arranged in a straight line between the plurality of cell rows. The first load capacity adjusting cell group and the second load capacity provided in a position on the left side of each of the plurality of cell rows when viewed from the signal connecting cell and arranged in a straight line between the plurality of cell rows. An adjustment cell group and a plurality of cell rows are provided for each of the plurality of cell rows, and the first load capacity adjustment cell to the second load capacity adjustment cell are wired so that the plurality of cell rows have the same wiring length. Signal connection Connected to the output of the cell row wiring, and provided between the first load capacitance adjusting cell group and the second load capacitance adjusting cell group of the plurality of cell rows and connected to the cell row wiring. Each of the load capacity adjusting cells, which comprises a plurality of standard cells and constitutes the first and second load capacity adjusting cell groups, has a unit capacity determined corresponding to a fan-out. The load capacity is set to an integer multiple for each, and the load capacity on the right side as seen from the signal connection cell and the load capacity on the left side as seen from the signal connection cell are set to be equal for each of multiple cell rows. I am trying.

In another aspect, the load capacitance adjusting cell has a capacitance insulated gate type FET portion having the same structure as the input gate of the standard cell, and the gate length in the capacitance insulated gate type FET portion is equal to that of the standard cell. It is characterized in that the unit capacitance corresponding to the fan-out is set by making it an integral multiple of the gate length of the insulated gate FET that constitutes the input gate of.

(Operation) In the semiconductor integrated circuit device having the above configuration, the load capacitances at the output ends of the respective signal connecting cells can be made equal to each other between the cell rows in which the signal connecting cells are provided. As a result, it is possible to prevent clock skew from occurring in each signal output from each signal connection cell.

Further, in the semiconductor integrated circuit device having the above configuration, the unit capacity corresponding to the fan-out is set in the load capacity adjusting cell, and the load capacity is set by a simple method of multiplying this unit capacity by an integer. It can be adjusted.

Moreover, since the wiring lengths of the cell row wirings are unified among a plurality of cell rows, the unit capacity set in the load adjustment cell is multiplied by an integer according to the number of fan-outs. By just doing so, the capacity according to the number of fan-outs and the capacity of the cell row wiring itself can be adjusted at the same time, which is highly accurate.

In addition, the load capacitance can be adjusted only by an integer multiple according to the number of fan-outs.Therefore, the load capacitance adjustment cell must have an insulated gate FET unit for capacitance that has the same structure as the input gate of the standard cell. , By setting the gate length in the insulated gate FET part for this capacitance to be an integral multiple of the gate length of the insulated gate FET that constitutes the input gate of the standard cell, it is possible to set the unit capacitance corresponding to the fanout, It can be performed more simply.

(Embodiment) A semiconductor integrated circuit device according to an embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the structure of a semiconductor integrated circuit device according to the first embodiment of the present invention. In FIG.
10 is an IC chip body, and in this chip body 10,
Multiple cell rows with multiple standard cells 11
(11A to 11D) are provided. These cell rows 11A-1
In 1D, the signal connection cells 12 are arranged in positions that are in a straight line between the cell rows. The signal connection cells 12 are connected to each other via inter-cell wiring 13 having a wide wiring width such that the wiring resistance can be ignored. A plurality of I / O cells 14 are provided around the chip body 10. Of these I / O cells 14, 14A is a clock driver cell to which a clock signal is input. The inter-cell wiring 13 is connected to the clock driver cell 14A. An amplifier 15 is provided in the signal connection cell 12. The input terminal of this amplifier 15 is connected to the inter-cell wiring 13, while the output terminal is connected to the cell row wiring.
Connected to 16.

Further, in the cell rows 11A to 11D, load capacity adjusting cells 17AR to 17DR and 17AL to aim to configure a capacity component.
17DL is provided.

Then, load capacity adjusting cells 17AR to 17DR, 17AL to 17DL
Are connected to the output ends of the amplifiers 15 by the cell row wirings 16 in each cell row.

These load capacity adjustment cells 17AR to 17DR and 17AL to 17DL are
It is provided in order to equalize the capacitances of the cell rows 11A to 11D, respectively, and if the capacitances of the cell rows 11A to 11D are all equal, the load capacitances of the amplifier 15 can be equal.

Therefore, there is almost no phase difference between the clock signals generated at the output end of the amplifier 15, and the problem of clock skew can be further reduced.

In the present invention, the load capacity adjusting cells 17AR to 17DR,
The capacities of 17AL to 17DL are configured to have some basic unit capacities.

In this way, the load capacity adjustment cells 17AR to 17DR, 17AL to 17
If the DL capacity has some basic unit capacity, the design of the semiconductor integrated circuit device becomes simple.

Next, an example of load capacity adjustment by the load capacity adjusting cells 17AR to 17DR and 17AL to 17DL will be described.

As one method for making the capacities of the cell rows 11A to 11D equal, the number of flip-flops on the right side (fan-out) and the number of flip-flops on the left side, which are viewed from the output terminal of the amplifier 15, are made uniform. Good.

For example, the cell rows having the largest fanout on the right side of the cell rows 11A to 11D centering on the amplifier 15 are the cell rows 11B and 11D of fanout 1. So another cell row 11A
Load capacity adjusting cells 17AR and 17CR whose capacities correspond to fanout 1 are incorporated so that 11C and 11C become fanout 1.

Also, the cell rows 11B and 11D have a fanout of 0.
The load capacity adjusting cells 17BR and 17DR corresponding to are incorporated.

In this way, the fan-outs 1 are all aligned on the right side of the cell rows 11A to 11D.

The same operation is performed on the left side of cell rows 11A to 11D.

For example, the cell rows having the largest fanout on the left side of the cell rows 11A to 11D centering on the amplifier 15 are the cell rows 11A and 11D of fanout 2. So another cell row 11B
In the cell row 11C, a load capacity adjusting cell 17CL having a capacity corresponding to the fan-out 2 is incorporated, and in the cell row 11C, a load capacity adjusting cell 17CL having a capacity corresponding to the fan-out 1 is incorporated.

Also, the cell rows 11A and 11D have a fanout of 0.
By incorporating the load capacity adjusting cells 17AL and 17DL corresponding to, the left sides of the cell rows 11A to 11D can be aligned with all the fanouts 2.

Therefore, all the cell rows 11A to 11D are in fan-out 3, and the capacities according to the number of flip-flops are all equal.

Furthermore, load capacity adjustment cells 17AL to 17DL, 17AR to 17DR
Is arranged at the end of each cell row, for example, so that the lengths of the cell row wirings 16 of the cell rows 11A to 11D are all equal and the capacitances due to the wiring lengths are all equal.

Next, the structure of the load capacity adjusting cells 17AL to 17DL and 17AR to 17DR will be described with reference to FIGS.

FIG. 2 is a plan view showing the configuration of the load capacity adjusting cells 17AR, 17CR, 17BL corresponding to the fan-out 1. As shown in FIG. 2, the load capacity adjusting cell is a P channel type MO.
It consists of SFET20P and N-channel MOSFET20N,
A gate electrode 21 is formed across both. This structure is the same as the structure of the input gate of, for example, a flip-flop connected to the cell row wiring 16.

In this way, by making the structure of the load capacitance adjusting cell the same as the structure of the input gate of the flip-flop, for example,
The gate capacitance of the flip-flop and the gate capacitance of the load capacitance adjustment cell can be made equal, and the fanout can be regarded as the same.

For example, when a CMOS inverter having a gate length L and a gate width W is used as an input gate of a flip-flop, a load capacitance adjusting cell (shown in FIG. 2) having the same gate length L and gate width W is used. , A load capacity adjusting cell corresponding to the fan-out 1.

Further, in order to obtain a load capacitance adjusting cell corresponding to the fan-out 2, if the gate electrode 21 has a double gate length, that is, a gate length of 2L, as shown in the plan view of FIG. Good.

Similarly, in order to obtain a load capacitance adjusting cell corresponding to fanout 0, the gate electrode 21 need not be formed as shown in the plan view of FIG.

However, in this case, the cell row wiring 16 extends to the area where the load capacity adjusting cells are arranged even if the load capacity adjusting cells corresponding to the fan-out 0 are formed. In this way, by extending the cell row wiring 16 to the above-mentioned arrangement region, the wiring lengths of the cell row wiring 16 are all unified in each of the cell rows 11A to 11D.

As described above, according to the device of the first embodiment of the present invention, the load capacity adjusting cells 17 are provided in the cell rows 11A to 11D, respectively.
By incorporating AR to 17DR and 17AL to 17DL, the fanouts of all cell rows 11A to 11D can be aligned.

Furthermore, load capacity adjustment cells 17AR to 17DR, 17AL to 17DL
Is arranged at, for example, the end of each cell row, so that the wiring length of each cell row wiring 16 can be made the same in all cell rows 11A to 11D.

From these facts, the load capacitance of the amplifier 15 becomes equal in each amplifier 15, the generation of the phase difference of the clock signals at the output end is suppressed, and the problem of clock skew is further alleviated.

By the way, in the device of the first embodiment, the load capacity adjusting cells 17AR to 17DR and 17AL to 17DL are arranged, for example, at the end of each cell row, so that the wiring lengths of the cell row wirings 16 are equalized. .

However, the means for unifying the wiring lengths is not limited to the arrangement at the outermost end.

For example, among the standard cells connected to the output terminal of the amplifier 12 in each cell row, one of the adjustment cells is located outside the standard cell located farthest from the connection point between the output terminal and the cell row wiring. To place. The wiring lengths can be unified by arranging the remaining adjustment cells at positions corresponding to the adjustment cells.

Next, such an example will be described as a second embodiment with reference to FIG. In FIG. 5, the same parts as those in FIG. 1 are designated by the same reference numerals, and a duplicated description will be avoided.

As shown in FIG. 5, the output terminal of the amplifier 12 and the cell row wiring
From the connection point with 16 (hereinafter referred to as node a for convenience), the cell row connected to node a on the right side of the drawing and having the standard cell located at the shortest distance is 11A. The wiring length from the node a to the standard cell located at the shortest distance is shown as l1. On the other hand, the cell row connected to node a and having the standard cell located at the longest distance is 11D.
Similarly, the wiring length is shown as l2. In the conventional device, the cell row wirings have different wiring lengths of 11 for the cell row 11A and 12 for the cell row 11D.

According to the present invention, the load capacitance adjusting cell 17DR is arranged further outside the standard cell arranged with the wiring length l2 in the cell row 11D. As a result, the cell row wiring 16 extends to the area where the adjustment cells 17DR are arranged, and has a wiring length LR that is longer than the wiring length l2. Then, the remaining adjustment cells 17AR to 17CR are arranged in accordance with the position of the adjustment cell 17DR so that the wiring length from the node a is LR.

By doing this, the cell row wiring on the right side when viewed from node a
All 16 wiring lengths are unified to LR. In this case, in each cell row, the standard cell is not necessarily arranged at the end of the cell row due to various design reasons such as being arranged at an arbitrary position by automatic placement and wiring design. Absent. For example, a standard cell for inputting a signal different from the clock signal is arranged in a region in the cell row 16 shown by 23 in the figure.

The same operation is performed on the left side from the node a. Briefly, the shortest wiring length from the node a is l3 in the cell row 11C, and the longest wiring length is l4 in the cell row 11A. Therefore, the load memory cell 11AL is in the cell row 11A. Then, it is arranged so as to be located outside the standard cell arranged with the wiring length l4. Then, the cell row wiring 16 is extended to this point so that the wiring length becomes LL. The remaining adjustment cells 17BL to 17DL are arranged in alignment with the adjustment cell 17AL so that the wiring length LL from the node a is obtained.

As described above, the standard cell connected to the node a may be arranged at any position in the cell row, and the adjustment cell may be arranged at any position in the cell row in accordance with the standard cell. Then, the wiring lengths of the other cell row wirings may be aligned with the wiring lengths of the longest cell row wirings (LR and LL in the figure).

Next, a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to FIG. Figure 6 shows
FIG. 7 is a plan view of the third embodiment device, in which the same parts as those in FIG. 1 are designated by the same reference numerals, and a duplicated description will be avoided.

The characteristic of the device of the third embodiment is that the output terminals of the amplifier 15 are
Furthermore, there is a point connected by wiring 18. Amplifier 15
By connecting the output terminals of each other, the variation of the capacitance in the amplifier 15 can be canceled out, and the generation of the further phase difference of the clocks can be suppressed.

Even in such a semiconductor integrated circuit device, by incorporating the load capacitance adjusting cell according to the present invention in each of the cell rows 11A to 11D, it is possible to further suppress the phase difference of the clock and reduce the problem of the clock skew. it can.

In the first to third embodiments described above, the load capacity adjustment cells are provided with fanouts 0, 1, and 2 as basic units, but of course, other units may be prepared. Good. For example, 3, 4 or more,
Furthermore, a plurality of load capacity adjustment cells having numerical values below the decimal point, such as 0.5 and 1.5, may be prepared instead of being an integer.

In the first to third embodiments, the capacitances on the right side and the left side of the output terminal of the amplifier 15 and the connection point with the cell row wiring 16 are different from each other.

However, if possible, it is more desirable that the fan-outs on both the left and right sides as viewed from the connection point are equal and the wiring lengths of the cell row wirings 16 are equal.

However, it is very difficult to design such a semiconductor integrated circuit device, and in practice, the left and right sides have the same fan-out as much as possible, and the cell row wirings 16 have the same wiring length as much as possible. Such consideration should be given.

[Effects of the Invention] As described above, according to the present invention, particularly when the amplifier is provided in the signal connection cell, the phase difference of the clock signal generated at the output end of the amplifier is reduced, and Provided is a semiconductor integrated circuit device capable of further reducing the problem of queues.

[Brief description of drawings]

1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention, FIGS. 2 to 4 are plan views showing the structure of a load capacitance adjusting cell, and FIG. 5 is a plan view of the present invention. 2 is a plan view of a semiconductor integrated circuit device according to the second embodiment, FIG. 6 is a plan view of a semiconductor integrated circuit device according to a third embodiment of the present invention, and FIG. 7 is a plan view of a conventional semiconductor integrated circuit device. is there. 10 …… Chip body, 11A to 11D …… Cell row, 12 …… Signal connection cell, 13 …… Inter-cell wiring, 14 …… I / O circuit, 15…
… Amplifier, 16 …… Cell row wiring, 17AL to DL, 17AR to 17DR…
… A load adjustment cell.

Front page continuation (72) Inventor Takashi Saigo No.580-1 Horikawa-cho, Sachi-ku, Kawasaki-shi, Kanagawa Inside the Toshiba Semiconductor System Technology Center, a stock company (56) Reference JP-A-63-293941 (JP, A) JP Flat 1-196137 (JP, A)

Claims (2)

[Claims] 1. A cell row group for arranging standard cells, and a signal connection cell group provided in a plurality of the cell rows and arranged in a straight line between the plurality of cell rows and containing an amplifier. A first load capacity adjusting cell group provided in a position on the right side of the plurality of cell rows when viewed from the signal connecting cell, and arranged in a straight line between the plurality of cell rows; Each of the cell rows, a second load capacity adjusting cell group provided at a position on the left side as viewed from the signal connection cell and arranged in a straight line between the plurality of cell rows, and each of the plurality of cell rows Connected to the output of the signal connection cell, the wirings are provided from the first load capacitance adjustment cell to the second load capacitance adjustment cell, and the plurality of cell rows have the same wiring length. Cell rows A wiring group; and a plurality of standard cells provided between the first load capacity adjusting cell group and the second load capacity adjusting cell group of the plurality of cell rows and connected to cell row wirings. Each of the load capacity adjusting cells constituting the first and second load capacity adjusting cell groups has a unit capacity determined corresponding to a fan-out, and is an integer for each load capacity adjusting cell. A doubled load capacity is set, and the load capacity on the right side as seen from the signal connection cell and the load capacity on the left side as seen from the signal connection cell are set to be equal for each of the plurality of cell rows. Semiconductor integrated circuit device. 2. The load capacitance adjusting cell has a capacitance insulating gate type FET portion having the same structure as the input gate of the standard cell, and the gate length in the capacitance insulating gate type FET portion is the standard gate length. 2. The semiconductor integrated device according to claim 1, wherein a unit capacitance corresponding to the fan-out is set by setting an integral multiple of a gate length of an insulated gate FET that constitutes an input gate of the cell. Circuit device.