JP2507630B2 - Multi-bid drive semiconductor integrated circuit - Google Patents

Description

The present invention relates to a multi-bit drive semiconductor integrated circuit suitable for a common drive semiconductor integrated circuit for LCD (liquid crystal display device) and the like by a serial transfer method.

[Conventional technology]

In the conventional LCD common drive semiconductor integrated circuit, as shown in FIG. 4, a data pulse DI input via the data signal terminal 1 is input via the clock terminal 2 at every cycle corresponding to the number N of clock pulses. In synchronization with the incoming clock pulse CP, serial transfer is sequentially performed from the first stage to the last stage, and the final stage output Qn is supplied as an output signal DO to the next stage integrated circuit via the external output terminal 3 for cascade connection. A bit shift register circuit 4, an N-bit level shift circuit 5 for boosting and converting the output of each stage of the circuit 4 from a logical power supply voltage level to a power supply level for LCD driving, and 1 for each output of this circuit 5.
Select LCD power supply voltage V ₀ ~V ₅ corresponds to to-1, N-bit sending a signal electrode applied voltage Y ₁ to Y _N with its respective voltage into an AC drive waveform based on an AC waveform of the clock M The data pulse (serial data signal) DI is sent by the N-bit shift register circuit 4, which is a serial-parallel converter, as a parallel signal of each stage output Q ₁ -Q _N.

[Problems to be Solved by the Invention]

In this type of LCD common drive semiconductor integrated circuit, the frequency (frame frequency) of the data pulse DI is 70 Hz.
In this case, when the pulse width is 1/200 duty, the transfer clock CP frequency is 14 KHz, and when 1/400 duty is 28 KHz, the transfer clock CP frequency is sufficient at a low operating frequency. Although there is little demand for higher speed, LSIs with more multi-bit outputs are desired.

This demand for high-density integration is to achieve a reduction in mounting cost that eliminates the multi-stage cascade connection of semiconductor integrated circuits as much as possible and a reduction in yield resulting from an increase in yield due to the increase in the number of bits of the LSI itself.

As a measure for high-density integration of the LCD common drive semiconductor integrated circuit, there is a way to reduce the chip size by the microfabrication process technology and simplify the circuit configuration itself. Of course, it is necessary to make full use of both to achieve high integration, but each stage of the shift register circuit 4 is normally 8
Since the number of bits (number of stages) of the shift register circuit 4 is increased in order to increase the number of bits, the occupied area of the shift register circuit significantly increases as compared with that of other circuits, because each transistor (gate) is configured. However, this leads to an increase in chip size and also leads to a reduction in yield.

Therefore, the present invention is to solve the above problems,
The problem is that by adopting a circuit configuration in which the number of stages of the shift register circuit does not increase even if the number of output bits is increased, it is possible to suppress the expansion of the chip size as much as possible while increasing the number of bits and improve the process yield. An object is to provide a multi-bit driving semiconductor integrated circuit that can be achieved.

[Means for Solving the Problems] In order to solve the above problems, the means taken by the present invention are:
A multi-bit drive semiconductor having an N-stage shift register circuit that serially transfers a data pulse that comes in every cycle corresponding to a multiple mN of the clock pulse number N from the first stage to the last stage in synchronization with the clock pulse. In the integrated circuit, input switching means for switching and connecting the data pulse input terminal and the final stage output of the shift register circuit to the first stage input of the shift register circuit, and the final stage output and the external output terminal Switching means for conducting / cutting off, m N-bit parallel output means for scanningly distributing and outputting N-bit parallel output of the shift register circuit for each cycle corresponding to the number N of clock pulses, and data pulse The input to the first stage input of the shift register circuit is accepted, and this is circulated in the shift register circuit m times,
In the circulation process, a return control means for controlling each of the above means so as to output a data pulse via the i-th N-bit parallel output means is provided. Further, between the N-stage shift register circuit and the m N-bit parallel output means, N-bit parallel output of the shift register circuit for receiving N-bit parallel output and converting and boosting the output is output.
A level shift circuit is provided.

[Action]

According to this structure, first, when the data pulse arrives at the input switching means, the data pulse is input to the first stage of the shift register circuit through the input switching means under the control of the return control means, and sequentially in synchronization with the clock pulse. Although the serial transfer is performed, the first N-bit / parallel output means is selected by the return control means until the number of clocks N, so that every clock pulse is transmitted through the first N-bit / parallel output means. A data pulse that shifts to appears in the other N-bit parallel output means. The switching means is opened by the control of the return control means up to the number of clocks N, the input of the first stage and the output of each stage are conducted, and at the time of the number of clocks N, they are connected to the external output terminals for cascade connection. The data pulse is not output and is returned to the first stage of the shift register circuit. At the time when the number of clocks is N + 1, the data pulse is captured in the first stage and
The nth N-bit parallel output means is selected by the control means, and the clock pulse is the second until the clock number N + 1 to 2N.
The N th bit, which appears through the parallel output means, and the other N
It does not appear in the bit / parallel output means.

In this way, the circulation of the clock pulse in the shift register circuit and the scanning selection of the N-bit / parallel output means are performed. In the last m-th circulation process, the switching means is closed and the first stage is selected. The input and the output of the final stage are cut off, and the supply of a data pulse from the shift register circuit to the shift register circuit side of the next stage and the incoming of a new data pulse are permitted.

Therefore, since the number of stages of the shift register circuit is N and the number of output bits is mN, the shift register circuit of mN stages is apparently provided. Therefore, the number of bits can be increased without increasing the occupied area (number of elements) of the shift register circuit.

〔Example〕

 Next, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a common drive semiconductor integrated circuit for an LCD according to the first embodiment of the present invention. In FIG. 1, the same parts as those shown in FIG. 4 are designated by the same reference numerals, and the description thereof will be omitted.

The semiconductor integrated circuit of this embodiment includes an N-stage (N-bit) shift register circuit 4, an input switching circuit 7, a next-stage output switch circuit 8, two N-bit / parallel output circuits 9 ₁ and 9 ₂ , and a return control. Circuit 10, 2N bit level shift circuit 11, and 2N
It is composed of a bit driver circuit 12.

The input switching circuit 7 is composed of two AND gates 7a and 7b and one OR gate 7c, and the input D of the shift register circuit 4 is
In contrast to this, the data pulse DI and the output Q _N of the final stage (Nth bit) of the shift register circuit 4 are selectively supplied, which is performed under the control of the return control circuit 10 described later. The next-stage output switch circuit 8 is composed of a single AND gate 8a, and conducts / interrupts the output Q _{N to} the external output terminal 3 for cascade connection under the control of the return control circuit.
N-bit parallel output circuit 9 ₁ has N AND gates 9 _{11 to} 91 _N
One input of each AND gate is connected to the outputs Q _{1 to} Q _N of the corresponding stages of the shift register circuit 4, and the other input of each AND gate is connected to the return control circuit 10. There is. The N-bit parallel output circuit 9 ₂ also the N AN
D gates 9 _{21 to} 92 _N , one input of each AND gate is connected to the corresponding output Q _{1 to} Q _N of the shift register circuit 4, and the other input of each AND gate is an inverter 9a. Is connected to the return control circuit 10 via.

The return control circuit 10 receives the first-stage output Q ₁ of the shift register circuit 4 as an input, and outputs the above-mentioned N-bit parallel output circuit.
T flip-flop 10a supplied to 9 ₁ and 9 ₂ and an AND gate 10b which receives the output O of the T flip-flop 10a and the N-1th stage output Q _N-1 of the shift register circuit 4 as inputs.
And the output of the AND gate 10b is the set input S, and the second stage output Q ₂ of the shift register circuit 4 is the reset input R
It is composed of a flip-flop 10c. The Q output of the SR flip-flop 10c is supplied as one input of the AND gate 7b of the input switching circuit 7. The N-th bit output Q _N of the shift register circuit 4 is supplied to the other input of the AND gate 7b. SR flip-flop 10
The output of c is supplied as one input of the AND gate 7a of the input switching circuit 7, and the output of the switching circuit 8 for the next stage output.
It is supplied as one input of the AND gate 8a.

The 2N-bit level shift circuit 11 outputs the outputs P _{1 to} P _2N of the N-bit parallel output circuits 9 ₁ and 9 ₂ from the logic power supply voltage level to L level.
2N each for boost conversion to the power level for CD drive.
Bit driver circuit 12 is for delivering the LCD power supply voltage V ₀ to ~V ₅ to AC drive waveform signal electrode applied voltage Y ₁ to Y _2N in one-to-one correspondence with the output of the level shift circuit 11.

Next, the operation of the above embodiment will be described with reference to FIG.

The frequency of the data pulse DI in this embodiment is 1 / 2N of the frequency of the clock pulse CP. First, when the data pulse DI arrives at the input switching circuit 7, the output of the SR flip-flop 10c is at the H level. Therefore, the data pulse DI passes through the input switching circuit 7 and is input to the shift register circuit 4 in synchronization with the first clock pulse CP.
As a result, the output Q ₁ of the first stage becomes H level, the output O of the T flip-flop 10a becomes H level, and the N-bit parallel output circuit 9 ₁ is selected.

Next, when the second clock pulse CP comes in, the shift operation of the shift register circuit 4 causes the second stage output Q ₂
Becomes H level, but SR flip-flops up to here
Since 10c is in the reset state, flip-flop 10c
Is still in reset.

When the (N-1) th clock pulse CP arrives, N-
Since the output of the first stage Q _N-1 becomes H level, the SR flip-flop 10c enters the set state, and the AND gate 7b of the input switching circuit 7 becomes 1 of the output of the N stage Q _N by the H level of the Q output.
Allowing to return to the stage and AND by L level of output
When the gate 7a is cut off, the AND gate 8a is also cut off. Next, when the Nth clock pulse CP comes in,
Although the Nth stage output Q _N becomes H level, this H level output is not transferred to the output terminal side but is applied to the input D of the shift register circuit 4 via the input switching circuit 7. And the Nth
When the + 1st clock pulse CP comes in, the first output Q ₁ becomes H level, which causes the output O of the T flip-flop 10a to become L level, so that the inverter 9a
N-bit parallel output circuit 9 ₂ is selected by the output.
Next, when the N + 2nd clock pulse CP comes in,
The output Q ₂ of the second stage becomes H level, which causes the SR flip-flop 10c to be in the reset state, so that the AND gate 7b is cut off and the AND gate 7a is in the passage permitting state for the next data pulse. , And the AND gate 8a is closed. Thereafter, each time a clock pulse CP is applied, the data pulses are sequentially serially transferred, the output P ₁ to P _N therebetween N-bit parallel output circuit 9 ₁ are all L level, also the N-bit parallel Output circuit 9 ₂ output P _{N + 1}
~ P _2N changes H level from left to right one by one. In this N-bit parallel output circuit 9 _second selection period, the 2N-
When the first clock pulse CP comes in, the output Q _N-1 of the (N-1) th stage becomes H level, but the T flip-flop
Since the output O of 10a is at the L level, the SR flip-flop 10c remains in the reset state. Then, when the 2nd Nth clock pulse comes in, the output Q _N of the Nth stage becomes H
This becomes a level, and this is supplied as a serial output DO to another N-bit shift register circuit side not shown in the figure through the AND gate 8a and the output terminal 3 in a cascade connection.

Thus, during the period from the first clock pulse to the second Nth clock pulse (2N bits), the outputs P _{1 to} P _2N of the N-bit parallel output circuits 9 ₁ and 9 ₂ are as shown in FIG. Transition to. That is, generally, only the output P _i of the i-th bit becomes the H level at the arrival of the i-th clock.
This has the same effect as when a 2N-bit shift register circuit is provided. As in the present embodiment, the N-bit shift register circuit 4 is provided without providing the 2N-bit shift register circuit, and the input switching circuit 7, the AND gate 8a, the return control circuit 10 and the N-bit parallel output circuit 9 ₁ , 9 ₂ when was provided, significant reduction in the number of gates is achieved. That is, the shift register circuit alone can reduce 8N gates.
Compared with that, the total number of gates of the input switching circuit 7, the return control circuit 10 and the AND gate 8a is small, and the number of gates of the N-bit parallel output circuits 9 ₁ and 9 ₂ is a buffer circuit which is usually provided in the conventional circuit. Since the number of gates is almost the same as the number of gates (not shown in FIG. 4), the number of gates does not double even if the number of bits is doubled, and the chip size can be reduced by saving the element occupation area. There is. Therefore, it is possible to provide an integrated circuit that promotes the increase in the number of bits at a low cost in combination with the improvement in the yield. Further, reduction of the number of elements also contributes to reduction of power consumption.

FIG. 3 is a block diagram showing a common driving semiconductor integrated circuit for an LCD according to a second embodiment of the present invention. The third
In the figure, the same parts as those shown in FIG. 1 are designated by the same reference numerals, and the description thereof will be omitted.

The difference of this embodiment from the first embodiment is that the LCD drive voltage is supplied through an N-bit level shift circuit 13 having inputs corresponding to the parallel outputs Q _{1 to} Q _N of the N-bit shift register circuit. After converting to a level in advance, N bits
It is supplied to the parallel output circuits 9 ₁ and 9 ₂ and the output is input to the 2N-bit driver circuit.
Level shift circuit 1 for converting the voltage level of the output O of 10a 1
Have 3a. The operation timing is the same as in the first embodiment.

In the second embodiment, the N-bit level shift circuit 13 which is half the number of bits of the 2N-bit level shift circuit 11 is sufficient as compared with the case of the first embodiment, and the circuit configuration is further reduced. To do.

Although the same data pulse in the N-bit shift register circuit 4 is passed (circulated) twice in each of the above-described embodiments, mN-bit parallel output can be obtained by circulating the same data pulse m times. . However, since the circulation control becomes complicated, the circulation up to 3 times is practical.

〔The invention's effect〕

As described above, the present invention is characterized in that the data pulse is circulated through the N-stage shift register circuit a plurality of times, and m N-bit parallel output circuits are sequentially switched and selected for each circulation process. Since it is a thing, it has the following effects.

The total number of gates of the return control means and the like is smaller than the total number of gates of the additional stages of the shift register circuit, and the circuit configuration is reduced as a result rather than increasing the number of stages of the shift register circuit. Also, by reducing the chip size and improving the yield, an inexpensive integrated circuit can be provided. Moreover, since the number of elements does not increase in proportion to the increase in the number of bits, low power consumption can be realized.

In addition, the parallel output of the N-stage shift register circuit is set to N
In the case of the configuration in which the signal is supplied to the N-bit parallel output circuit through the bit / level shift circuit, the configuration of the level shift circuit, that is, the number of elements can be reduced, so that the above effect becomes more remarkable. .

[Brief description of drawings]

FIG. 1 is a block diagram showing a common drive semiconductor integrated circuit for an LCD according to the first embodiment of the present invention. FIG. 2 is a timing chart showing timings of various signal waveforms in the embodiment. FIG. 3 is a block diagram showing an LCD common drive semiconductor integrated circuit according to a second embodiment of the present invention. FIG. 4 is a block diagram showing a conventional LCD common drive semiconductor integrated circuit. [Description of symbols] 1 ... Data input terminal 2 ... Flock pulse input terminal 3 ... External output terminal for cascade connection 4 ... N-bit shift register circuit 7 ... Input switching circuit 8 ... Next stage output switch Circuit 9 ₁ , 9 ₂ N-bit parallel output circuit 10 Return control circuit 11 2 N-bit level shift circuit 12 2 N-bit driver circuit 13 N-bit level shift circuit 7a, 7b, 8a, 10b, 9 _{11 to} 9 _1N , 9 _{21 to} 9 _2N ...... AND gate 7c ...... OR gate 9a ...... Inverter 10a ...... T flip flop 10b ...... SR flip flop 13a ...... Level shift circuit.

Claims (2)

(57) [Claims] 1. An N-stage shift register circuit for serially transferring a data pulse, which comes in every cycle corresponding to a multiple mN of the number N of clock pulses, in synchronization with the clock pulse from the first stage to the last stage. Input switching means for switching and connecting the data pulse input terminal and the final stage output of the shift register circuit with respect to the first stage input of the shift register circuit, and connecting / disconnecting the final stage output and the external output terminal. Switching means for performing, m N-bit parallel output means for scanningly distributing and outputting the N-bit parallel output of the shift register circuit for each period corresponding to the number N of clock pulses, and the shift register for the data pulse. It receives an input to the first stage input of the circuit and circulates it m times in the shift register circuit, and in the ith cycle, the ith N-bit parallel output means. Multi-bit driver semiconductor integrated circuit characterized by having a a return control unit for controlling said respective means to output the data pulse through. 2. The N-bit parallel output of the shift register circuit according to claim 1, between the N-stage shift register circuit and the m N-bit parallel output means. A multi-bit driving semiconductor integrated circuit, characterized in that an N-bit level shift circuit for boosting and converting and outputting is provided.