JPH02282722A - Liquid crystal driving circuit - Google Patents

Abstract

PURPOSE:To make a beautiful display without any decrease in display brightness by including a delay circuit which outputs a signal delayed a specific time behind a liquid crystal AC signal (frame signal) and a signal delayed a specific time delayed behind a clock signal or latch pulse, and providing an output control circuit which controls an output circuit. CONSTITUTION:The control circuit signal (A signal) generated from the clock signal or latch pulse through a delay circuit or the control circuit signal (B signal) generated from the frame signal through a delay circuit, the output data of a shift register or latch, and the frame signal area ORed to control respective gates of the 4-level analog switch of the output circuit. Consequently, a waveform which lowers the display contrast of a panel does not appear in a driver output because of the delay time of the data and frame signal and beauty display can be made without any decrease in the display brightness.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a liquid crystal drive circuit used for driving a dot matrix type liquid crystal display panel.

[Conventional technology]

Conventionally, an IJ type liquid crystal panel is driven based on the voltage averaging method, and it is common to use an LSI-based liquid crystal drive circuit (hereinafter also referred to as an LCD driver) as shown in Fig. 13. . In this figure, 4 is a shift register in the case of the scanning electrode side (common') LCD driver, and a latch circuit is connected to the shift register and the output of the shift register in the case of the data electrode side (segment) LCD driver. This is a circuit with a Output data DATA from this shift register is input directly or via a latch circuit to a level shifter 3, level-converted, and input to an output circuit 2 to output terminal 1 (O6 to On>
is output from. Note that SI is a serial input, and SO is a serial output.

FIG. 8 shows a circuit for one bit of the driver array in the LCD driver. Output data from the shift register is level-converted and inputted from terminal 39, and level-converted from another system and inputted to terminal 38. Inverters 36, 37, NAND circuit 32
-35 and inverters 26-31, FETs 22-25, which constitute a 4-level analog switch, are turned on.
, is turned off and turned into an alternating current. Here, vl is a selection potential (highest potential) on the high potential side, and VEE is a selection potential (lowest potential) on the low potential side. Further, v2 is a non-selection potential on the high potential side, and v5 is a non-selection potential on the low potential side. In addition, 22.23 is P channel FET, 24.25 is N
It is a channel FET.

[Problem to be solved by the invention]

For example, when driving a dot matrix type liquid crystal panel with the circuit configuration shown in FIG. 8 using the logic based on the truth table of the liquid crystal drive output shown in FIG. 9, the output level is selected by the logical sum of the data DATA and the frame signal FR. Therefore, if a shift register 4 in which data is shifted at the falling edge of the clock signal CLK is used, as shown in FIG. 10, if the frame signal FR lags the data DATA by time B, the liquid crystal drive waveform of the driver output will be As in (6),
Unexpected Vl and VEE levels appear in the output waveform.

Also, in Figure 11, if the frame signal FR is 12 hours earlier than the data DATA, the output waveform will be as shown in
V2. The V5 level is output for t2 hours. As a result, pixels that are originally in an off state become halftone, which lowers the contrast of the liquid crystal panel, and also impairs the reliability of the panel due to deviations in the effective value of the voltage applied to the pixels.

SUMMARY OF THE INVENTION An object of the present invention is to provide a liquid crystal drive circuit that solves these conventional problems and enables beautiful display without reducing display brightness.

[Means to solve the problem]

In order to solve the above problems, the liquid crystal drive circuit of the present invention has the following features:
A delay circuit that takes a liquid crystal alternating current signal (frame signal) as an input and outputs a signal delayed by a predetermined time from the rise and fall of the input, and a delay circuit that takes a clock signal or latch pulse as an input and outputs a signal delayed from the rise and fall of the input. Alternatively, it is characterized in that it includes at least one of a delay circuit that outputs a signal delayed by a predetermined time from the falling edge, and includes an output control circuit that controls the output circuit.

[Effect]

According to the above configuration of the present invention, the control circuit signal (
A signal) or a control circuit signal (B signal) created from the frame signal through a delay circuit, the output data of the shift register or latch, and the frame signal are logically summed, and the 4-level analog switch of the output circuit is control each gate.

When the A signal or B signal goes to the L level, the 4-level analog switches in the output circuit all go into a high impedance state, and the data and frame signals change H-L or L-H during the L level. is carried out, and after a predetermined time,
Only the lFET according to the truth table is turned on. Therefore, the level caused by the phase difference between the data and the frame signal is not output to the driver output. In addition, when the driver output is high impedance, the potential of the scan electrode or data side electrode on the panel side is held at the potential immediately before high impedance due to the panel capacitance, so the apparent delay time of the driver output is It is the same as increasing the size by the time of , but does not reduce the contrast on the panel side.

〔Example〕

FIG. 1 is a circuit diagram showing an output circuit according to an embodiment of the present invention, and the same parts as in FIG. 8 are denoted by the same reference numerals.

The one in this figure is a high-voltage circuit, 38°39,
67 inputs the frame signal FR, the data DATA which is the output of the shift register or latch, and the A signal or B- signal after converting the level to a high voltage, and inputs the 3 inputs N.
Input to AND circuit 320.330.340°350.

The circuits for producing the F signal or the B signal are shown in FIGS. 2, 3, and 4.

Figures 2 and 3 are examples of circuits that generate signals from the clock signal CLK or latch pulse LP, which are pulses (hereinafter referred to as high-impedance pulses) for making the output high-impedance, and which clock the shift register or latch. When outputting at the falling edge of the signal CLK or latch pulse LP, use the example shown in Figure 2, and when outputting at the rising edge, use the example shown in Figure 3. The input and output waveforms of these circuits are shown in Figure 5. , as shown in Figure 6.

Figure 4 shows an example of a circuit that generates a zero impedance pulse B signal from the frame signal FR. In this example, the driver output changes each time the frame signal FR changes from H to LSL to H, so It is necessary to create high impedance at the rising and falling edges of the frame signal FR.

The delay circuit 8 shown in FIGS. 2 to 4 is composed of an even number of inverter stages, and a delay signal in phase with the input is sent to the input.
Created by inverter delay time.

This delay signal is set to be slightly longer than the response time of the level shifter, and slightly longer than the two hours shown in B of FIG. 1O and FIG. 11.

FIG. 12 shows the clock signal CLK or latch pulse L.
The input/output waveforms are shown when eight high-impedance pulse signals are generated at the falling edge of P and input to the one in FIG. In this case, there is a phase difference between the output data DATA of the shift register or latch and the frame signal FR, but the signal between them is in the L period, the driver output becomes high impedance, and the panel side electrode potential changes depending on the panel capacitance. , the potential immediately before high impedance is held.

When the signal goes to H level, the driver output is controlled by the output data DATA of the shift register or latch and the frame signal FR according to the logic shown in the truth table of FIG.

Also, as shown in Figure 11, if the frame signal FR is earlier in phase than the data DATA, this can be solved by using the circuit in Figure 4 and inputting the B signal, but normally the signal from the controller is clock signal CLK. Since the signal is frequency-divided to create the frame signal FR, the frame signal FR is generally delayed as shown in FIG. 12. In addition, as an application of the panel driving method, a signal obtained by the logical sum or logical product of the output 11 in FIG. 2 and the output 14 in FIG. 4, or the output 11 in FIG. 3 and the output 14 in FIG. 4 is used as a high impedance pulse. You can also do that.

The drive circuit of the present invention can be applied to both a scanning side driver and a data side driver.

[Effects of the Invention] As described above, if the drive circuit of the present invention is used, a waveform that lowers the display contrast of the panel will not be output to the driver output due to the delay time of data and frame signals, and the display brightness will also be reduced. Beautiful display can be obtained without lowering the display.

In addition, since the output circuit is made high impedance,
Excessive through current caused by simultaneous ON of Pch and Nch FETs that constitute the output driver can be eliminated, and the LS
The current consumption of I is reduced, and it becomes possible to implement panel mounting methods, high-speed operation, and multiple outputs, which were previously limited by the heat generated by the LSI itself.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the output circuit according to the present invention, FIGS. 2 to 4 are circuit diagrams showing different embodiments of the output control circuit according to the present invention, and FIGS. 5 to 7 are circuit diagrams showing different embodiments of the output control circuit according to the present invention. Time charts showing the operations of those in FIGS. 2 to 4, respectively;
FIG. 8 is a circuit diagram showing a conventional output circuit, FIG. 9 is a diagram showing a truth table for explaining the driving operation of the liquid crystal driving circuit to which the present invention is applied, and FIGS. FIG. 8 is a time chart showing the operation of the device, FIG. 12 is a time chart showing the operation of the embodiment of the present invention, and FIG. 13 is a block diagram showing the configuration of a liquid crystal drive circuit to which the present invention is applied. ■ Output terminal, 2 Output circuit, 3 Level shifter, 4
Shift registers (and latches), 22-25,...
,,,FET,CLK clock signal,
LP latch pulse, FR frame signal, vl High potential side selection potential, V2 High potential side non-selection potential, v5 Low potential side non-selection potential, VEE Low potential side selection potential, 6.7
Inverter, 8 delay circuit, 9.10.91°92,
101.102.320.330.340. :3! i
o、、、、、 N A N D times CLK (also 1 Yoshi P) CLK (or LP) CLK (or LP) CLK (or (also) LP) Figure Figure Figure

Claims (1)

[Claims] 1) A dot matrix type liquid crystal display panel equipped with a shift register that converts serial data into parallel data, and an output circuit having an FET that selects one level from four levels of liquid crystal drive power supply based on the parallel data and frame signal. In the liquid crystal drive circuit for driving, a delay circuit receives a liquid crystal alternating current signal as an input and outputs a signal delayed by a predetermined time from the rise and fall of the input;
It includes at least one of a delay circuit that receives a clock signal or a latch pulse as an input and outputs a signal delayed by a predetermined time from the rising or falling time of the input,
A liquid crystal drive circuit comprising an output control circuit that controls the output circuit.