JP2506855B2 - Video signal generation circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal generating circuit for generating a video signal, and more particularly to a special signal as a test signal source for a video semiconductor integrated circuit as well as a standard signal. It also relates to a circuit configuration in which various signals can be created in a programmable manner.

2. Description of the Related Art Conventionally, as shown in the block diagram of FIG. 3, a pattern generator having one frame as one cycle is configured to obtain various timing signals and video signals at logic signal levels. Fig. 4 shows the waveform of a 1-frame video signal. In the case of the NTSC system, there are 525 horizontal scanning lines and 3 per second.
0 screens are made by interlaced scanning, and a complete 1 screen (1 frame) is completed by 2 vertical scans.
When the video signal being generated is a still image, the signal has a period of 1/30 second. Although this signal is generated by a digital pattern, it is necessary to display one horizontal scan with a sufficiently fine resolution. If it is displayed with a resolution of, 64 × 525 = 33600 digital patterns will be generated in 1/30 second.

The configuration of the block diagram of FIG. 3 will be described. The output of the pulse generator 1 which serves as a clock signal for generating a video signal is used to generate a sequence of digital patterns. It is input to the input terminal 91 of the binary counter 9 for one horizontal scanning period). The output of the counter output terminal 92 is
The pattern data of the video signal for one frame is input to the address input terminal 101 of the memory 10 in which the pattern data is stored in order. The video signal pattern output from the output terminal 102 of the memory 10 is input to the latch 7 and triggered by the clock signal. Various timing signals can be DA converted from the output latched by the latch 7 and a video signal can be obtained by the DA converter 8.

Problems to be Solved by the Invention In such a conventional example, when various timing signals and video signals are generated, in order to obtain sufficient resolution,
Since it is necessary to increase the number of clocks for pattern generation to a frame frequency of 30Hz (NTSC method), a huge amount of memory is required for pattern generation. For example, NT
If the resolution of one horizontal scanning period is 1/64 in the SC method and the digital output is 16 bits to generate a digital pattern, the required memory is 64 x 525 x 16 = 537600.
It becomes [bit]. In view of the above point, the present invention has an object to provide a circuit that easily generates a video signal with a small amount of memory.

Means for Solving the Problems In order to solve the above problems, the present invention pays attention to the fact that a video signal for one frame is a stack of horizontal scanning line signals, and is 2n times the horizontal synchronizing signal in the video signal. A clock generating means for generating an original signal corresponding to a frequency of (n is an integer of 1 or more), a first binary counter for dividing the original signal by 1 / 2n, and an output signal of the first binary counter. 1 /
A second binary counter that divides by 1024, a first memory to which the output signal of the second binary counter is input to the address section, and which reads out horizontal scanning signal sequence data stored in advance in response to the input, and an address section The horizontal scanning signal sequence data and the output signal of the first binary counter are input to the second memory, and the second memory that reads out horizontal scanning signal pattern data stored in advance in response to the inputs and the clock input of the original signal is input. Latching means for latching the output signal of the second memory and a DA converter for DA converting the output signal of the latching means to generate various timing signals and video signals. The second binary counter is reset by an output signal of the latch means corresponding to a clock.

According to the configuration of the present invention, the obtained video signal is no different from the conventional video signal, and the memory required for pattern generation can be greatly reduced.

Embodiment FIG. 1 shows a block diagram of an embodiment of the present invention, and FIG. 2 shows a conceptual diagram thereof. As shown in FIG. 4, in the case of the NTSC system, the video signal is composed of 525 horizontal scanning lines per frame.
The five horizontal scanning lines can be classified into N types (for example, 9 types if all the horizontal scanning lines on the TV screen have the same pattern). That is, the conceptual diagram of FIG. 2 shows that when N horizontal scanning signals are selected by the selector, which horizontal scanning signal 525 horizontal scanning lines select for each horizontal scanning line, one frame image of NTSC system is obtained. It shows that a signal can be generated. Next, the configuration of the block diagram of FIG. 1 will be described. 1 is a pulse generator that determines the resolution of one horizontal scanning period of the video signal, and the required resolution is an index of 2. If (n: 5 or more is practical), the oscillation frequency is the horizontal oscillation frequency _{H of the} TV multiplied by 2n. This original oscillation is used to drive the horizontal scanning signal pattern. Input to the input terminal 21 of the first binary counter 2 and the most significant bit of the output terminal 22 is further input terminal of the 1/1024 second binary counter 3 for driving the horizontal scanning signal sequence.
Enter 31. The output of the counter output terminal 32 is horizontal scanning signal sequence data, that is, the address data input terminal 51 of the memory 5 storing the data on how to arrange N types of horizontal scanning signal patterns in one frame.
The horizontal scanning sequence data output from the output terminal 52 and the output of the output terminal 22 of the first binary counter 2 are input to the upper 61 of the address data input terminals of the memory 6 storing N types of horizontal scanning signal patterns. Then, enter each in the lower 62. Upper level of address data input terminal of memory 6
Reference numeral 61 is for controlling which of the N kinds of horizontal scanning signals is selected, and is a lower order 62 of the address data input terminal.
Is for generating one horizontal scanning signal pattern. The horizontal scanning signal pattern output from the output terminal 63 of the memory 6 is input to the latch 7, and the clock signal of the pulse generator 1 that is the original oscillation is the same edge as the edge that triggers the input terminal 21 of the first binary counter 2. Trigger latch 7. The inverter 4 is for matching the polarities of the first binary counter 2 and the latch (D type flip-flop) 7 which are triggered by a negative edge and a positive edge, respectively, in a general standard logic. When triggering at the same edge, the accumulated delay time by the first and second binary counters 2, 3 and the memories 5, 6 is allowed up to one cycle of the original oscillation. The output latched by the latch 7 can be used as it is as various logic level timing signals, or by the DA converter 8.
Can be used as a video signal after DA conversion.

One bit of these latch outputs is a clear terminal of the second binary counter 3 for generating the horizontal scanning signal sequence.
A video signal for one frame can be obtained by inputting to 33, using it for counter reset, and resetting at the 2nth clock of the final horizontal scanning signal pattern (525th line in the case of NTSC).

EFFECTS OF THE INVENTION As described above, according to the present invention, the memory for pattern generation in the video signal generation circuit can be greatly reduced by N / 525 times compared to the conventional example, and the memory for horizontal scanning signal sequence data can be reduced. The addition is only 525 x (decimal places above Log ₂ N) [bit].

[Brief description of drawings]

FIG. 1 is a block diagram showing a video signal generating circuit according to an embodiment of the present invention, FIG. 2 is a conceptual diagram thereof, FIG. 3 is a block diagram of a conventional video signal generating circuit, and FIG. 4 is an NTSC system video. It is a signal waveform diagram. 1 ... Pulse generator, 2 ... Binary counter, 3 ... 1/1024 Binary counter, 4
…… Inverter, 5 …… Memory, 6 …… Memory, 7 ……
Latch, 8 ... DA converter, 9 ... Binary counter, 10 ... Memory.

Claims (1)

(57) [Claims] 1. A 2n times (n is 1) horizontal sync signal in a video signal.
A clock generating means for generating an original signal corresponding to a frequency of the above integer), a first binary counter for dividing the original signal by 1 / 2n, and an output signal of the first binary counter for 1/1024 A second binary counter that rotates, an output signal of the second binary counter is input to an address section, and a first memory that reads out horizontal scanning signal sequence data stored in advance in response to the input; A horizontal scanning signal sequence data and an output signal of the first binary counter are input, a second memory that reads out horizontal scanning signal pattern data stored in advance in response to the input, and the memory is input in response to a clock input of the original signal. Latch means for latching the output signal of the second memory, and various timing signals and video signals by DA converting the output signal of the latch means And a DA converter that generates a video signal generating circuit, characterized in that resetting the second binary counter at the output signal of said latch means corresponding to a last clock of the horizontal scanning signal pattern data.