JPS6355070B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a raster scanned cathode ray tube (raster scanned cathode ray tube).
Regarding display devices that display characters, numbers, symbols, etc. (simply referred to as characters in this specification) on a CRT (hereinafter referred to as CRT), in particular, scanning speed, such as a scanning electron microscope,
The present invention relates to a character display device suitable for use in an apparatus having a viewing CRT whose number of scanning lines changes significantly.

For example, in scanning electron microscopes, CRT
In some cases, characters indicating the imaging conditions (magnification, accelerating voltage, etc.) of the image are displayed superimposed on the sample image. This character display is not limited to one line, but may include multiple lines. The character display is done by addressing a character generator by a vertical address obtained in response to a vertical scanning signal, and by using a dot pattern (usually 8x
8 bits per row (consisting of 8 dots) are read out in parallel, and outputted one dot at a time in synchronization with the horizontal address obtained in response to the horizontal scanning signal via a parallel-to-serial converter. This is done by adding it to the video signal and displaying it on a CRT.

By the way, the output data of the character generator is undefined during the access time, but if the vertical address changes during the horizontal scanning period, this undefined output may be taken into the parallel/serial converter. At that time, there was a problem that the data converted and output here was displayed on the CRT and appeared as noise on the screen.

The present invention has been made in view of these points, and its purpose is to prevent the vertical address from changing during the horizontal scanning period, so that the undefined outputs of the character generators can be parallelized and It is an object of the present invention to provide a character display device which suppresses noise from being taken into a serial converter and prevents noise from appearing on a CRT.

A feature of the present invention is that by latching the vertical address signal that specifies the address of the character generator with the horizontal blanking signal, the address signal that specifies the row of the character generator always changes during the horizontal blanking period. , to prevent inaccurate display from appearing on the CRT.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a character display device of the present invention. In the figure, 1 and 2 are analog-to-digital converters (hereinafter referred to as A/D converters), 3 is a memory that stores character data to be displayed in advance, 4 is a vertical address designation circuit, and 5 is a character generator (hereinafter referred to as A/D converter). (abbreviated as CG), 6 is a parallel/serial converter (hereinafter abbreviated as P/S converter), 7 is an adder,
8 is an amplifier, and 9 is a CRT. A/D converter 1
converts the horizontal scanning signal H having a sawtooth waveform into a digital signal at a sufficiently short period compared to the period of the horizontal scanning signal H, and outputs the digital signal. As an example, 32 pieces of data are displayed, so an 8-bit configuration output can be obtained. That is, among the 8 bits, the upper 5 bits correspond to the position of each character, and the lower 3 bits correspond to the position of a dot in one character. Similarly, the A/D converter 2 converts the vertical scanning signal V having a sawtooth waveform into a digital signal at a period sufficiently shorter than that period and outputs the digital signal. Since 16 items are to be displayed, the configuration is such that a 7-bit configuration output is obtained. Among the 7 bits, the upper 4 bits correspond to the position of each character, and the lower 3 bits correspond to each row of the dot string in one character. The data of the upper 4 bits and the lower 3 bits are led to the vertical address designating circuit 4, and are latched by a horizontal blanking signal that is output during retrace of horizontal scanning. In the memory 3, character data to be displayed on one screen is stored at an address corresponding to a CRT screen.
The character data is stored in advance by a computer (not shown) or the like. Address designation of each character data is performed by the outputs of A/D converters 1 and 2. That is, the upper 5 bits of the A/D converter 1 specify a horizontal address, and the upper 4 bits of the vertical address designation circuit 4 specify a vertical address. The CG5 is a character generator that stores a large number of characters in patterns each consisting of an 8x8 dot matrix, and generates characters using the character data ( _A0 to _A7 ) output from the memory 3. Can be specified. Furthermore, the lower three bits of the vertical address designation circuit 4 specify which dot string to output from the specified character pattern. The parallel dot string signal generated by the CG 5 is sent to the P/S converter 6. The P/S converter 6 is given the output of the lower 3 bits of the A/D converter 1, and converts the parallel dot string signal into a temporally serial character signal based on the 3-bit horizontal address. Send to adder 7. Adder 7 adds this character signal and image signal (video signal), and the resulting composite signal is sent via amplifier 8.
It is designed to be sent as a brightness signal to the CRT9 grid.

The operation of the apparatus of the present invention in such a configuration will be described next. The horizontal scanning signal is A/D converted by A/D converter 1, and the horizontal direction address (H address) is
get. At the same time, the vertical scanning signal is A/D converted by A/D converter 2 to obtain a vertical address (V address).
get. Top 5 of the 8-bit H address
The address to the memory 3 is composed of the bit and the upper 4 bits of the 7-bit V address. Memory 3 sends out the character data (8 bits) stored at the designated address. In response to this, the CG 5 selects a character pattern (indicating the number 8) of an 8×8 dot pattern as shown in FIG. 2A.
This character pattern is 0, 1 as shown in Figure 2 (b).
It is stored as a signal. On the other hand, the vertical address designating circuit 4 obtains a vertical address for one character from the A/D converter 2, and supplies this to the CG5. CG is in the specified character pattern,
Dot string data D ₀ of the row corresponding to this address
~D ₇ are output in parallel. P/S converter 6 is A/D
Based on the lower 3 bits of the H address output from converter 1, it is sequentially output from D ₇ to D ₀ . For example, CRT
When displaying the second line of the character pattern above,
001 is given as a vertical address to CG5, and thereby a pattern signal of 00011110 is given to P/S converter 6. P/S converter 6 is H address lower 3
Synchronizing with the bits changing to 0, 1, 2, 3, . . . , 6, 7, the bits are sequentially output as 0, 0, 0, 1, . . . , 1, 0. 0 of this character signal corresponds to a black level, and 1 corresponds to a white level luminance signal, which is superimposed on a video signal (in some cases without a video signal) by an adder 7, and is applied to a CRT 9 via an amplifier 8.
In this way, one line of character pattern (D ₀ to D ₇ )
is displayed as a dot.

The next character in the horizontal direction is displayed in the same manner as described above. When character display in one horizontal direction is completed in this way, the same operation as described above is repeated for the next row of dot columns. In this case, the vertical address designation circuit 4 always latches and outputs the V address with the horizontal blanking signal, so even if the V address of the A/D converter 2 changes during one horizontal scanning period, it will not be output during one horizontal scanning period. is designed not to change. Therefore, an unstable output of the CG5 during horizontal scanning is not displayed, and high-quality character display without noise is guaranteed.

As explained above, according to the present invention, the vertical address for addressing the character generator can change in synchronization with the horizontal blanking signal, so that the vertical address does not change during the horizontal scanning period. It is possible to prevent problems such as displaying an irregular character pattern and noise being mixed into the displayed characters.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a character display device according to the present invention, and FIG. 2 is a diagram showing an example of a character pattern. 1, 2...A/D converter, 3...memory, 4...
...Vertical address designation circuit, 5...Character generator, 6...P/S converter, 9...CRT.

Claims (1)

[Claims] 1. Specify the character data related to the character to be displayed based on the address obtained by digitally converting the horizontal scanning signal and the vertical scanning signal, and correspond to the specified character data from among a large number of dot matrix character patterns. In an apparatus for displaying characters by selecting a character pattern, transmitting a character pattern signal in which a line to be transmitted is determined based on a vertical address signal obtained by digitally converting the vertical scanning signal, and supplying the signal to a cathode ray tube. . A character display device, characterized in that the vertical address signal changes only during a blanking period of horizontal scanning to designate a line in which a character pattern is to be sent.