JPS63108379A - Contrast converter - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a gradation conversion device that converts a multivalued signal converted into an electrical signal by an image sensor into black and white binary image data.

[Conventional technology]

Conventionally, in this type of device, when reproducing a video signal having halftones converted into an electrical signal by a solid-state image sensor, etc., such as a COD, a specific value is determined from the bit value of the input video signal. It was binarized using a binarization pattern.

FIG. 5 is a block diagram illustrating the configuration of a conventional gradation conversion device, and 31 is an A/D converter that converts the input video signal into an electrical signal by a solid-state image sensor such as a COD (not shown). Convert to digital body signal. Reference numeral 32 denotes a binarized pattern memory, which converts a certain pattern signal from the conversion matrix shown in FIG. A pattern signal conforming to the digital input/output level characteristics shown in FIG. 7 is outputted to the digital output system 1, for example, a laser beam printer, or the pattern signal is outputted to the D/A converter 33 to be converted into an analog signal, For example, the D/A converted pattern signal is output to a CRT display or the like.

FIG. 6 is a schematic diagram illustrating a conversion pattern matrix stored in the binarized pattern memory 32 shown in FIG.

FIG. 7 is a digital input/output level characteristic diagram, where the vertical axis shows the output level and the horizontal axis shows the input level.

In this figure, the conversion characteristic is a digital scale that has a constant slope and has a uniformly constant output level depending on the level of the digital grayscale signal input to the A/D converter 31. Outputs the modulation signal.

When the video signal from the image sensor inputted by the A/D converter 31 is converted into a 4-bit digital gradation signal, for example, 4-bit ro011J2, the bit value of the converted digital gradation signal is "5". ”, the conversion pattern matrix shown in FIG. 6 is addressed. Therefore, in the conversion pattern shown in FIG. 6, a signal is output to the D/A converter 33 in which pixels from θ to 5 are black pixels and the remaining pixels are white pixels.

[Problem that the invention seeks to solve]

For this reason, since the input video signal for one screen is binarized using the same binarization pattern as shown in Figure 6, regular patterns may occur in the output image, and fine details in one screen may appear. There were problems such as loss of smoothness in some parts.

In addition, since the gradation of one screen is converted according to the digital input/output level characteristics shown in Figure 7, even if there is a request to see the difference in shading in a low gradation area, for example, it cannot be handled. Even if gradation conversion is performed using a matrix different from the conversion pattern matrix shown in FIG. Even if you can cope with
Similar problems occur in other areas of the screen.

This invention was made in order to solve the above-mentioned problems, and by having a plurality of binarized patterns stored in advance specify the gradation pattern within a specified area on the screen, the specified gradation pattern can be specified. An object of the present invention is to obtain a gradation conversion device that can freely vary the gradation within a region.

[Means for solving problems]

A gradation conversion device according to the present invention includes an image memory that stores an input digital gradation signal, and a binarization pattern for pseudo-converting the digital gradation signal stored in the image memory into a black and white binary signal. A pattern memory that stores a plurality of patterns, an arbitrary area in an image that is binarized by one binarization pattern selected from this pattern memory, and output to an output device, and a binarization pattern in the pattern memory. is an instruction means for instructing a different binarization pattern, a digital gradation signal corresponding to an area instructed by the instruction means, and a digital gradation signal read out based on the binarization pattern instructed by the instruction means. 2
and output control means for outputting the digitized black and white binary signal to the output means.

[Effect]

In this invention, when a digital gradation signal read from one image memory is converted into black and white binarized by one binary pattern in the pattern memory and outputted to the output means, the instruction means selects an arbitrary area on the output means. When a binarization pattern different from the above-mentioned binarization pattern is instructed, the output control means reads out a digital gradation signal corresponding to the area indicated by the instruction means,
A black and white binary signal obtained by binarizing the digital gradation signal read out based on the value pattern is output to the output means.

〔Example〕

FIG. 1(a) is a block diagram illustrating the configuration of a gradation conversion device showing an embodiment of the present invention, in which 1 is an A/D converter, and 1 is a solid-state image sensor provided in an Sv camera and an image scanner (not shown). A/D conversion is performed on a video signal VDO or an NTSC signal from a video, SV recorder, etc., which has been converted into an electrical signal by the element. 2 is an image memory, and A/D converter 1
A/D converted digital gradation signal is stored based on the address generated by the address generation circuit 3.The address generation circuit 3 includes a horizontal synchronization signal H5YNC for storing video signals, a vertical synchronization signal vSYNC and an address. A clock signal CK for generating generation timing is sent from an MPU (output control means) shown in FIG. 4 is a pattern memory section which stores matrix patterns MPs to MPn having the input/output characteristics shown in FIG. 1(b).
It outputs the black and white binary signals converted by the matrix patterns MP to MPn directly to the CRT display 5 serving as an output means or to the D/A converter 6. 7
A display pattern selection memory stores pattern selection information S instructed by the pointing device shown in FIG. 2, and selects an arbitrary matrix pattern in the pattern memory section 4 according to instructions from the MPU (described later).

FIG. 1(b) is an input/output level characteristic diagram converted by the matrix pattern MPI"MPn shown in FIG. 1(a), where ■!~r1n is the input/output level characteristic, and the larger the slope, the more This figure shows a case where the number of black pixels increases.

FIG. 2 is a block diagram illustrating the system configuration of an image processing system having the tone conversion device shown in FIG. 1(a), and the same components as in FIG. 1(a) are given the same reference numerals. It is.

In this figure, °11 is the controller section lMPU1
1a, a program memory (PMEM) 11b, etc., and the MPU 11a performs overall control of each metropolitan den based on a control program stored in the program memory 11b. 12a is a keyboard for inputting control information, numerical information, etc.;

12b is a pointing device that indicates an arbitrary area in the black and white binary signal displayed on the CRT display 5 and pattern selection information for black and white binary conversion. 13
is a bidet RAM (VRAM) that stores pixel data to be displayed on the CRT display 5 in a bitmap.

An image memory 14 stores image data to be output to one of the output units 15, for example, a laser beam printer 15a.

Reference numeral 15b denotes an interface circuit that interfaces the exchange of image data stored in the image memory 14 or the transfer of control signals from the laser beam printer 15a to the MPU 11a. 16 is Bit Move Units) (BM
U) controls the rotation and movement of image data.

FIG. 3 is a schematic diagram illustrating the gradation conversion display instruction operation according to the present invention, and the same parts as in FIG. 1(a) are given the same reference numerals.

In this figure, El and E2 are designated areas, which are designated by the pointing device 12b. Note that the pointing device 12b specifies the range by specifying, for example, diagonal coordinates of the specified area EIIE2.

First, the operator converts the gradation data stored in the image memory 2 into a specific pattern, for example, matrix pattern M.
When the pointing device 12b gives an instruction to binarize the data using P& and display it on the entire CRT display 5, the pattern selection information S is stored in the display pattern selection memory 7. At this stage, the horizontal synchronization signal H5YN is sent from the address generation circuit 3 based on the command sent from the MPU 11a.
An address signal is sent to the image memory 2 and the display pattern selection memory 7 in synchronization with the C1 vertical synchronization signal VSYNC, and a black and white binary signal binarized based on the matrix pattern MPs is displayed on the CRT display 5. 3
It is displayed on one screen as shown in the figure.

Here, the operator operates the pointing device 12b to point to the diagonal coordinates of an arbitrary designated area E I * E 2, and also designates a matrix pattern for binarizing the designated areas El and E2. Then, the pattern selection information S is sent from the MPU 11a.
is sent to the display pattern selection memory 7, and the instruction area E! .

Address information corresponding to E2 is sent to address generation circuit 3. In response to this, the address generation circuit 3 sends a read address to the image memory 2 and the pattern memory section 4, and the gradation data corresponding to this read address, that is, the gradation data in the designated areas E, E2, is generated. Pointing device 1 reads out the instruction area El.
2b, for example matrix pattern MA5. The designated area E2 is binarized using a matrix pattern designated by the pointing device 12b, for example, matrix pattern MA9, and the binarized black and white binary signal is transferred to the CRT display 5. This allows the CRT display 5 to simultaneously display a plurality of binarized images using different matrix patterns. Note that since the image memory 2 stores the gradation data displayed on the CRT display 5, the same or different areas can be binarized with different matrix patterns any number of times by operating the pointing device 12b.

Next, the binarization processing operation according to the present invention will be explained with reference to the flowchart shown in FIG.

FIG. 4 is a flowchart illustrating a display control operation procedure by binarization processing according to the present invention.

Note that (1) to (,111,,) indicate each step.

Display the matrix pattern selection screen on the CRT display 5 (1), wait for the matrix pattern to be selected by the pointing device 12b (2), and when the matrix pattern is selected, the MPU 11a will display the readout address of the gradation data stored in the image memory 2. Information address generation circuit 3
1 and read out gradation data from the image memory 2 based on the read address generated by the address generation circuit 3.

The binarized black and white binary data is binarized based on the matrix pattern selected in step (2) (3). The binarized black and white binary data is displayed as a list on the CRT display 5 (4). Next, the pointing area is displayed using the pointing device 12b. 5), and when the designated area is designated, the pointing device 12b is
Wait for the matrix pattern to be selected by 6.
), pattern selection information S specifying the matrix pattern
is stored in the display pattern selection memory 7 (7) 0 Next, when address information for generating a read address corresponding to the designated area is input from the MPU 11a to the address generation circuit 3, the address generation circuit 3 generates the read address. is output to the image memory 2 (8), the gradation data corresponding to the designated area is read out from the read address (9), and is binarized using the matrix pattern stored in the display pattern selection memory 7 ( 1G) 0 Next, the black and white binary signals that have been binarized using different matrix patterns are output to the CRT display 5, and as shown in FIG. is displayed (11).

In the above embodiment, a case has been described in which the output means is constituted by a CRT display 5, but the present invention can be easily applied to a case in which the output means is constituted by a laser beam printer 15a shown in FIG.

〔Effect of the invention〕

As explained above, the present invention includes an image memory that stores an input digital gradation signal, and a binarization pattern for pseudo-converting the digital gradation signal stored in the image memory into a black and white binary signal. What is a pattern memory that stores multiple patterns, an arbitrary area in an image that is binarized by one binarization pattern selected from this pattern memory, and output to an output device, and a binarization pattern in the pattern memory? An instruction means for instructing a different binarization pattern, a digital gradation signal corresponding to an area instructed by the instruction means, and a digital gradation signal read out based on the binarization pattern instructed by the instruction means. 2
Since output control means for outputting the digitized black and white binary signal to the output means is provided, for example, a specified area of the gradation data displayed on the display can be binarized and displayed in different patterns. Therefore, images can be displayed clearly with arbitrary shading. In addition, when there are vertical patterns, horizontal patterns, diagonal patterns, etc. on the same screen, it is possible to have a corresponding matrix pattern, smoothing the image quality of areas with vertical patterns, horizontal patterns, diagonal patterns, etc. on the same screen. Can be done. Furthermore, since the gradation data is held in the image memory, it has excellent advantages such as being able to binarize the same area or different areas as many times as desired using any matrix pattern.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram illustrating the configuration of a gradation conversion device showing an embodiment of the present invention, and FIG. 1(b) is a block diagram illustrating the structure of a gradation conversion device according to an embodiment of the present invention. Input/output level □ characteristic diagram, FIG. 2 is a block diagram illustrating the system configuration of an image processing system having the gradation conversion device shown in FIG. 1(a), and FIG. 3 is a gradation conversion display according to the present invention. FIG. 4 is a schematic diagram illustrating the instruction operation, FIG. 4 is a flowchart illustrating the display control operation procedure by binarization processing according to the present invention, FIG. 5 is a block diagram illustrating the configuration of a conventional gradation conversion device, and FIG. is a schematic diagram for explaining the conversion pattern matrix stored in the binarized pattern memory shown in FIG. 5, and FIG. 7 is a digital input/output level characteristic diagram. In the figure, 1 is an A/D converter, 2 is an image memory, 3 is an address generation circuit, 4 is a pattern memory section, 5 is a CRT display, 6 is a D/A converter, 7 is a display pattern selection memory, 11a is an MPU, and 12b is a pointing device. Figure 1 (a) Single power level 16 Figure 2 Figure 4 Figure 3 Figure 6 Figure 7 Crying input level

Claims (2)

[Claims] (1) In an image processing apparatus having an output means for pseudo-converting an input digital gradation signal into a black and white binary signal and outputting the resultant signal, an image memory for storing the input digital gradation signal, and an image memory for storing the input digital gradation signal; a pattern memory that stores a plurality of binarization patterns for pseudo-converting the stored digital gradation signal into a black and white binary signal; an instruction means for instructing an arbitrary area in an image to be outputted to the output device and a binarization pattern different from the binarization pattern in the pattern memory;
A black and white binary signal is obtained by reading out the digital gradation signal corresponding to the area specified by the instruction means and binarizing the digital gradation signal read out based on the binary pattern specified by the instruction means. What is claimed is: 1. A gradation conversion device comprising: output control means for outputting to output means. (2) The output control means reads the digital gradation signal corresponding to the same area indicated by the instruction means, and re-outputs the black and white binary signal binarized with different binarization patterns to the output means multiple times. A gradation conversion device according to claim (1), characterized in that: