JP2506720B2 - Encoder - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding apparatus in hierarchical coding in which images thinned out in a first stage are coded, and images complementing the gaps are sequentially coded in a second stage and thereafter. It is a thing.

2. Description of the Related Art With the diversification of facsimile communication, it has been considered to use a facsimile terminal in combination with a display terminal for interactive image communication and image database search. Compared to conventional encoding methods such as MR method which sequentially encodes from the top to the bottom of the image according to scanning lines,
As a coding method suitable for such conversational image communication, a method of performing a hierarchical coding process has been proposed. In the decoding process using the hierarchical encoding method, a rough image is displayed at an early stage and the final image can be obtained while the resolution is sequentially increased, which is suitable for interactive image communication and image database search. One of them is the sequential reproduction coding method (Japanese Patent Laid-Open No. 60-127875).

 The sequential reproduction coding method performs coding in the following procedure.

(1) Run by connecting every ΔX = 2 ⁿ (n = integer) pixels in the horizontal (main scanning) direction and ΔY = 2 ⁿ (n = integer) lines in the vertical (sub-scanning) direction. Performs length coding.

(2) Next, the pixel located at the center surrounded by a rectangle with the four adjacent coded pixels is set to five states according to the number of black pixels of the reference pixels with these four pixels as reference pixels. The pixels are classified, and pixels corresponding to each state are connected to perform run-length coding.

(3) Next, the pixel located at the center surrounded by the rhombus with the four adjacent coded pixels is set to five states according to the number of black pixels of the reference pixels with these four pixels as reference pixels. The pixels are classified, and pixels corresponding to each state are connected to perform run-length coding.

(4) The encoding of (2) and (3) is repeated until all the pixels are encoded.

FIG. 5 is a diagram showing the concept of the encoding order in the sequential reproduction encoding method in the case of ΔX = ΔY = 4. First, the pixels marked with ⊚ are encoded ((1) above).

Next, the circled pixels are coded according to the state (the number of black pixels) of the reference pixels, using the four nearest neighbors that surround the circled pixels among the already coded circled pixels as reference pixels. ((2) above). Next, regarding the pixels marked with Δ, among the already coded pixels marked with ◎ and ○, the four nearest neighbors surrounding the pixels marked with triangles in a diamond shape are used as reference pixels, and the state of the reference pixels (the number of black pixels ) Separate encoding ((3) above). Then ×
The pixel of the mark is the reference pixel which is the four nearest neighbors surrounding the rectangle of the pixel of the mark ∘ among the pixels of the mark ∘, ○ and Δ already encoded, and the state of the reference pixel (the number of black pixels) Encode separately. ((2) above). Finally, the pixel of the mark is, among the already coded pixels of the ◎ mark, the O mark, the Δ mark, and the X mark, the four nearest pixels that surround the pixel of the mark in a diamond shape are used as reference pixels,
Encoding is performed for each state of reference pixels (the number of black pixels). ((3) above).

The above is the case of ΔX = ΔY = 4, but other ΔX and ΔY
The same applies to. When ΔX ≠ ΔY, the distance in one direction is fixed when the reference pixel interval in one direction becomes 2, and the processes in (2) and (3) are performed until the reference pixel distance becomes 2 only in the other direction. I do.

Further, in the decoding in the sequential reproduction coding method, the decoding is performed for each reference pixel state (the number of black pixels) according to the same procedure as (1), (2), and (3) of the coding.

Problems to be Solved by the Invention There is a hierarchical coding method in which coding is performed for each state of reference pixels for the purpose of improving the data compression rate. For example, in the above-described sequential reproduction coding method, coding is performed for each state by dividing into five states according to the number of black pixels of four reference pixels. FIG. 4 shows a hierarchical structure in the case where one state is one layer in the sequential reproduction coding system. This is the case where ΔX and ΔY in the first layer (level 1) are 8, and the state i in the figure means a state in which there are i black pixels among the four reference pixels.

The encoding system having such a hierarchical structure has the following problems. That is, when the processing is performed for each state of reference pixels as in the sequential reproduction encoding method described above, the same encoding / decoding pixel and reference pixel are accessed in duplicate in each state. However, there is a problem in that the access to the reference pixels is wasteful. Taking the sequential reproduction coding method as an example, the second layer to the sixth layer in FIG. 4 all use the same code / decode pixel and reference pixel (square with ΔX = ΔY = 8), and the same code /
Decoded pixels and reference pixels are accessed redundantly in each layer. The same applies to 7th to 11th layers, 12th to 16th layers, and
It also occurs in each of the 17th to 21st layers, the 22nd to 26th layers, and the 27th to 28th layers. For this reason, overhead occurs in accessing the coded / decoded pixel and the reference pixel, resulting in a decrease in the overall processing speed.

The present invention has been made in view of the above points, and an object thereof is to reduce the number of times of access to a pixel to be coded and a reference pixel in a coding process.

Means for Solving the Problems In order to achieve the above object, the present invention relates to a known reference pixel obtained by taking a pixel sampled from among the pixels at a specific position with respect to the sampled pixel. An apparatus for performing a hierarchical encoding process in which the reference pixels are classified according to states and the pixels belonging to each state are encoded, and the image data to be encoded is stored and the reference pixels are sampled at a predetermined sampling. And a storage unit that outputs a pixel to be encoded, a plurality of encoding units that are provided for each state of the reference pixel and that encodes the pixel to be encoded, and the state based on whether the reference pixel is black or white. A discriminating unit for discriminating, and a code for selecting one encoding unit from the plurality of encoding upper parts based on the discrimination result of the discriminating unit and inputting a pixel to be encoded to the selected encoding unit. An encoding unit selecting unit, and by collectively performing the processing of the encoding target pixels in one or more states of the reference pixel, the encoding target pixel and the reference pixel can be accessed in each state. In the encoding / decoding process for the hierarchical pixels to be shared, the process is performed at high speed.

Effect With the above-described configuration, the present invention makes it possible to share access to the encoding target pixel and the reference pixel in each state for processing in a plurality of states having the same reference pixel.

First Embodiment FIG. 1 is a block diagram showing an encoding apparatus according to an embodiment of the present invention, and a circuit for performing a decoding process is also shown for the sake of detailed description. The apparatus shown in the figure is configured for the sequential reproduction coding system, which is one of the hierarchical coding systems described above.

In the apparatus shown in FIG. 1, a memory device capable of accessing pixels sampled in the main scanning direction as one pixel memory (for example, those disclosed in JP-A-60-3039 and JP-A-60-81661). ) Is used. FIG. 2 is a diagram for explaining pixel access in such a memory device. The figure (a) shows the case of memory read, and as shown in the figure, the contents of the image memory are reduced and read. FIG. 7B shows a case of memory write, and data is diffused and written in the image memory as shown in the figure. At this time, the original value is stored without writing the data in the position of the X mark of the image memory.

By using such a memory device for the image memory 1, the sampling interval Δ in the sequential reproduction encoding method is increased.
It is possible to process only the pixels corresponding to X. The operation of the apparatus shown in FIG. 1 will be described below.

First, the operation of the apparatus of FIG. 1 at the time of encoding will be described. A coded pixel and a reference pixel corresponding to the coded pixel are read from the image memory 1 and set in the coded pixel shift register 3 and the reference pixel shift register 2, respectively. When data is set in each shift register, the timing control unit 28 starts shifting of each shift register. The coded pixels output from the coded pixel shift register 3 are sent to the coding units in each of states 8 to 12. on the other hand,
The reference pixel output from the reference pixel shift register 2 is 5
The reference pixel state determining unit determines the state of the reference pixel, that is, the number of black pixels among the four reference pixels, and outputs a code indicating the state of the reference pixel to the demultiplexer 6. The demultiplexer 6 selects an encoding unit according to the state according to the code indicating the state from the reference pixel state determination unit 5 and sets the timing control unit 28 to the corresponding encoding unit.
To output the encoded pixel capture clock from. For example, when the coded pixel output from the coded pixel shift register 3 is in the state 0, the coded pixel is fetched only in the state 0 coding section 8 under the control of the demultiplexer 6 and is coded. These processes are sequentially performed in bit units of encoded pixels. The demultiplexer 6 selects the coding units 8 to 12 according to the state of each bit of the coded pixel and inputs the coded pixel. In this way, the code data independently generated in the coding units 8 to 12 in each state are 23 to 23, respectively.
It is stored in the code buffer corresponding to each state of 27. When the processing is completed up to the lower right of the screen, a hierarchical coding system is constructed based on the code data accumulated in the code buffers 23 to 27 in each state.

By the processing described above, it is possible to perform coding in all states with one access to the coded pixel and the reference pixel for the five states (state 0 to state 4) in which the reference pixels are the same.

Next, the decoding operation of the apparatus shown in FIG. 1 will be described.

First, the case of decoding all five states in the same reference pixel will be described. The code data in each state is stored in the code buffers 23-27. The decoding units 13 to 17 in each state independently read the code data from the code buffer in the corresponding state and perform decoding, and output the decoded pixels in each state to the buffers 18 to 22 and store them.
In parallel with this, reference pixels are read from the pixel memory 1 and set in the reference pixel shift register 2. When the reference pixel is set in the shift register 2, the timing control unit 28 causes the reference pixel shift register 2, the decoding pixel shift register 4, and the mask pattern shift register 30.
To start the shift. Similar to the case of encoding, the reference pixel output from the reference pixel shift register 2 has its state determined by the reference pixel state determination unit 5, and outputs a code indicating the state. The code indicating the state is output to the multiplexer 7 and the gate 29. The multiplexer 7 selects the buffer corresponding to the state of the reference pixel according to the code indicating the state from the reference pixel state determination unit 5, and outputs the content of the buffer to the decoding pixel shift register 4. For example, if the reference pixel is in state 0, the decoded pixel of the buffer 18 is output to the decoded pixel shift register 4. The buffer 18
22 to 22 are composed of a FIFO (fast-in / fast-out memory) or the like, and when the contents are shifted out by 1 bit, the next bit appears in the output.

Similar to the encoding, these processes are sequentially performed on a bit-by-bit basis of the decoded pixel, and the multiplexer 7 selects the buffers 18 to 22 according to the state of the reference pixel to read the decoded pixel and decode the decoded pixel shift register. Output to 4. When a predetermined amount of decoded pixels are accumulated in the decoding shift register 4, the contents of the decoding pixel shift register 4 are written in the image memory 1. At this time, the image memory 1
Only the necessary bits are written in and the unnecessary bits are masked. The mask pattern shift register 30 generates a mask pattern for controlling the mask in bit units. The mask pattern shift register 30 controls the mask / non-mask in bit units by activating the write enable signal only in the memory chip corresponding to the bit to be written in the image memory 1. This is a control that is performed because, for example, when decoding only one of the five states, the bits of the other four states need to be masked when writing to the image memory. In this case, since all five states are being decoded, the contents of the decoded image shift register 4 are all written to the image memory 1, so all the bits of the mask pattern shift register 30 indicate active. Therefore, the gate 29 always outputs an active signal to the mask pattern shift register 30. The gate 29 is controlled by the state control signal 31. The state control signal 31 gives the gate 29 which state to decode, and in this case, gates the code indicating that all five states will be decoded.
Giving to 29.

If the processing to the lower right of the screen is performed in this way, it means that decoding of five states (state 0 to state 4) in which the reference pixels are the same is performed by one-time decoding pixel and reference pixel access. .

Next, a case where only some of the five states of the same reference pixel are decoded will be described. Since it is basically the same as the case of decoding all five states described above, only different points will be described.

The timing control unit 28 operates only the decoding units 13 to 17 corresponding to the decoding state according to the state control signal 31, and accumulates the decoded pixels in the buffers 18 to 22. The multiplexer 7 selects the buffer corresponding to the state by the code indicating the state from the reference pixel state determination unit 5, and outputs the content of the buffer to the decoding pixel shift register 4. At this time, there is no decoded pixel other than the decoded state in the buffer, so it is don't care and has an indefinite value.

The mask pattern shift register 30 is a mask pattern for masking bits other than the decoding state when writing the contents of the decoded pixel shift register 4 to the pixel memory 1, that is, the above-mentioned don't care and undefined value pixels. To generate. FIG. 3 is a diagram showing this, and is a case where the states 0 and 1 are decoded when the reference pixel is in the rectangular position and ΔX = ΔY = 2. FIG. 11A shows the position of the decoded pixel in the image memory and the reference pixel. As shown in the figure, the state at each decoding position is given by the number of black pixels of the corresponding reference pixels. 2B and 2C show the contents of the decoding shift register 4 and the mask pattern shift register 30 in FIG. 1, respectively. By the access sampled as described with reference to FIG. 2, the bits of the decoding pixel shift register 4 and the mask pattern shift register 30 are set with the data corresponding to the bit-by-bit sampling of the image memory 1. By the way, in this case, since only the states 0 and 1 are decoded, the bits of the states 2, 3 and 4 of the decoding register of (b) are don't care (undefined value), so that of (c) Also in the mask pattern shift register, the corresponding bit position is non-active. Therefore, when writing the contents of the decoded pixel shift register 4 to the image memory 1, only the pixels in the states 0 and 1 are written to the image memory under the control of the mask pattern shift register 30.

The input to the mask pattern shift register 30 of FIG. 1 is controlled by the gate 29. The gate 29 compares the state control signal 31 indicating the state of decoding with the code indicating the state of the reference pixel output from the reference pixel state determination unit 5, and if the state of the reference pixel matches the state of decoding. If the signals are active and do not match, a non-active signal is output to the mask pattern shift register 30. In this way, the mask pattern shift register 30 generates a mask pattern in which only the bit positions to be written in the image memory 1 are active.

While the operation of the apparatus of FIG. 1 at the time of encoding and decoding has been described above, the processing of the first layer in FIG. 4 will be described as a special case. In the sequential reproduction coding method, reference pixels do not exist only in the processing of the first layer. In the first layer, the sampling pixels defined by ΔX and ΔY are concatenated as they are for encoding / decoding. In order to deal with the processing of the first layer in the apparatus shown in FIG. 1, the output of the reference pixel state determination unit 5 is forcibly fixed to a certain state, and the gate 29
The output of should always be active. For example, if the output of the reference pixel state determination unit 5 is fixed to the state 0, all the encoded pixels are encoded by the state 0 encoding unit 8 and stored in the code buffer 23 during encoding. At the time of decoding, all the code data of the state 0 code data is decoded by the state 0 decoding unit 13, and the decoded pixels are sent to the decoded pixel shift register 4 via the buffer 18. All the contents of the decoded pixel shift register 4 are valid, while the contents of the mask pattern shift register 30 are all active under the control of the gate 29. Therefore, all the contents of the decoded pixel shift register 4 can be written in the image memory 1. it can. In this way, the processing of the first layer of the sequential reproduction coding method can be performed.

Further, for example, if the processes from the second layer to the sixth layer are performed sequentially, the access of the encoding / decoding pixel and the reference pixel is performed in each layer, and the same encoding / decoding pixel and the reference pixel are accessed five times in total. Will be accessed. If this is performed by the batch processing of a plurality of states according to the present invention, the access of the code / decode pixel and the reference pixel is performed only once, and the number of access times of the code / decode pixel and the reference pixel is eventually increased.
That's 1/5. This greatly contributes to the improvement of processing speed.

Finally, the operation of the coding units 8-12 and the decoding units 13-17 in each state in FIG. 1 will be described. In the present invention, the coding units 8-12 and the decoding units 13-17 for each state are
Can be operated in time division or in parallel. For example, at the time of encoding, in the case of time division operation, while the encoding unit in one state is operating, the encoding units in the other states are stopped, whereas when operating in parallel, The encoder can operate simultaneously. Therefore, unless one state is continuous, the processing of the encoding unit is faster in parallel operation. If the processing speed of the coding units 8 to 12 is slow, the coded pixels output from the coded pixel shift register 3 cannot be processed, and the shift operation of the coded pixel shift register 3 needs to be temporarily stopped. This means that the processing speed of coded pixels is reduced. In this respect, the processing of the coding units 8 to 12 is preferably high speed, and the parallel processing of the processing of the coding units 8 to 12 is advantageous in terms of processing speed, except when the same state continues. The same applies to decoding, and it is advantageous in terms of processing speed that the decoding units 13 to 17 operate in parallel.

EFFECTS OF THE INVENTION As described above, according to the present invention, it is possible to collectively perform coding processing for all layers having common reference pixels in the hierarchical coding method. Therefore, it is possible to perform the processing for all layers in which the access reference pixel of the encoding target pixel and the reference pixel is common once. Therefore, it can be processed at extremely high speed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an encoding device according to an embodiment of the present invention, FIG. 2 is a diagram explaining sampled access to an image memory, and FIG. 3 is a mask pattern at the time of decoding. FIG. 4 is a diagram for explaining a mask pattern of a shift register, FIG. 4 is a diagram showing one row of a hierarchical structure in a sequential reproduction coding system, and FIG.
The figure is a diagram showing the concept of the encoding order in the sequential reproduction encoding method. 1 ... Image memory, 2 ... Reference pixel shift register, 3
...... Encoding pixel shift register, 4 Decoding pixel shift register, 5 Reference pixel state determination unit, 6 Demultiplexer, 7 Multiplexer, 8 to 12 Encoding unit, 13 to 17 … Decoding unit, 18-22 …… Buffer, 23-27
...... Code buffer, 28 ...... Timing control unit, 29 ......
Gate, 30 ... Mask pattern shift register

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Endo 2-23 Nakameguro, Meguro-ku, Tokyo Inside the International Telegraph and Telephone Corporation (72) Inventor Hisaharu Kato 2-1, Nakameguro, Meguro-ku, Tokyo No. 23 International Research Institute of Telegraph and Telephone Corporation (72) Inventor Hiroshi Kusao 1006 Kadoma, Kadoma City Matsushita Electric Industrial Co., Ltd. (72) Inventor Akira Hirasawa 1006 Kadoma, Kadoma City Matsushita Electric Industrial Co., Ltd. 72) Inventor Neiichi Nishino 1006 Kadoma, Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Hiroshi Miki 2-3-3 Shimeguro, Meguro-ku, Tokyo Matsushita Electric Transport Co., Ltd. (72) Inventor Asaba Shoji 2-3-8 Shimo-Meguro, Meguro-ku, Tokyo Matsushita Electric Transport Co., Ltd.

Claims (1)

(57) [Claims] 1. A pixel sampled from an image is classified according to a state of the reference pixel based on a state of a known reference pixel taken from the image at a specific position with respect to the sampled pixel, In a device that performs hierarchical encoding processing that performs encoding for each pixel belonging to each state,
A storage unit that stores image data to be encoded and outputs a reference pixel and an encoding target pixel by predetermined sampling; and a plurality of units provided for each state of the reference pixel and encoding the encoding target pixel Coding unit, a discrimination unit that discriminates the state by the black-white discrimination of the reference pixel, and one coding unit is selected from the plurality of coding units based on the discrimination result of the discrimination unit, and the selection is performed. An encoding unit selecting unit for inputting an encoding target pixel to the encoded unit, and the encoding is performed by collectively processing the encoding target pixels in one or more states of the reference pixels. An encoding device, characterized in that access to a target pixel and the reference pixel is shared by processing in each state.