JP2532422B2 - Encoder - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an encoding device in a device that handles image data such as a facsimile machine.

2. Description of the Related Art The MR coding method finds the position of a pixel change point (a point that changes from white to black or vice versa) on each of a coding line and a reference line, and performs coding according to the relative position. In the device that performs this encoding method, when detecting the position of the change point from the pixel accessed in block units, the encoding line and the reference line can be independently performed, and one block of pixels is read out in each line. The presence or absence of a pixel change point is detected for each (for example, Japanese Patent Laid-Open No. 61-82578).

On the other hand, with the diversification of facsimile communication, it has been considered to use a facsimile terminal in combination with a display terminal in order to perform interactive image communication and search of an image database. In contrast to the conventional encoding method such as MR method which sequentially encodes from the top to the bottom of the image according to the scanning line, as a coding method suitable for such interactive image communication, a sequential reproduction encoding method (for example, JP 60-1278
A method for performing hierarchical encoding processing, such as Japanese Patent No. 75), has been proposed.

 The sequential reproduction coding method performs coding in the following procedure.

(1) The pixels extracted for each ΔX = 2 ⁿ (n = integer) pixel in the horizontal (main scanning) direction and for each ΔY = 2 ⁿ (n = integer) line in the vertical (sub-scanning) direction n are connected. Performs run length encoding.

(2) Next, the pixel located at the center surrounded by a rectangle with the four adjacent coded pixels is set to five states according to the number of black pixels of the reference pixels with these four pixels as reference pixels. The pixels are classified, and pixels corresponding to each state are connected to perform run-length coding.

(3) Next, the pixel located at the center surrounded by the four adjacent coded pixels surrounded by the rhombus is set to 5 states according to the number of black pixels of the reference pixels with these 4 pixels as reference pixels. The pixels are classified, and pixels corresponding to each state are connected to perform run-length coding.

(4) The encoding of (2) and (3) is repeated until all the pixels are encoded.

FIG. 8 is a diagram showing the concept of the encoding order in the sequential reproduction encoding method in the case of ΔX = ΔY = 4. First, the pixels marked with ⊚ are encoded. Next, the pixels marked with a circle are roughly coded pixels marked with a circle, and the four nearest pixels surrounding the circled circle are used as reference pixels, and the pixels are coded according to the number of black pixels of the reference pixels. Next, the Δ-marked pixels are roughly coded ◎ -marked and ◯ -marked pixels, and the four nearest neighbors surrounding the Δ-marked pixels in a rhombus are used as reference pixels, and are coded according to the number of black pixels of the reference pixels. Turn into. Next, the pixels marked with X are roughly coded pixels marked with ◎, ○, and Δ, and the four nearest neighbors surrounding the pixel marked with X are used as reference pixels. Encode by number. Finally, the pixels marked with-are coded according to the number of black pixels of the reference pixels, with the already coded four being the reference pixels.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the sequential reproduction coding method described above, coded pixels are classified according to the number of black pixels of reference pixels extending over a plurality of lines, and the classified pixels are connected to change the pixel. The points are detected and run length coded. In encoding, when detecting a pixel change point from a pixel accessed in block units, the pixel change point is detected every time one block of pixels is read in each line, as in the case of the MR encoding described above. It cannot be detected. Therefore, after the necessary encoded pixels and reference pixels are sequentially read out in block units, pixels that match the number of black pixels of the reference pixels that are currently being processed are extracted, and their change points are detected. In decoding, necessary reference pixels are sequentially read in block units, and then the pixels are reproduced at positions that match the number of black pixels of the reference pixels currently being processed.

When the detection of the pixels matching the number of black pixels of the reference pixels and the detection of the change point of the pixels are sequentially performed from the pixel of the block unit in the bit unit, the next block is processed until all the pixels in the block are processed. The pixels are not read out, and the processing speed decreases. On the other hand, if the change point of the pixel is detected in parallel, the number of pixels to be handled is large, and the circuit scale becomes large.

The present invention has been made in view of the above points, and provides an encoding device that efficiently detects a pixel position that matches a reference pixel, detects a change point of the pixel, or reproduces the pixel with a simple configuration. The purpose is to

Means for Solving the Problems In order to achieve the above object, the present invention provides a reference pixel register group for setting reference pixel data in block units,
A coded pixel register for setting coded pixel data in block units, shift control means for outputting a load signal for loading data of the reference pixel register group and the coded pixel register, and the load signal Reference pixel shift register group for respectively loading and shifting the data of the reference pixel register group according to the above, and for the encoding pixel for loading and shifting the data of the encoding pixel register according to the load signal A shift register; and a microprocessor that activates the shift control means to perform the data set of each register and the shift operation of each shift register, wherein the shift control means stores predetermined data in each shift register. When the shift is completed, the shift operation of each shift register is stopped until the next activation. Performs control to, in which to perform in parallel a shift operation of the microprocessor access to the respective shift register to the reference pixel register group and encoded pixel register.

With the above-described configuration, the present invention allows the control device to sequentially access the buffer registers and the shift register to shift the data of one block in parallel, and further to shift the data of one block in the shift register. Since the data shift process is completed while the control device is accessing the register for the buffer, the control device can operate without detecting the completion of the shift process. The processing speed of the detection and the change point of the pixel or the reproduction of the pixel is improved.

Embodiment Hereinafter, the case of the sequential reproduction coding system shown in FIG. 8 will be described as an example. FIG. 1 is a block diagram showing an embodiment of a coding / decoding device of the present invention. In the figure, 1 is a microprocessor (MPU), 2 is an image memory for storing image data, 3 is a code memory for storing encoded data, 4 is a register for encoding pixels, and 5 to 7 are for reference pixels. A register, 9 is a shift register for a coded pixel that loads the data of the register 4 and bit shifts, 10 to 12 is a shift register for a reference pixel that loads the data of the registers 5 to 7 and bit shifts, and 13 is a A shift register for decoding pixels for bit-shifting and reproducing data, 8 a register for decoding pixels for loading data in the shift register 13, 14 a shift registers 9-12 and shift data in registers 4-7, respectively. LOAD signal for transferring data of register 13 to register 8 and shift register 9
Shift control circuit for generating SHIFT-CLOCK signal which is a shift clock of ~ 13, 15 is a state detection circuit for checking the number of black pixels of reference pixels, 16 is extraction and reproduction of pixels matching the state of reference pixels and reference pixels SHIFT-C where the condition of
An extraction circuit that generates a COUNT-CLOCK signal that is a clock that extracts the LOCK signal and counts the run length, 17 is a change point detection circuit that detects changes in the pixels extracted by the extraction circuit 16, and 18 is a counter that counts the run length Is.

Hereinafter, the number of bits of the registers 4 to 8 and the shift registers 9 to 13 is 8 bits, and the image memory 2 has 1/2 ^m (m =
A memory device in which 8-bit data reduced to an integer (sampling every 2 ^m bits) can be accessed once (for example, Japanese Patent Laid-Open Nos. 60-3039 and 60-81661).
Will be described as using.

First, the case of encoding the pixels marked with ⊚ will be described.
FIG. 2 is a timing chart at the time of this encoding. (A) shows the case where the change point detection circuit 16 does not detect a pixel change, (b) shows
Is a diagram when it is detected.

(1) The MPU 1 performs sampling access every 4 bits, reads 8 bits only from the pixel memory 2 for the coded pixel (pixel marked with ⊚), and sets it in the register 4 (data set to the register 4).

(2) Set data in the shift control circuit 14 and start it (start of shift control circuit). The operation of is repeated.

When the data is set, the shift control circuit 14 outputs the LOAD signal and then outputs the SHIFT-CLOCK signal for only 8 clocks. The shift register 9 loads the data in the register 4 with the LOAD signal and shifts the data with the SHIFT-CLOCK signal. Since there is no reference pixel in the encoding here, the extraction circuit 16 extracts all the pixels and outputs them to the change point detection circuit 17,
All SHIFT-CLOCK signals are extracted to create a COUNT-CLOCK signal and output to the counter 18. Counter 18 is this COUNT
-Count the CLOCK signal. Furthermore, the shift register 9
Is configured so that the time required to load the data in the register 4 and shift it by 8 bits is shorter than the time required for the MPU 1 to perform the processes of (1) and (2).

When the change point detection circuit 17 does not detect a pixel change, the MPU 1 repeats the processes (1) and (2) as shown in FIG.

When the change point detection circuit 17 detects a change in the pixel, the operation shown in FIG. 2 (b) is performed. The change point detection circuit 17 generates an INT1 signal which is an interrupt signal. Shift control circuit 14
When receiving this signal, will stop sending the SHIFT-CLOCK signal. When the MPU1 receives the INT1 signal, it suspends the process (1) or (2) that is currently being performed, i) reads the data (run length) of the counter 18, and ii) creates a code from this data and creates the code memory 3 Stored in (create code from run length),
iii) The operation (interrupt processing) of setting data in the shift control circuit 14 and starting it (start of the shift control circuit) is performed. After performing this interrupt processing, the interrupted processing is restarted. When the data is set, the shift control circuit 14 sends the SHIFT-CLOCK signal for the remaining clocks (8 clocks minus the clock sent before the stop). Although FIG. 2B shows the case where the pixel change is detected only once during the 8-bit shift in the shift register, the same is true when the pixel change is detected twice or more.

Next, the case where the pixels marked with a circle are encoded will be described.
FIG. 3 is a timing chart at the time of this encoding. (A) shows a case where the change point detection circuit 16 does not detect a pixel change, (b) shows
Is a diagram when it is detected.

The MPU 1 (1) performs access by sampling every 4 bits, reads only 8 bits of the coded pixel (pixel marked with a circle) from the pixel memory 2, and sets it in the register 4 (data set to the register 4).

(2) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with ⊚) on two lines are read from the pixel memory 2 by 8 bits and set in the register 5 (data set to the register 5). .

(3) Access is performed by sampling every 4 bits, and 8 bits are read from the pixel memory 2 only for reference pixels (pixels marked with ⊚) 2 lines below the encoded pixel and set in the register 6 (data set in the register 6). .

(4) Set data in the shift control circuit 14 and start it (start of shift control circuit). The operation of is repeated.

When the data is set, the shift control circuit 14 outputs the LOAD signal and then outputs the SHIFT-CLOCK signal for only 8 clocks. The shift registers 9 to 11 load the data in the registers 4 to 6 with the LOAD signal and shift the data with the SHIFT-CLOCK signal. The state detection circuit 15 includes shift registers 10 and 11
The number of black pixels of the pixels from is output to the extraction circuit 16, and the extraction circuit 16 detects the change point by extracting the pixels from the shift register 4 that match the currently encoded state (the number of black pixels of the reference pixels). Output to circuit 17, SHIF where pixel is extracted
Only the T-CLOCK signal is extracted to create the COUNT-CLOCK signal and output it to the counter 18. Counter 18 is this COUNT-CLOCK
Count the signals. Further, the time required for the shift registers 9 to 11 to load the data in the registers 4 to 6 and shift the data by 8 bits is configured so that the time required for the MPU 1 to perform the processing of (1) to (4) is shorter. .

When the change point detection circuit 17 does not detect a pixel change, the MPU 1 repeats the processes (1) to (4) as shown in FIG.

When the change point detection circuit 17 detects a pixel change,
The operation shown in FIG. 3B is performed in the same manner as described in the case of encoding the pixel of the mark.

Next, the case of encoding the pixels marked with Δ will be described.
FIG. 4 is a timing chart at the time of this encoding. (A) shows a case where the change point detection circuit 16 does not detect a pixel change, (b) shows
Is a diagram when it is detected.

The MPU 1 (1) performs access by sampling every 4 bits, reads only 8 bits from the pixel memory 2 for the encoded pixels (pixels marked with Δ), and sets them in the register 4 (data set to the register 4).

(2) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with ◯) on 2 lines are read out from the pixel memory 2 by 8 bits and set in the register 5 (data set to the register 5). .

(3) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with a circle) 2 lines below the encoded pixel are read out from the pixel memory 2 for 8 bits and set in the register 6 (data set to the register 6). .

(4) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with ⊚) in the same line as the encoded pixels are read out from the pixel memory 2 by 8 bits and set in the register 6 (data set to the register 7).

(5) Data is set in the shift control circuit 14 to start (shift control circuit start). The operation of is repeated.

When the data is set, the shift control circuit 14 outputs the LOAD signal and then outputs the SHIFT-CLOCK signal for only 8 clocks. The shift registers 9 to 12 load the data in the registers 4 to 7 with the LOAD signal and shift the data with the SHIFT-CLOCK signal. The state detection circuit 15 is a shift register 10-12.
The number of black pixels of the pixels from is output to the extraction circuit 16, and the extraction circuit 16 extracts the pixels from the shift register 4 that match the currently encoded state (the number of black pixels of the reference pixels) to detect the change point. Output to circuit 17, SHIF where pixel is extracted
Only the T-CLOCK signal is extracted to create the COUNT-CLOCK signal and output it to the counter 18. Counter 18 is this COUNT-CLOCK
Count the signals. Further, the time required for the shift registers 9 to 12 to load the data in the registers 4 to 7 and shift the data by 8 bits is configured so that the time required for the MPU 1 to perform the processing of (1) to (5) is shorter. .

When no pixel change is detected by the change point detection circuit 17, the MPU 1 repeats the processes (1) to (5) as shown in FIG. 4 (a).

When the change point detection circuit 17 detects a pixel change,
The operation shown in FIG. 4B is performed in the same manner as described in the case of encoding the pixel of the mark.

Below, the coded pixels marked with X are similar to the coding when the sampling interval for coding the pixels marked with ○ is halved, and the coded pixels marked with are half the sampling intervals for coding the pixels marked with Δ. This is the same as the encoding in the case of.

Described below is the case of decoding the pixels marked with ⊚. FIG. 5 is a timing diagram at the time of this decoding. (A) shows the counter 18
Is a diagram when the carry-down signal is not output, and (b) is a diagram when it is output.

The MPU 1 (1) reads the register 8 and performs access by sampling this data every 4 bits and writes it to the pixel memory 2 (reading of the register 8).

(2) Set data in the shift control circuit 14 and start it (start of shift control circuit). The operation of is repeated.

When the data is set, the shift control circuit 14 outputs the LOAD signal and then outputs the SHIFT-CLOCK signal for only 8 clocks. The register 8 loads the data of the shift register 13 with the LOAD signal. Since there is no reference pixel in the encoding here, the extraction circuit 16 uses the color of the pixel currently being decoded (white / white /
(Black) is output to the shift register 13 and all SHIFT-CLOCK signals are extracted to create a COUNT-CLOCK signal and output to the counter 18. The shift register 9 shifts in the data from the extraction circuit 16 with the SHIFT-CLOCK signal. The counter 18 counts down the set run length with this COUNT-CLOCK signal. Further, the time required for the register 8 to load the data in the shift register 13 and then shift the data by 8 bits in the shift register 13 should be shorter than the time required for the MPU 1 to perform the processes (1) and (2) above. To configure.

When the counter 18 does not output the carry-down signal, the MPU 1 repeats the processes (1) and (2) as shown in FIG.

When the counter 18 outputs the carry-down signal, the operation shown in FIG. 5 (b) is performed. When the counter 18 counts down by the set run length, it generates an INT2 signal as an interrupt signal as a carry-down signal. When the shift control circuit 14 receives this signal, it stops sending the SHIFT-CLOCK signal. When the MPU1 receives the INT2 signal, it interrupts the process (1) or (2) that is currently being performed, and i) reads the code data stored in the code memory 3 and creates a run length from this data (code (Run length creation), ii) data (run length) is set in the counter 18, iii) data is set in the shift control circuit 14 to start (shift control circuit start), and the operation (interrupt processing) is performed. . After performing this interrupt processing, the interrupted processing is restarted. When the data is set, the shift control circuit 14 sends the SHIFT-CLOCK signal for the remaining clocks (8 clocks minus the clock sent before the stop).
FIG. 5 (b) shows the case where the shift register detects a pixel change only once during 8-bit shift.
The same applies when detected more than once.

Next, the case of decoding the pixels marked with a circle will be described.
FIG. 6 is a timing diagram at the time of this decoding. FIG. 6A is a diagram when the carry-down signal is not output from the counter 18, and FIG. 6B is a diagram when it is output.

The MPU 1 (1) reads the register 8 and performs access by sampling this data in units of 4 bits and writes the logical sum with the data stored in the pixel memory 2 (reading of the register 8). In order to take the logical sum with the data stored here, only the pixel where the state matches is rewritten.

(2) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with ⊚) on 2 lines are read out from the pixel memory 2 by 8 bits and set in the register 5 (data set to the register 5). .

(3) Access is performed by sampling every 4 bits, and 8 bits are read from the pixel memory 2 only for reference pixels (pixels marked with ⊚) 2 lines below the decoded pixel and set in the register 6 (data set to the register 6). .

(4) Set data in the shift control circuit 14 and start it (start of shift control circuit). The operation of is repeated.

When the data is set, the shift control circuit 14 outputs the LOAD signal and then outputs the SHIFT-CLOCK signal for only 8 clocks. The register 8 loads the data of the shift register 13 with the LOAD signal, the shift registers 10 and 11 load the data of the registers 5 to 6 with the LOAD signal, and shifts the data with the SHIFT-CLOCK signal, and the shift register 9 shifts the SHIFT- CLOCK
The data from the extraction circuit 16 is shift-input by a signal. The state detection circuit 15 outputs the number of black pixels of the pixels from the shift registers 10 and 11 to the extraction circuit 16, and the extraction circuit 16 is currently in the place where it matches the state (the number of black pixels of reference pixels) currently being decoded. Decoded pixel color is "L" if it does not match
The level pixel is reproduced and output to the shift register 13, and only the SHIFT-CLOCK signal where the color of the currently decoded pixel is reproduced is extracted to create the COUNT-CLOCK signal and output to the counter 18. Counter 18 shows the set run length
Count down with the COUNT-CLOCK signal. Further, the shift registers 10 and 11 load the data of the registers 5 and 6 and
The time required for bit shifting and the shift register 13 after the register 8 has loaded the data in the shift register 13
The time required to shift data by 8 bits in MPU1
Is shorter than the time required for the above processes (1) to (4).

When the counter 18 does not output the carry-down signal, the MPU 1 repeats the processes (1) to (4) as shown in FIG. 6 (a).

When the counter 18 outputs the carry-down signal, the operation shown in FIG. 6 (b) is performed in the same manner as in the case of decoding the pixel marked with ⊚.

Next, the case of decoding the pixels marked with Δ will be described.
FIG. 7 is a timing diagram at the time of this decoding. FIG. 7A is a diagram when the carry-down signal is not output from the counter 18, and FIG. 7B is a diagram when it is output.

The MPU 1 (1) reads the register 8 and performs access by sampling this data in units of 4 bits and writes the logical sum with the data stored in the pixel memory 2 (reading of the register 8). The reason for taking the logical sum with the data stored here is to rewrite only the pixel where the state matches.

(2) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with ◯) on 2 lines are read out from the pixel memory 2 by 8 bits and set in the register 5 (data set to the register 5). .

(3) Access is performed by sampling every 4 bits, and only the reference pixels (pixels marked with a circle) 2 lines below the decoded pixel are read from the pixel memory 2 for 8 bits and set in the register 6 (data set to the register 6). .

(4) Access is performed by sampling every 4 bits, and 8 bits are read from the pixel memory 2 only for reference pixels (pixels marked with ⊚) on the same line as the decoded pixel and set in the register 6 (data set to the register 7).

(5) Data is set in the shift control circuit 14 to start (shift control circuit start). The operation of is repeated.

When the data is set, the shift control circuit 14 outputs the LOAD signal and then outputs the SHIFT-CLOCK signal for only 8 clocks. The register 8 loads the data of the shift register 13 with the LOAD signal, the shift registers 10 to 12 load the data of the registers 5 to 7 with the LOAD signal and shifts the data with the SHIFT-CLOCK signal, and the shift register 9 shifts the SHIFT- CLOCK
The data from the extraction circuit 16 is shift-input by a signal. The state detection circuit 15 outputs the number of black pixels of the pixels from the shift registers 10 to 12 to the extraction circuit 16, and the extraction circuit 16 is currently in the place where it matches the state (the number of black pixels of reference pixels) currently being decoded. Decoded pixel color is "L" if it does not match
The level pixel is reproduced and output to the shift register 13, and only the SHIFT-CLOCK signal where the color of the currently decoded pixel is reproduced is extracted to create the COUNT-CLOCK signal and output to the counter 18. Counter 18 shows the set run length
Count down with the COUNT-CLOCK signal. Further, the shift registers 10 to 12 load the data of the registers 5 to 8 and
The time required for bit shifting and the shift register 13 after the register 8 has loaded the data in the shift register 13
The time required to shift data by 8 bits in MPU1
Is shorter than the time required for the above processes (1) to (5).

When the counter 18 does not output the carry-down signal, the MPU 1 repeats the processes (1) to (5) as shown in FIG.

When the counter 18 outputs the carry-down signal, the operation shown in FIG. 7 (b) is performed in the same manner as in the case of decoding the pixel marked with ⊚.

Below, the decoding pixels marked with X are the same as the decoding when the sampling interval for decoding the pixels marked with ○ is halved, and the coded pixels marked with are half the sampling intervals for decoding the pixels marked with Δ. This is the same as the decoding in the case of.

The case of the sequential playback coding method has been described as an example, but MR
It can also be applied to coding and MH coding.

EFFECTS OF THE INVENTION As described above, according to the present invention, the MPU is
The sequential access to the buffer register between the shift register and the shift register and the shift of the data of one block by the shift register operate in parallel, and further, the shift processing of the data of one block by the shift register is performed. Since the processing is completed while the MPU is accessing the buffer register, etc., the MPU can operate sequentially without detecting the completion of the shift processing, thus improving the encoding processing speed.

[Brief description of drawings]

FIG. 1 is a block diagram of an encoding / decoding device according to an embodiment of the present invention, FIGS. 2 to 4 are timing diagrams at the time of encoding, FIGS. 5 to 7 are timing diagrams at the time of decoding, and FIG. It is a figure which shows the concept of the encoding order in a sequential reproduction encoding system. 1 ... MPU, 2 ... image memory, 3 ... code memory,
4-8 ... Register, 9-13 ... Shift register, 14 ...
… Shift control circuit, 15 …… State detection circuit, 16 …… Extraction circuit, 17 …… Change point detection circuit, 18 …… Counter.

Front page continuation (72) Inventor Toshiaki Endo 2-23 Nakameguro, Meguro-ku, Tokyo Inside Kokusai Telegraph and Telephone Corporation (72) Inventor Hisaharu Kato 2-12-23 Nakameguro, Meguro-ku, Tokyo International Telegraph and Telephone Corporation Research Institute (72) Inventor Nyoichi Nishino 1006 Kadoma, Kadoma City, Matsushita Electric Industrial Co., Ltd. (72) Inventor Hiroshi Kusao 1006 Kadoma, Kadoma City, Matsushita Electric Industrial Co., Ltd. (72) Inventor Akira Hirasawa 1006 Kadoma, Kadoma, Kadoma-shi, Matsushita Electric Industrial Co., Ltd. (72) Hiroshi Miki 2-3-8 Shimomeguro, Meguro-ku, Tokyo Matsushita Electric Transport Co., Ltd. (72) Inventor, Shoji Asaba Tokyo 2-3-8 Shimomeguro, Meguro-ku, Tokyo Matsushita Electric Transport Co., Ltd.

Claims (1)

(57) [Claims] 1. A reference pixel register group for setting reference pixel data in block units, a coded pixel register for setting coded pixel data in block units, the reference pixel register group and the coded pixel group. Shift control means for outputting a load signal for loading data in a register, reference pixel shift register groups for respectively loading and shifting data in the reference pixel register group according to the load signal, and the load signal According to the above, the coded pixel shift register for loading and shifting the data of the coded pixel register, the data set of each register, and the activation of the shift control means for performing the shift operation of each shift register. The shift control means is provided with a microprocessor. When the shift is completed, control is performed to stop the shift operation of each shift register until the next activation is started, and the microprocessor access to the reference pixel register group and the coded pixel register and the shift register of each shift register. An encoding device characterized in that shift operations are performed in parallel.