JP2705290B2 - Image processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a conversion device that inputs data represented by facsimile encoding, performs screen enlargement / reduction conversion if necessary, and outputs data represented by facsimile encoding. .

[Prior Art] FIG. 3 shows, for example, Mitsubishi Electric Technical Report Vol.
FIG. 3 is a configuration diagram of a facsimile code conversion device using a circuit described in “One-chip facsimile band compression / expansion circuit by SI design method”. In the figure, (30) is a one-chip LS
I-band compression / expansion circuit, (31) facsimile recording unit, (32) facsimile original reading unit, (33) pixel thinning unit, (34) switch for decoded image signal, (35) (36) two line memories for decoding, (37) two line memories for encoding, (3)
8) and (41) are readout line switches, (39) and (4)
0) is a write line switch, (42) is a decryption controller, (4)
3) is an encoding controller, (44) is a facsimile encoded data input interface, and (45) is a facsimile encoded data output interface.

Next, the operation will be described. The configuration shown in FIG. 3 is not only used as a code conversion device, but also encodes an image signal read by a reading unit (32) and decodes coded data into a recording unit (33).
Can be used to output recording paper. When used as an encoding conversion device, the switch (34) is on the B side, and the switch (35) is on the B side.
Side, and the decoded image signal is supplied to the pixel thinning unit (3
3) The band compression / decompression circuit (3
Set to the state where it is input again to 0).

The flow of processing as a transcoder is described as follows. First, the decoding controller (42) decodes the input facsimile encoded data (44),
The pixel is reproduced by writing to the other line memory while referring to the reference line pixel data read from one of the pixels. When the decoding of one line is completed, the switches (38) and (39) are switched in preparation for the next decoding. Next, the image signal of the decoded line is transferred to the pixel thinning section (33). When reduction in the main scanning direction is necessary, the pixel thinning unit (33) thins out pixels in accordance with the reduction ratio and writes the pixel into one of the line memories (37). Further, when an image signal for one line is written to the line memory, the encoding control unit (43) is activated, and the other line memory is used as a reference line for one line.
The encoding process for the lines is performed, and encoded data (45) is output. Then, the switches (40) and (41) are switched in preparation for the next encoding. The above processing procedure corresponds to one cycle, and by repeating this cycle, the encoding conversion processing can be performed. At this time, when performing line thinning in the sub-scanning direction, after the decoding process of one line is completed, the decoding process of the next line is performed without transferring the image signal of the decoded line. Then, the decoded image signal of the line is transferred to the pixel thinning unit (33) to perform the encoding process.

In the case of such a conventional configuration, since the decoding processing unit and the encoding processing unit are independent, it is possible to perform the encoding and simultaneously perform the decoding processing of the next line. FIG. 11 (a) shows a flow of processing when the image is reduced to 2/3 in the sub-scanning direction.

As a facsimile coding method, an MH (Modified Huffman) code is used as a one-dimensional coding method, and an MR (Modified Read) code is used as a two-dimensional coding method. In the case of the MR code, it is necessary to encode (or decode) the next line by referring to the line that has been encoded (or decoded) immediately before,
This means that the encoding unit and the decoding unit each require two lines.

[Problems to be Solved by the Invention] Since the conventional facsimile code conversion device is configured as described above, two devices are used for decoding and two devices are used for encoding.
Since a total of four line memories are required, and a part for performing the decoding process and a part for performing the encoding are separately required, there is a disadvantage that the circuit scale becomes large. In addition, there is a problem that an extra procedure such as transferring the decoded pixel data to the encoding processing unit is required.
Further, the reduction processing by thinning has a disadvantage that image quality is deteriorated such as disappearance of a thin line. For example, when the image of FIG. 6 is reduced to 2/3 in the main scanning direction and the sub-scanning direction, the thin lines disappear as shown in FIG.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a facsimile code conversion apparatus with a smaller circuit scale and a processing circuit capable of suppressing deterioration in image quality at the time of reduction. And

[Means for Solving the Problems] An image processing apparatus according to the present invention comprises: decoding image data, reference image data, and image data to be encoded;
Storage means for storing each line, first switching means provided on the input side of the storage means and distributing the decoded image data decoded by the decoding means described below to predetermined lines, and storage means A second switching unit provided on the output side of the storage unit, for extracting reference image data or image data to be encoded from a predetermined line of the storage unit;
Decoding processing for the externally encoded input encoded data based on the reference image data extracted from the storage means by the second switching means by inputting the externally encoded input encoded data. And decoding means for outputting the decoded image data subjected to the decoding process to the first switching means for writing to the storage means, and a reference extracted from the storage means by the second switching means. An encoding unit that performs an encoding process based on image data and image data to be encoded, and outputs the encoded data that has been encoded to the outside; In order to switch the line distribution and extraction of each image data to the storage unit at a ratio corresponding to the reduction ratio in accordance with the reduction ratio, the first switching unit is connected to the first switching unit. In which a control means for controlling the second switching means.

In the encoding process of the encoding unit, after decoding a plurality of lines, the pixel data of the line to be thinned out in the sub-scanning direction is encoded while ORing with the pixel data of the line to be encoded. Things.

In the encoding process of the encoding means, the pixel to be decimated is logically ORed with the next pixel to be encoded, and the pixel is decimated in the main scanning direction and then encoded.

[Operation] In the facsimile code conversion device according to the present invention, the line memory is reduced to three lines, and the portion for performing the encoding and decoding processes is shared, so that the circuit scale can be reduced. In addition, by performing a logical sum operation when performing reduction by thinning, the disappearance of thin lines can be prevented, and image quality with less deterioration can be obtained.

Embodiment An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, (2) is a line memory for three lines,
(3) is a switch for selecting a line memory to which the pixel data decoded by the first switch is to be written, and (4) is a second switch for outputting the output of each of the three line memories to the reference line Y1,
A switch selectively connected to the encoding line Y2 and the thinning line Y3, (5) an encoding / decoding controller for performing encoding or decoding, and (10) for encoding / decoding data. An input / output interface with the outside, (11) an address commonly output from the encoding / decoding controller to the three line memories, (12) a switching control signal of the switching unit (3), and (13) a switching A switching control signal of the unit (4), (14) reproduced pixel data decoded by the encoding / decoding controller,
(15) is the reference line pixel data, (16) is the coded line pixel data, (17) is the ON / OFF control signal for the OR processing of the pixel data of the reference line and the thinned line, and (18) is the coded line. ON / O of OR operation of pixel data of thinning line
FF control signal. An encoding / decoding controller (5)
FIG. 2 shows the internal configuration. In the figure, (6) is a controller, (7) is an address counter, (8) is a controller for thinning out pixels in the main scanning direction, (19) is a reset signal of the address counter, and (20) is a count-up pulse of the address counter. , (21) is also a countdown pulse,
(22) is a thinned pixel instruction signal output from the pixel thinning control unit, and (23) is a logical sum processing control signal.

In the line memory, white pixels are 0 and black pixels are 1
Shall be written.

The line memory (2) is a storage unit for storing the decoded image data, the reference image data, and the encoded image data for each line, and the switching unit (3) is a first switching unit and a switching unit (4). ) Is the second switching means,
The decoding controller (5) corresponds to an encoding unit, a decoding unit, and a control unit.

 Next, the operation of this embodiment will be described.

The operation of the present apparatus can be roughly divided into a decoding operation and an encoding operation. The decryption operation depends on the input / output interface (1
0) is decoded and selected by the switch (3) while referring to the reference line pixel data (15) read from the line memory (2) selected by the switch (4). The reproduced pixel data is written to the line memory. In the encoding operation, encoding is performed with reference to the reference line pixel data (15) and the encoded line pixel data (16) from the line memory (2) selected by the switch (4), and the encoded data is input. Output to the output interface (10).

The encoding operation in the case of the MR code will be described focusing on the operation of the encoding / decoding controller (5). In encoding one line, the encoding / decoding controller (5) first switches the switch (4) to select a line memory to be used for the reference line and the encoding line. As the reference line, it is necessary to select the line memory used as the encoding line in the immediately preceding encoding. Next, the controller (6) outputs a reset signal (19) and sets the address counter (7) to the reset state, and then starts the encoding process. Address (1
Since 1) is common to the three line memories, the reference line pixel data (15) and the encoded line pixel data are input to the encoding / decoding controller (5) at the same address. As shown in FIG. 5, the encoding / decoding controller (5) can determine the encoding mode according to the four state transitions determined by the two pixel data. For example, an encoding example in the case of pixel data as shown in FIG. 4 is shown below. First, since three pixels from the beginning of the line remain in the state a in FIG. 5 and transition to the state d at the fourth pixel, this is coded in the vertical mode V (0). Next, at the address 3, when starting from the state d, the state transits to the state b, and once again stops at the state b, and then transits to the state a. Therefore, the state is encoded by V _R (2) in the vertical mode. Next, at the address 6, since the state starts from the state a, transits to the state c, and returns to the state a, this is encoded in the pass mode P. Next is the state a at the address 11
, After passing through state b twice and transiting to state d, this is encoded in the vertical mode V _L (2). Only in the V _L mode, after encoding, an operation of returning (decreasing) the address before the next departure is required. That is, in the case of V _L (x) (x = 1, 2, 3), the address is returned by x. In the case of this example, the next departure is performed from address 15 by returning two from 17. This is because, in principle, the changed pixel position of the coding line becomes the starting point of the next coding. Now, starting from the state b at the address 15, the state becomes the state a via the state d, and this is coded in the vertical mode V (0). Next, starting from state a at address 19, state a is changed three times and state b is changed to four.
After returning to the state a, the horizontal mode H
, And the white run-length 3 and the black run-length 4 are subsequently encoded with the MH code. Hereinafter, starting from the state "a" of the address 26, the same processing is performed, and the encoding of one line is executed.

Next, the decoding operation for the MR code will be described. When decoding one line, the encoding / decoding controller (5)
First, the switches (3) and (4) are switched to select the line memories used for the decoding line and the reference line, respectively. As the reference line, it is necessary to select the line memory used as the decoding line in the immediately preceding decoding. Next, the controller (6) outputs a reset signal (19) to reset the address counter (7), and then starts the decoding process. Since the address (11) is common to the three line memories, the reference line pixel data (1
The address of the reproduced pixel data (14) written as (5) will be the same. The encoding / decoding controller (5) decodes the MR encoded data input from the input / output interface (10) and decodes the reproduced pixel data (14) while referring to the reference line pixel data (15). It will be written to line memory. For example, an example of decoding in the case of encoded data and reference pixel data as shown in FIG. 4 will be described below. First, as a result of decoding encoded data, the first encoding mode is decoded as V (0), so that white is reproduced on the decoded line up to the address position where the reference line changes from white to black. . Therefore, white pixels are reproduced up to address 2. Since the next encoding mode is decoded as V _R (2), starting from address 3, black is reproduced on the decoded line up to two pixels after the pixel data of the reference line changes to white. Therefore, black pixels are reproduced up to address 5. Since the next encoding mode is decoded as the pass mode P, starting from the address 6, the decoding line is reproduced up to the address 11 where the reference line temporarily turns black and returns to white again. Since the next encoding mode is decoded as V _L (2), white is reproduced on the decoding line up to address 17 at which the reference line changes from white to black, and then the address is returned (decreased) by two. Operation is required. Since the next code or mode is decoded as vertical mode V (0), starting from address 15, black is reproduced on the decoded line until the reference line goes black and returns to white again.
Since the next encoding mode is decoded as the horizontal mode H (3,4), white is first reproduced from the addresses 19 to 21 on the decoding line regardless of the pixel data of the reference line,
Subsequently, black is reproduced from addresses 22 to 25. Thereafter, similar processing is performed, and one-line decoding is executed. When performing equal-size conversion in the sub-scanning direction (that is, neither enlargement nor reduction), the decoding process and the decoding process are performed by 1
This is performed alternately in line units. When performing reduction in the sub-scanning direction, lines are thinned out, which is realized by reducing the number of coding lines compared to the number of decoding lines. For example, when reducing to 2/3, as shown in Fig. 11 (b), by repeating the procedure of decoding, encoding, decoding, decoding and encoding, thinning out one line per three lines is realized. it can.

However, when line thinning is simply performed, there is a disadvantage that the horizontal thin line disappears as shown in the conventional example. Therefore, in the present embodiment, the line to be decimated is devised so as to be able to perform the encoding process while calculating the logical sum with the next encoding line. Hereinafter, the logical sum processing of the thinned lines will be described.

In FIG. 1, Y1 of the output of the switch (4) corresponds to a reference line, Y2 corresponds to a coding line, and Y3 corresponds to a thinning line, and is connected to any one of the inputs 11, 12, and 13 on a one-to-one basis. If the encoding / decoding controller (5) turns on the logical sum processing control signal (17) (logic 1), the logical sum processing of Y1 and Y3 is performed. The logical sum of the same address pixels of the line and the thinned line can be obtained. Similarly, when the encoding / decoding controller (5) turns on the logical sum processing control signal (18) (logic 1), Y2 and Y3
Is ORed, the encoded line pixel data (1
As 6), the logical sum of the same address pixels of the encoding line and the thinning line can be obtained.

FIG. 9 shows a flow of processing in the case where the size is reduced to 2/3 in the sub-scanning direction. The hollow column in the figure indicates that the column is redundant. First,
In the processing number 1, the switch (4) has I1 connected to Y1, the switch (3) has X2 connected to D, and the OR control (17) has 0
Since it is (OFF), decoding is performed using the line memory (2a) as a reference line, and reproduced pixel data is written on the line memory (2b). In the next process number 2, the switch (4)
Since I1 is connected to Y1, I2 is connected to Y2, and I3 is connected to Y3, and the OR control (17) and (18) are both 0, the line memory (2a) is used as a reference line, and the line memory (2b) is used. Encoding is performed as an encoding line. In the next processing number 3, since I2 is connected to Y1 and D is connected to X3, decoding is performed using the line memory (2b) as a reference line, and reproduced pixel data is written on the line memory (2c). In the next processing number 4, decoding is similarly performed using the line memory (2c) as a reference line, and reproduced pixel data is written on the line memory (2a). In the next processing number 5, the line memory (2b)
Is a reference line, the line memory (2a) is a coding line, and the line memory (2c) is a thinning line. Since the OR processing control signal (18) is 1 (ON), the coding line and the thinning line The ORed pixel data is encoded. In the next processing number 6, the line memory (2a)
Is used as a reference line, and reproduced pixel data is written in the line memory (2b). In the next processing number 7,
Line memory (2a) is the reference line, line memory (2b)
Is an encoding line, and the line memory (2c) is a thinning line. Since the logical sum processing control signal (17) is 1 (ON), pixel data obtained by logical sum of the reference line and the thinning line is referred to as a reference line pixel. Encoded as data. This is because, in the immediately preceding encoding process (ie, process number 5), the pixel data obtained by performing the logical sum of the line memories (2a) and (2c) is encoded. Line memory (2
This is because it is necessary to use pixel data obtained by performing a logical sum of (a) and (2c). The next processing number 8 is the same as the processing number 3, and the next processing number 9 is the same as 4 and 10 is the same as 5. Therefore, after that, it is only necessary to repeat the process from the process numbers 3 to 7 in order. In this way, when the image data is reduced in the sub-scanning direction, the thinned line can be encoded by performing a logical sum process.

On the other hand, even in the case of reduction in the main scanning direction, it is desired to perform a logical OR process of thinned pixels in order to prevent disappearance of a vertical thin line. In the present embodiment, the control section (8) for pixel thinning in FIG.
Performs this function.

Hereinafter, the logical sum processing of the thinned pixels in the main scanning direction will be described. The pixel thinning controller (8) includes a thinning counter corresponding to the cycle of reduction. For example, when reducing to 2/3, the thinning counter counts 3 as a cycle. The thinning counter is reset by a reset signal (19) of the address counter, counts up by a count-up pulse (20), and counts down by a count-down pulse (21). A pixel thinning controller (8) is configured to output a thinning pixel instruction signal (22) and a logical sum processing control signal (23) based on a counter value of a thinning counter and a count-up pulse (20) or count-down pulse (21) input thereto. Is output. For example, FIG. 10 shows an example of the case where the size is reduced to 2/3. First, a reset signal (19) is input prior to encoding of each line.
The address counter (7) and the thinning counter are reset. Subsequently, when a count-up pulse (20) is input, the address counter (7) and the thinning counter are sequentially incremented. When the count-up pulse (20) is input while the value of the thinning counter is 0, the thinning counter becomes 1 and the thinning pixel instruction signal (22) turns ON (logic 1). When the thinned pixel instruction signal is ON, the controller (6) ignores the pixel at that address and attempts to encode the pixel at the next address. At the next address, the thinned pixel instruction signal (22) is turned off and the logical sum processing control signal (23) is turned on instead, so that the controller (6) eventually sends the current pixel data value as reference pixel data to the controller (6). The logical sum of the immediately preceding thinned pixel data value is input, and the encoded pixel data of which the logical sum of the current pixel data value and the immediately preceding thinned pixel data value is input. Since the cycle of the thinning counter is 3, such processing is performed in units of three pixels thereafter. On the other hand, when the countdown pulse (21) is input, the thinning pixel instruction signal (22) is turned on when the value of the thinning counter is 2, and the logical sum processing control signal is turned on when the value of the thinning counter is 1. .
Therefore, in the case of countdown, the thinning counter is set to 2
The pixel at the time of (1) is thinned out, and this is logically ORed with the pixel at the time of the next thinning counter being 1, and the controller (6)
Will be processed.

This is because, in the case of the _VL mode in the MR code, the operation of returning the address is necessary as described above, but in the process of returning the address, the pixel is treated exactly the same as when the address is increased. It is.

With the above-described processing, the thinned-out pixels in the main scanning direction can be subjected to the logical sum processing and encoded. FIG. 8 shows an image in which the pixels in FIG. 6 are reduced to 2/3 by the code conversion apparatus of the present embodiment, and the vertical fine lines and the horizontal fine lines are preserved without disappearing, and a good image quality is obtained. It is understood that it can be done.

Note that, in the above-described embodiment, a case where reduction is performed to 2/3 in both the main scanning direction and the sub-scanning direction has been described. However, it is apparent that an arbitrary reduction ratio of M / N can be realized.

Further, in the above embodiment, the case of the MR code was shown as the encoding method. However, as the data input / output via the input / output interface (10), for example, the encoding mode (V (0), V _R (x), V
_L (y), P, H).

Although the above embodiment has described the facsimile code conversion, it goes without saying that the device can be used as a facsimile coding / decoding device by providing an input / output interface for pixel data.

[Effects of the Invention] As described above, according to the present invention, three line memories are used.
Since the number of lines is reduced and the portion for performing the encoding and decoding processes is shared, the circuit scale can be reduced and the price can be reduced.

Further, an unnecessary procedure of transferring the decoded pixel data to the encoding processing unit can be omitted.

Further, in the case of reduction, since thinning lines and pixels are subjected to logical OR processing with lines and pixels to be processed next and then subjected to encoding processing, fine lines can be prevented from disappearing and good image quality can be obtained. .

[Brief description of the drawings]

FIG. 1 is a diagram showing a facsimile code conversion apparatus according to an embodiment of the present invention, FIG. 2 is a diagram showing the internal configuration of an encoding / decoding controller in FIG. 1, and FIG. 3 is a conventional facsimile code. FIG. 4 is a diagram showing a conversion device, FIG. 4 is a diagram showing an example of MR encoding,
FIG. 5 is a diagram showing a state transition at the time of MR encoding, FIG. 6 is a diagram showing an example of an image, and FIG. 7 is a case where the image of FIG. 6 is reduced to 2/3 by a conventional facsimile converter. FIG. 8 is a diagram showing an image when the image of FIG. 6 is reduced to 2/3 by the apparatus of the present invention, and FIG. 9 is 2 / in the sub-scanning direction by the apparatus of the present invention.
FIG. 10 is a diagram showing a procedure of processing when the image is reduced to 3, FIG. 10 is a time chart when the image is reduced to 2/3 in the main scanning direction, and FIG. FIG. 11B is a diagram showing a flow of processing in the case of reduction, and FIG. 11B is a diagram showing a flow of reduction in the sub-scanning direction to 2/3 in the apparatus of the present invention. (2) ... three line memories, (3), (4) ... switch, (5) ... encoding / decoding controller, (17), (1)
8) Thinning-out control signal. In the drawings, the same reference numerals indicate the same or corresponding parts.

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yuji Hirokawa 4-1-1 Mizuhara, Itami-shi, Hyogo Mitsubishi Electric Corporation Kita-Itami Works (56) References JP-A-62-202668 (JP, A) JP-A-2-19898 (JP, A) JP-A-2-54675 (JP, A) JP-A-4-35362 (JP, A)

Claims (3)

(57) [Claims] An externally coded input coded data is inputted, and a decoding process is performed while referring to the input coded data with already decoded image data (reference image data). The encoding process is performed while referring to the processed image data and the already encoded image data (reference image data), and the decoding process or the encoding process is controlled to perform the reduction ratio conversion process of the input encoded data. And an image processing apparatus for outputting the coded data subjected to the above-described coding processing to the outside, comprising: storage means (2) for storing decoded image data, reference image data, and image data to be coded for each line; First switching means (3) provided on the input side of the storage means for distributing the decoded image data decoded by the decoding means described below to predetermined lines; Second switching means (4) provided on the output side of the stage for extracting reference image data from a predetermined line of the storage means or image data to be coded, and the externally encoded input code Inputting encoded data, performing decoding processing on the externally encoded input encoded data based on the reference image data extracted from the storage means by the second switching means, and performing decoding processing. Decoding means (5) for outputting the decoded image data to the first switching means for writing to the storage means, and encoding the reference image data extracted from the storage means by the second switching means with the decoding means. Encoding means (5) for performing an encoding process based on image data to be processed and outputting the encoded data subjected to the encoding process to the outside; In accordance with the reduction rate for the encoded input encoded data, line distribution of the image data in the storage means,
In order to switch the extraction at a ratio corresponding to the reduction ratio, the first
An image processing apparatus comprising: a switching unit for controlling the switching unit and a control unit for controlling the second switching unit. 2. The encoding process of the encoding means, after decoding a plurality of lines, performs a logical OR operation with pixel data of a line for encoding pixel data of a line thinned in the sub-scanning direction. 2. The image processing apparatus according to claim 1, wherein encoding is performed while performing the encoding. 3. The encoding process of the encoding means, wherein a pixel to be decimated is logically ordinally calculated with the next pixel to be encoded, and after the pixels are decimated in the main scanning direction, encoding is performed. The image processing device according to claim 1 or 2.