JPH08205192A - Image encoding device - Google Patents

Abstract

PURPOSE: To provide the image encoding device of MPEG1 standards which can output a P and an I picture and has its necessary memory capacity reduced. CONSTITUTION: This device is equipped with a reference image buffer 12 which temporarily holds image data PP consisting of only vertical pixels as many as those in a vertical vector search range of image data DI of one frame and a bus controller 11 which overwrites the image data PP in the area of the image data DP stored in an image frame memory 10 after the image data DP are referred to.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus,
In particular, the present invention relates to an image encoding device that encodes video data in conformity with the MPEG standard.

[0002]

2. Description of the Related Art ISO / IEC, JTC1 / are used as interframe predictive coding systems for video signals of televisions and the like.
MPEG (Movi) standardized by SC2 / WG8
ngPicture Expert Group) is known. This one is recommended ISO
The MPEG1 standard defined in / IEC-11172-2 (1993) (reference 1) defines a decoder. MPEG1 video encoder refers to a device that generates a bit string of encoded video data that can be decoded by an MPEG1 video coder.

In the MPEG1 standard, three image types are defined, and an intra-frame compressed image (I picture),
Time-series past reference images (P-pictures), time-series past
It is called a future reference image (B picture). Of course, the MPEG1 video decoder is required to have all the decoding capabilities of these I, P, and B pictures, but the MPEG1 video encoder does not include B or P pictures if the bit rate of the output bit string satisfies the regulation. You may generate the bit string only for a picture.

The reference image coding apparatus, which is the recommended MPEG1 video encoder described in Document 1, has an encoding capability compatible with all I, P, and B pictures.

FIG. 4 is a block diagram showing the reference image coding apparatus.
Referring to FIG. 1, the reference image coding apparatus shown in FIG. 1 includes a frame reorder circuit 31 for inputting an image signal DI and outputting coding target data DE, and a motion vector of the coding target data DE for detecting a signal D, a vector. A motion compensation (MC) processor 30 including a motion vector detection circuit 32 which outputs V and mode M, and an adder 33 which outputs difference data DD in response to the supply of the signal D, and the difference data D
Discrete cosine transform circuit (DCT) 34 that performs discrete cosine transform of D to generate signal DT, quantizer circuit 35 that quantizes signal DT to generate data DQ, and data DQ is variable-length coded and compressed to code data. A variable length coding circuit (VLC) 36 for generating a CD, an inverse quantization circuit 37 for dequantizing the data DQ and generating a signal IT, and an inverse discrete cosine transform for inverse discrete cosine transforming the signal IT to generate a signal ID. A circuit (IDCT) 38, an adder circuit 40 for adding the signal ID and the past image DP to generate a signal PI, and a signal P.
I, vector V, mode M is input and past image D for reference
Past image buffer 39 that outputs P, and encoded data C
D, vector V, mode M are selectively output to output data A
A multiplexer 41 for generating D, a buffer 42 for generating output data DO and data BO in response to the supply of data AD, and a regulator 43 for generating data QC in response to the supply of data BO are provided.

The operation of the reference image coding apparatus will be described with reference to FIG. 4. Image data DI separated into a luminance component and a color component by a luminance / color (Y / C) decoder (not shown) is frame reordered. It is supplied to the MC processor 30 via the circuit 31, and the MC processor 30
Is the past image DP supplied from the past image buffer 39.
, The difference data DD is output with respect to the obtained motion vector V.

Referring also to FIG. 5 showing the concept of retrieval of the motion vector V, in the MPEG1 image, a macro block (MB) consisting of a luminance component of 16 × 16 pixels and a color component of 8 × 8 pixels is basically used. Handle as a unit.
The MC processor 30 performs a vector search on the internal luminance component of this MB as follows. Current MB to search
, ± 15 or ± 7 from the same coordinates of the reference image
The sum of the squared differences is calculated, and the vector having the smallest sum of the squared differences is set as the motion vector V.

Upon receiving the supply of the differential data DD output from the MC processor 30, the DCT 34 performs a DCT operation on the differential data DD to generate a signal DT decomposed into frequency components. The quantization circuit 35 quantizes each frequency component of the signal DT to generate quantized data DQ,
It is supplied to the LC 36 and the inverse quantization circuit 37, respectively.
The VLC 36 outputs the encoded data CD generated by performing variable-length code compression on the supplied quantized data DQ via the multiplexer 41 and the buffer circuit 42 as data DO.

On the other hand, the dequantization circuit 37 dequantizes the supplied quantized data DQ to generate data IT and I
The data is supplied to the DCT 38, and the IDCT 38 reverses the data IT.
CT calculation is performed to generate a signal ID, which is supplied to the adder circuit 41. The adder circuit 41 adds the signal ID and the past image DP from the past image buffer 39 to generate image data PI for updating the past image DP and writes it back to the past image buffer 39.
That is, the dequantization circuit 37, the IDCT 38, and the addition circuit 41 form a feedback loop for the past image buffer.

In the above-mentioned reference image coding apparatus, a calculation operation particularly occurs in the generation of B pictures, which hinders real-time processing, and increases the scale of hardware and software, which causes a price increase. As described above, by omitting the B picture, the device can be simplified.

Referring to FIG. 6, which shows a block diagram of a conventional first image coding apparatus which is simplified by generating only I pictures, the conventional first image coding apparatus shown in FIG. The input image data DI is DCT operated, quantized and variable-length coded to generate an output signal DO, a bus controller 2, and image data memories 3 and 4 for double buffering.

The encoding processor 1 has the functions of the DCT 34 of the reference image encoding device, the quantization circuit 35, and the VLC 36.

The operation will be described with reference to FIG.
The input image data DI is transferred to the image data memory 3 or 4 via the bus controller 2. One of the image data memories 3 and 4 which is not currently transferring the image data DI, that is, the image data memory 4 is coded when the image data DI is being transferred to the image data memory 3, and the image data memory 3 is coded when the image data DI is being transferred. Connected to the processor 1 via the bus controller 2. As a result, the image data DI
Even during the transfer to the image data memory, the image compression operation conforming to MPEG1 can be performed. The output DO of the encoding processor 1 is written in the recording medium.

Here, when encoding the input image data PI of 352 × 240 pixels, the luminance level is 8 according to the 4: 2: 0 format in which the color signal information amount 2 corresponds to the luminance signal information amount 4. When quantized with bits, the required memory area of the buffer image data memory is 127k
It becomes a byte. Therefore, the required memory capacity of this first image coding apparatus is 254 kbytes.

Further, since the first conventional image coding apparatus only generates I pictures, the compression rate is low at the prescribed bit rate of the MPEG1 standard, and the image quality is degraded.

To improve this, in addition to the I picture, P
Referring to FIG. 7, which shows a block diagram of a conventional second image coding device simplified by generating a picture and omitting only the B picture, FIG. 7 shows a block diagram of a conventional second image coding device shown in FIG. The difference from the second encoding device is that in FIG.
In addition to the constituent elements 2 to 4, the function of the encoding processor 1 includes the inverse quantization circuit 37, ID of the conventional reference image encoding device.
An encoding processor 1A further including the function of CT38;
A reference field including a motion compensation (MC) processor 5 having substantially the same function as the MC processor 30 of the conventional standard image encoding device, and a RAM corresponding to the past image buffer 39 and storing the previous image data (past image data). And a memory 6.

The operation of the second conventional image coding apparatus will be described with reference to FIG. 7. The input image data DI passes through the bus controller 2 and the image data memory 3 similarly to the second image coding apparatus. , Or 4, and is also supplied to the MC processor 5. The MC processor 5 uses the past image data DP from the reference field memory 6.
After calculating the motion vector in the input image data DI, the past image data DP is calculated based on the motion vector.
And the difference data DD is calculated. The difference data DD output from the MC processor 5 is supplied to the encoding processor 1, and the encoding processor 1A determines the DC of the difference data DD.
Output data DO after T calculation, quantization, and variable length coding
Output as Also, inverse quantization of this quantized data,
The IDCT operation is performed, and the obtained data PI is written back to the reference field memory 6.

Under the same encoding conditions as the conventional first image encoding device, the required memory capacity of the image data memory for the buffer is 381 kbytes. Also, the required memory capacity of the RAM that constitutes the reference frame memory is 2 screens,
That is, it becomes 508 kbytes.

[0019]

The first conventional image coding apparatus described above has a small memory capacity required for the image data buffer, but can generate only the I picture, and thus the MPE.
The G1 standard bit rate has a drawback that the image quality is deteriorated because the compression rate is low.

The second conventional image coding apparatus, which has improved this, requires a large capacity RAM for the reference frame memory as the required memory capacity of the image data buffer increases, and the area after the reference is This RAM has a drawback that the usage efficiency of this RAM is very poor because it is not used until the frame.

[0021]

According to the image coding apparatus of the present invention, the first image data composed of the separated luminance signal and chrominance signal is divided into a predetermined number of pixels in the vertical and horizontal directions for each frame. First image data storage means for outputting macroblock data, which is block data for a predetermined number of pixels of the image data when storing and reading.
The first image data and the past reference image data of the previous frame of the first image data are compared for each macroblock data within a predetermined vertical and horizontal search range to search for a motion vector. A motion compensation processor that outputs corresponding difference data, and a frame according to a predetermined data format by performing discrete cosine transform and quantization of the difference data to generate quantized data and performing variable length coding of the quantized data. An encoding processor that generates inner compressed image data as output data, performs dequantization and inverse discrete cosine transform of the quantized data to generate second image data, and stores the second image data at the time of reading. In an image encoding device including a second image data storage unit that outputs the past reference image data, Partial image data consisting of only the same number of vertical pixels as the vertical search range of the first image data for a frame is generated as the second image data, and the second image data is stored in the past. It is configured to include a memory control unit that overwrites an area in the reference image data after the reference is completed.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A first embodiment of the present invention will now be described with reference to FIG. 1, which is also shown in block form with common reference characters / numbers for components common to FIG. The image coding apparatus according to the present embodiment is the same as the conventional coding processor 1.
In addition to the MC processor 7 and the input image data DI
FIFO that sequentially stores data and outputs data DF in input order
7, a direct memory access controller (DMAC) 8 for controlling the input / output to / from the input image buffer 9 for scan conversion of the data DF, the input image buffer 9 for temporarily storing the data DF, and the past data of the previous frame. An image frame memory 10 for storing image data, a bus controller 11, and a reference image buffer 1 for temporarily holding past image partial data to be transferred to the image frame memory.
2 and.

Next, the operation of this embodiment will be described with reference to FIG. 1. First, similarly to the conventional case, a luminance / color (Y / C) decoder (not shown) separates the luminance component and the color component. The processed image data DI is temporarily stored in the FIFO 7, and the DMAC 8 transfers the output data DF of the FIFO 7 to the input image buffer 9. Normally, the image data DI stored in the FIFO 7 is decoded with the movement of the scanning line with the upper left corner of the screen as the origin, and thus becomes the data for each horizontal scan (raster scan data). Meanwhile, M
In the PEG1 encoder, as described above, 16 × 1
Since processing is performed in units of 6-pixel macro blocks (MB), it is necessary to change the raster scan data into block scan data. Therefore, it is transferred to the randomly accessible image buffer 9 using the DMAC 8. When 352 × 240 pixel image data is quantized with 8 bits for both luminance and color signals as in the conventional case, the required memory capacity of the input image buffer 9 is 8448 bytes.

The MC processor 5 performs motion compensation using the MB data MB read from the input image buffer 9 and the past image data DP read from the image frame memory,
The difference data DD generated as a result is supplied to the encoding processor 1A. The encoding processor 1A is a conventional second
Similarly to the image encoding device of FIG. 1, the difference data DD is DCT-operated, quantized, and variable-length encoded to generate the output signal DO, and inversely quantized, and IDCT operation is performed to generate the past image partial data PP. To generate. The past image partial data PP is stored in the bus controller 1 as described below.
It is held in the reference image buffer 12 under the control of No. 1 and transferred to the image frame memory 10.

Referring to FIG. 2 showing the basic concept of the buffer operation of the reference image buffer 12 of the present embodiment, FIG.
It is assumed that the coordinate position of the MB 52 in the 352 × 240 pixel image 51 to be encoded shown in (A) is (32, 48) with the upper left corner of the screen as the origin (0, 0). When the motion vector search is performed, ± 15 from the position of the MB 62 at the same coordinates in the reference past image 61 shown in FIG.
The vector search range 63 is a square having the diagonal lines of (17, 33) and (47, 79).
Therefore, when searching the reference area 65 including the vector search range 63, Y in the past image 61 is searched.
The area 64 in the range of 0 to 16 on the axis is irrelevant to the search, and since the MB is processed from the upper left, it is not referred to thereafter. Therefore, the reference image buffer 1
The required memory capacity of 2 may be the same as that of the area 65, and the past image partial data PP temporarily stored after the end of the reference is written back to the image frame memory 10.

The required memory size of the reference image buffer 12 is 253 when the vector search range is MB coordinates ± 15.
44 bytes, and 16896 bytes for MB coordinates ± 7.

From the above conditions, the required memory capacities of the FIFO 7, the input image buffer 9, and the image frame memory 10 are 127 Kbytes, 8448 bytes, and 127 Kbytes, respectively. When obtained, the vector search range is about 288 kbytes when the MB coordinate is ± 15, and 280 kbytes when the MB coordinate is ± 7.

This corresponds to about 56% of the required memory capacity of 508 Kbytes of the reference frame memory 6 of the conventional second encoding device.

A second embodiment of the invention will now be described with reference to FIG. 3, which is also a block, with common reference characters / numbers for components common to FIG. The difference from the first embodiment of the image coding apparatus of the embodiment is that the MC processor 5, the coding processor 1, and the input image buffer 9 are different.
The reference image buffer 12 is replaced with a DSP 19 which is a general programmable high-speed processor having a well-known architecture called Harvard architecture having an internal data bus with separated memory and instructions.

The DSP 19 has internal data buses 28 and 29.
Local memories 20, 2 respectively connected to the input image buffer 9 and the reference image buffer 12, respectively.
3, a register 21, an ALU 22, an instruction memory 24, a control unit 25, and a DMAC 26.
, Selectors 17 and 27, and internal data buses 28 and 29
With.

The operation of this example will be described with reference to FIG. 3. First, the input image data is stored in the FIFO 7, and the output image data DF is stored in the internal data bus 28.
Stored in the local memory 20 via. Further, the past image DP for reference is read from the image memory 10 connected to the outside of the internal data bus 29, and the image data D
The P, the register 21, and the ALU 22 refer to the image data MB corresponding to the image data DF read from the local memory 20, and perform motion compensation, DCT calculation, IDCT calculation, quantization, dequantization, and variable length coding. Perform processing.

The encoded output data DO is the internal data bus 2
9 is output to a recording medium connected to the outside of the internal storage medium 9 and is locally decoded by the IDCT operation and inverse quantization of the ALU 22.
It is temporarily stored in the local memory 23 connected to the server 9.

The data temporarily stored is as follows.
It is written back to the reference image memory 10. According to the instruction from the instruction memory 24, the activation signal R is supplied from the control unit 25 to the DMAC 26 at a predetermined timing. In response to the supply of the activation signal R, the DMAC switches the internal data bus using the selectors 27 and 30, and DMA-transfers the data PP held in the local memory 23 to the image frame memory 10.

By using the DSP having such a configuration, it is possible to obtain the same effect as that of the first embodiment, and it is possible to reduce the number of external connection devices such as the MC processor and the encoding processor.

[0035]

As described above, the image coding apparatus of the present invention generates partial image data consisting of the same number of pixels in the vertical direction as the vector search range in the vertical direction in one frame of image data. By providing the memory control means for overwriting the partial image data in the area of the past reference image data after the end of the reference, the required memory capacity can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a first embodiment of an image coding apparatus according to the present invention.

FIG. 2 is a conceptual diagram showing a basic concept of buffer operation of image data in the image encoding apparatus of the present embodiment.

FIG. 3 is a block diagram showing a second embodiment of the image encoding device of the present invention.

FIG. 4 is a block diagram showing an example of a reference image encoding device which is a recommended video encoder of the MPEG1 standard.

FIG. 5 is a conceptual diagram showing the concept of a motion vector search operation.

FIG. 6 is a block diagram showing a first conventional image coding apparatus.

FIG. 7 is a block diagram showing a second conventional image coding apparatus.

[Explanation of symbols]

 1, 1A Encoding processor 2, 11 Bus controller 3, 4 Image data memory 5, 30 MC processor 6 Reference frame memory 7 FIFO 8, 26 DMAC 9 Input image buffer 10 Image frame memory 12 Reference image buffer 19 DSP 20, 23 Local Memory 21 Register 22 ALU 24 Instruction memory 25 Control unit 17, 27 Selector 28, 29 Internal data bus 31 Frame reorder circuit 32 Motion vector detection circuit 33, 40 Adder circuit 34 DCT 35 Quantization circuit 36 VLC 37 Inverse quantization circuit 38 IDCT 39 Past image buffer 41 Multiplexer 42 Buffer 43 Regulator 51,61 Image 52,62 MB 63 Bekettle search range 64,65 area

Claims (3)

[Claims] 1. The first image data composed of separated luminance signal and chrominance signal is stored for each one frame composed of a plurality of pixels in predetermined vertical and horizontal directions, and the predetermined number of pixels of the image data is read out at the time of reading. First image data storage means for outputting macroblock data, which is block data for a minute, and predetermined vertical and vertical directions of the first image data and past reference image data of a frame preceding the first image data. A motion compensation processor that searches for a motion vector for each macroblock data within a horizontal search range and outputs corresponding difference data; and a discrete cosine transform and quantization of the difference data to generate quantized data. Then, this quantized data is subjected to variable length coding, and compressed image data within a frame according to a predetermined data format is output data. And an encoding processor that performs inverse quantization and inverse discrete cosine transform of the quantized data to generate second image data, and stores the second image data and outputs it as the past reference image data at the time of reading. In the image coding device including the second image data storage means, partial image data including only the same number of vertical pixels as the vertical search range of the first image data for one frame is generated. An image coding apparatus, comprising: memory control means for generating the second image data and overwriting the second image data in an area in the past reference image data after completion of the reference. 2. The memory control means stores third image data storage means for temporarily holding the second image data output from the encoding processor, and stores the second image data after completion of the vector search. The image encoding apparatus according to claim 1, further comprising a bus control unit that transfers the third image data storage unit to the second image data storage unit. 3. The image code according to claim 1, wherein the encoding processor comprises an integrated circuit digital signal processing device including the second and third image data memories and the bus control means. Device.