JPH08163371A - Encoding/decoding device - Google Patents

Abstract

PURPOSE: To provide the encoding/decoding device which doesn't require the external circuit which changes the timing of a vertical synchronizing signal neither the change of a parameter value set to an internal register. CONSTITUTION: The operation required for encoding and decoding of digitized picture data is started based on the vertical synchronizing signal which indicates the division of one picture of digitized picture data. This encoding/decoding device 10 is provided with a timing control part 103 which generates a signal START, which has the same period as the vertical synchronizing signal and is delayed by a prescribed extent and initializes the encoding and decoding operation, and sets the extents of delay for encoding and decoding based on information from the outside (CPU).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coding / decoding device for coding and decoding digitized image data in real time.

[0002]

2. Description of the Related Art In JPEG (International Standard for Still Image Coding) and the like, an image coding / decoding method using orthogonal transform such as discrete cosine transform (DCT) is used as an image compression technique. And when encoding the image,
The system is such that the digitized video data is directly supplied to the encoding / decoding device to be encoded, and at the time of decoding, the decoded data is displayed as it is as video data.

The configuration of the above system is shown in FIG. A / D
The converter 22 converts an analog video signal from the outside such as a VTR or a camera (not shown) into digital video data. The encoding / decoding device 20 uses the A /
The video data digitized by the D converter 22 is encoded and output to the external memory 24. At the time of decoding, the coded data is read from the external memory 24 and decoded into video data. The decoded video data is output to the D / A converter 23. The D / A converter 23 converts the digital video data from the encoding / decoding device 20 into an analog video signal, and outputs this analog video signal to an external monitor or the like.

The line memory 21 is used for converting video data from raster to block during encoding, and for converting block to raster during decoding.

FIG. 6 is a conceptual diagram showing the raster / block conversion. As shown in FIG. 7A, the image data is sent in raster order (from the upper left of the screen to the lower right). For orthogonal transform such as discrete cosine transform, it is necessary to make image data into blocks of 8 pixels × 8 pixels as shown in FIG. Therefore, the data for 8 lines is once written in the line memory 21, the read address is controlled, and the data is read again from the line memory 21 to obtain pixel data of a block of 8 pixels × 8 pixels.

The encoding / decoding device 20 operates in synchronization with the vertical synchronizing signal and the horizontal synchronizing signal of the video signal, and processes only valid data of the video signal. As shown in FIG. 7, this effective signal period is determined by the blanking period and the effective line period from the vertical synchronizing signal, the blanking period from the horizontal synchronizing signal, and the effective pixel number, and the encoding / coding is performed.
In the decoding device 20, these parameter values are set in the internal register.

FIG. 8 is a block diagram showing the internal configuration of the encoding / decoding device 20. Based on this block diagram, the operation of continuously encoding images will be described below.

When the encoding / decoding device 20 receives an encoding start command from the outside during encoding, the vertical sync signal rises (when the vertical sync signal is in the negative theory,
It is a fall, but here it is a positive theory signal and it is a rise. ) To initialize the inside and start operation.

The raster / block conversion unit 201 does not take in data during the blanking period from the rising of the vertical synchronizing signal and becomes the valid period at the timing A.
The digital video data output from the / D converter 22 is captured. Then, in order to perform the orthogonal transformation, the line memory 21 is used to perform the transformation from the raster to the block as described above.

Blocked pixel data is encoded /
It is sent to the decoding unit 202. The encoding / decoding unit 202 executes the encoding process and stores the encoded data in the external memory 2
4 is output. The operation ends when all the image data in the effective area is encoded and the output of this encoded data is completed.
When the vertical synchronizing signal is input again after the operation is completed, the above operation is repeated.

On the other hand, at the time of decoding, as in the case of encoding, when an operation start instruction is received from the outside, the encoding / decoding device 20 initializes the inside (memory contents etc.) at the rising edge of the vertical synchronizing signal. Start operation. When the operation starts,
The coding / decoding unit 202 reads the coded data from the external memory 24, decodes the coded data, and sends the decoded block data to the raster block conversion unit 201. The raster block conversion unit 201 outputs the pixel data in raster order by temporarily writing the block data in the line memory 21, contrary to the encoding, and controlling the read address to read the data again from the line memory 21.

The output pixel data is output in synchronization with the effective period of the image. Then, when the output of all the image data is completed, the operation is completed. When the vertical synchronizing signal is input again after the operation is completed, the above operation is repeated. At the time of this decoding, unlike at the time of encoding, the encoding / decoding device 20
In the case of outputting image data from, it is necessary to write the data in the line memory 21 before outputting the data.

[0013]

The continuous encoding processing and the decoding processing are performed as described above, but further conditions are required to perform the continuous encoding and decoding processing. .

FIG. 9 shows a timing chart at the time of encoding. In this figure, the valid screen represents the valid area (hatched portion) in FIG. 7, and indicates that the "H" state is the valid screen. The same applies to FIG. 10 described later. Then, at the time of encoding, since the image data is encoded via the line memory 21, a delay of the line memory (eight lines) occurs.

Therefore, by the time the encoding processing for the entire one field image is completed, 8 horizontal periods from the input of the final image data + internal processing time (denoted by α in the figure). Is required.

FIG. 10 shows a timing chart at the time of decoding. As described above, at the time of decoding, unlike the case of encoding, when outputting data from the encoding / decoding device 22, the data of line memory (eight lines) is stored in the line memory 21 before outputting the data. Need to be written.

However, the TV standard such as NTSC does not standardize the blanking period before the rising of the vertical synchronizing signal and the blanking period after the rising of the vertical synchronizing signal. Therefore, blanking suitable for encoding / decoding is performed. The timing may not be reached.

For example, as shown in FIG. 11, if the blanking period from the final image data to the next vertical synchronizing signal is 5.5 horizontal periods, the vertical synchronizing signal rises in the middle of the encoding operation and is initialized. Because it will be
All the data stored in the line memory 21 cannot be encoded, and normal operation cannot be performed.

Further, at the time of decoding, as shown in FIG. 12, if the blanking period from the rising edge of the vertical synchronizing signal is 4 horizontal periods, the decoded data is externally output after the decoding operation is started. The effective area of the screen starts before the output of. That is, there is an inconvenience that data is not output even when the effective area is reached.

Therefore, in the prior art, as the vertical synchronizing signal supplied to the encoding / decoding device 20, a signal whose timing is different from that of the original vertical synchronizing signal is supplied, and this signal is used for the encoding / decoding device. 20 was working. However, this requires an external circuit that changes the timing of the vertical synchronizing signal, and the hardware scale is large, which increases the cost. Also, the timing of the vertical synchronizing signal is changed by this external circuit, and the encoding / decoding device 20
It is also necessary to change the parameter value set in the internal register in 1., and further, it is necessary to change the parameter value in each of the encoding operation and the decoding operation.

In view of the above circumstances, the present invention does not require an external circuit for changing the timing of the vertical synchronizing signal, and does not need to change the parameter value set in the internal register. The purpose is to provide.

[0022]

In order to solve the above-mentioned problems, an encoding / decoding device of the present invention uses a digital signal based on a first signal indicating a division of one screen of digitized image data. In an encoding / decoding device that starts an operation required for encoding and decoding the encoded image data,
Means for generating a second signal which has the same period as the first signal and is delayed by a predetermined amount to initialize the encoding and decoding operations; and the respective delay amounts at the time of encoding and at the time of decoding. And means for setting based on the information from.

Further, in the above structure, a negative value may be set as the information from the outside for setting the respective delay amounts at the time of encoding and at the time of decoding.

[0024]

According to the first configuration, the encoding and decoding operations are initialized by the second signal having the same period as the first signal and delayed by a predetermined amount. Therefore, for example, even if the blanking period from the final image data to the next first signal is 5.5 horizontal periods on the external side, 8 horizontal periods + internal processing time are set in the encoding / decoding device. By setting the second signal that is ensured, initialization is not performed even if the first signal rises during the encoding operation, and all the data can be encoded. Even at the time of decoding, even if the blanking period from the rising edge of the first signal is 4 horizontal periods on the external side, 8 horizontal periods + internal processing time are secured in the encoding / decoding device. By setting the second signal, it is possible to prevent the effective area of the screen from starting after the decoding operation is started and before outputting the decoded data to the outside.

Therefore, an external circuit for changing the timing of the first signal is not necessary, and the cost of the second signal can be reduced because the second signal generating means can be constructed with hardware smaller than this external circuit. Since the blanking period from the first signal in the encoder / decoder to the start of the valid screen does not change, it is not necessary to change the parameter value set in the internal register of the encoder / decoder. Become.

Further, according to the second configuration, a negative value can be set as the information from the outside for setting the respective delay amounts at the time of encoding and at the time of decoding. Therefore, instead of giving a positive value with a large number of digits as the delay amount of the second signal from the outside to the encoding / decoding device, it is possible to give a negative value with a small number of digits equivalent thereto. The delay amount can be easily set.

[0027]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings showing its embodiments.

FIG. 1 shows an encoding / decoding device 10 of the present invention.
It is a schematic block diagram showing. Peripheral circuits similar to those of the conventional example shown in FIG. 5 are arranged around the encoding / decoding device 10, but only the line memory 11 is shown in FIG. Then, in the encoding / decoding device 10, the raster / block conversion unit 101, the encoding / decoding unit 102, and the CPU interface 104, as in the conventional case.
Is provided.

The raster / block conversion unit 101 and the encoding / decoding unit 102 execute the raster / block conversion and the encoding / decoding process using the line memory 11 as described in the conventional example. START described later
When a signal is received, it is initialized by the rising edge of the signal.

The above encoding / decoding device 10 is provided with a timing control section 103. A vertical synchronizing signal (first signal) and a horizontal synchronizing signal are input to the timing control unit 103, and
From a CPU (not shown) to the CPU interface 10
The N setting information, the total number of lines information, and the operation start instruction signal, which will be described later, are input via the command line 4. Then, the timing control unit 103 generates a START signal (second signal) based on the above-mentioned information, and uses this to generate the raster / block conversion unit 101 and the encoding / coding unit.
Output to the decoding unit 102.

FIG. 2 shows the timing control section 1 described above.
3 is a schematic block diagram showing an internal configuration of 03. FIG.

A vertical synchronizing signal, an operation start instruction signal, and a clock are input to the pulse generating circuit 600. The pulse generation circuit 600 starts operation in response to the operation start instruction signal, detects the rising edge of the vertical synchronization signal, generates a pulse synchronized with the clock, and outputs this pulse to START.
The signal is output to the signal delay circuit 601.

The START signal delay circuit 601 inputs the pulse and the horizontal synchronizing signal from the pulse generation circuit 600, the delay amount information from the delay amount calculation circuit 602, and the delay amount according to the delay amount information. Only after that, the START signal is output. For example, when information such as "5" is received as the delay amount from the delay amount calculation circuit 602, the START signal is output when 5 pulses of the horizontal synchronizing signal are counted. In addition, START
The signal delay circuit 601 uses a clock to pulse the START signal. The START signal is generated every time the vertical synchronizing signal rises.

The delay amount calculation circuit 602 receives the N value information from the N setting register 603 and the total line number information from the total line number register 604, and generates the delay amount information based on these information. For example, N setting register 6
If the N value information from 03 is a positive value, this is used as it is as a delay amount, and if the N value information from the N setting register 603 is a negative value, all lines which are information from the total line number register 604. The value obtained by subtracting the N value from the number is the delay amount.

Each of the above information is transferred from the CPU to the N setting register 603 and the total line number register 604 and stored therein.

Next, the operation of the encoding / decoding device 10 having the above-described configuration at the time of encoding and at the time of decoding will be described.

(At the time of encoding) Raster / block converter 1
In 01, the area of the effective screen is determined from the vertical synchronizing signal and the horizontal synchronizing signal, and the input video data is written into the line memory 11 for 8 lines, and then the line memory 1
Data is read from 1 in block order and conversion from raster to block is performed. Then, the blocked data is transferred to the encoding / decoding unit 103.

The encoding / decoding unit 103 performs DCT conversion and quantization on the block data and then encodes the coded data, and outputs the coded data to the outside (memory 2).
Output to 4). Then, when the coding of the data of the effective area (effective screen) for one screen is completed, the operation is automatically ended. After that, when the vertical synchronizing signal rises, the same operation is started again.

Here, as shown in FIG. 3, it is assumed that there is only 5.5 horizontal periods from the end of the effective screen to the next vertical synchronizing signal. If it is assumed that the processing time inside the encoding / decoding device 10 requires a maximum of one horizontal period, the final image data will be processed by the time the encoding process for the entire one-field image is completed. After inputting, a total of 9 horizontal periods of 8 horizontal periods + 1 horizontal period are required.

Under such an assumption, for example, STA
The N value is set so that the generation of the RT signal is delayed by 5 horizontal periods from the vertical synchronizing signal. In this case, a total of 10.5 horizontal periods is ensured by the above 5.5 horizontal periods + 5 horizontal periods from the input of the final image data to the generation of the START signal. The START signal serves as an initialization signal for the raster / block conversion unit 101 and the encoding / decoding unit 102, and is set to 1 after the final image data is input.
Since the initialization is performed after 0.5 horizontal period, the encoding process for the entire one-field image ends during this period. That is, all the data stored in the line memory 11 can be encoded, and the normal operation is performed.

(At the time of decryption) At the time of decryption, external (CPU)
When an operation start instruction is received from the STA, the timing control unit 103 outputs a START signal.
Raster / block converter 10 at the rise of RT signal
1 and the encoding / decoding unit 102 are initialized, and the operation is started.

That is, the encoding / decoding unit 102 reads code data by outputting a read signal to the outside (external memory) to decode the code data, and decodes the decoded block data to the raster / block conversion unit. Transfer to 101. In the raster / block conversion unit 101, the block data is once written in the line memory 11 contrary to the time of encoding, and the data is read again from the line memory 11 to convert and output the data in the raster order. The output data is output in synchronization with the valid period of the image. Then, when the output of all the image data is completed, the operation ends. When the vertical synchronizing signal is input again after the operation is completed, the above operation is started.

Here, as shown in FIG. 4, it is assumed that the period from the rising of the vertical synchronizing signal to the beginning of the effective screen is only four horizontal periods. Assuming that the processing time inside the encoding / decoding device 10 requires a maximum of 1 horizontal period, the period from the rise of the vertical synchronization signal to the start of the effective screen is 8 horizontal periods + 1 horizontal period. A total of 9 horizontal periods are required.

Under such an assumption, for example, STA
N (N = -5) is set so that the generation of the RT signal proceeds from the vertical synchronizing signal by 5 horizontal periods. In this case, the value obtained by subtracting “5” from the total number of lines is the delay amount, so ST
From the generation of the ART signal to the start of the effective screen, a total of 9 horizontal periods are secured in the above 4 horizontal periods + 5 horizontal periods. Therefore, by the start of the valid screen, the writing of the data of 8 lines to the line memory 11 has already been completed, and the decoding operation is normally performed.

As described above, since the delay amount can be set to a negative value such as N = -5, it is easy to set the operation start timing before and after the rising of the vertical synchronizing signal.
That is, START from the outside to the encoding / decoding device 10
Instead of giving a positive value with a large number of digits as a signal delay amount, it is possible to give a negative value with a small number of digits equivalent to this, so that the delay amount can be set easily. In particular, the advantage is great in an HDTV having a large number of scanning lines.

Further, in this embodiment, the horizontal synchronizing signal is counted and the START signal is delayed, but it may be delayed by a clock instead of the horizontal synchronizing signal.

[0047]

As described above, according to the present invention, the external circuit for changing the timing of the vertical synchronizing signal is not required, the cost can be reduced, and the internal register of the encoding / decoding device can be set. Therefore, it is not necessary to change the parameter value. Further, by adopting a configuration in which a negative value can be set as the information from the outside for setting the respective delay amounts at the time of encoding and at the time of decoding, it is possible to easily set the delay amount.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an encoding / decoding device of the present invention.

FIG. 2 is a schematic block diagram showing a timing control unit of the encoding / decoding device of the present invention.

FIG. 3 is a time chart showing various signals during encoding according to the present invention.

FIG. 4 is a time chart showing various signals at the time of decoding according to the present invention.

FIG. 5 is a block diagram showing an encoding / decoding device and its peripheral circuit.

FIG. 6 is a conceptual diagram illustrating raster / block conversion.

FIG. 7 is a conceptual diagram illustrating an effective area of a screen.

FIG. 8 is a schematic block diagram showing a conventional encoding / decoding device.

[Fig. 9] Fig. 9 is a time chart of various signals in the case where encoding can be performed favorably during conventional encoding.

FIG. 10 is a time chart of various signals when good decoding can be performed during conventional decoding.

FIG. 11 is a time chart of various signals when encoding cannot be performed favorably during conventional encoding.

FIG. 12 is a time chart of various signals when decoding cannot be performed well in conventional decoding.

[Explanation of symbols]

 10 Encoding / decoding device 101 Raster / block conversion unit 102 Encoding / decoding unit 103 Timing control unit 104 CPU interface 600 Pulse generation circuit 601 START signal delay circuit 602 Delay amount calculation circuit 603 N setting register 604 Total line number register

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Claims (2)

[Claims] 1. An encoding / decoding device for starting an operation required for encoding and decoding of digitized image data based on a first signal indicating a division of one screen of digitized image data. A means for generating a second signal which has the same cycle as the first signal and is delayed by a predetermined amount to initialize the encoding and decoding operations, and the respective delay amounts at the time of encoding and at the time of decoding And a means for setting based on information from outside, the encoding / decoding device. 2. A negative value can be set as the information from the outside for setting each delay amount at the time of encoding and at the time of decoding. Encoding / decoding device.