JP2505186Y2 - Memory module - Google Patents
Memory moduleInfo
- Publication number
- JP2505186Y2 JP2505186Y2 JP1130590U JP1130590U JP2505186Y2 JP 2505186 Y2 JP2505186 Y2 JP 2505186Y2 JP 1130590 U JP1130590 U JP 1130590U JP 1130590 U JP1130590 U JP 1130590U JP 2505186 Y2 JP2505186 Y2 JP 2505186Y2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memory module
- control signal
- element control
- impedance matching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Landscapes
- Static Random-Access Memory (AREA)
Description
【考案の詳細な説明】 〔産業上の利用分野〕 本考案はメモリモジュールに関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial application] The present invention relates to a memory module.
従来、この種のメモリモジュールは、メモリ素子制御
信号伝送路にインピーダンス整合素子が設けられていな
かった。Conventionally, this type of memory module has not been provided with an impedance matching element in the memory element control signal transmission line.
上述した従来のメモリモジュールは、情報処理装置等
に実装されたとき、インピーダンス不整合がある場合、
メモリ素子制御信号に反射波の影響により信号割れや信
号の減衰等が生じ、その悪影響が制御信号駆動回路のい
きい値を超えてしまうと、メモリが誤って書き込まれた
り、読み取られたりしてしまうという問題点があった。When the conventional memory module described above is mounted on an information processing device or the like and has an impedance mismatch,
When the memory element control signal is affected by the reflected wave and the signal is broken or attenuated, and the adverse effect exceeds the threshold value of the control signal drive circuit, the memory may be erroneously written or read. There was a problem that it would end up.
本考案の目的は、メモリ素子制御信号のインピーダン
ス不整合に起因する信号割れや信号の減衰等を防ぎ、メ
モリ素子の誤動作を防ぐことができるメモリモジュール
を提供することにある。An object of the present invention is to provide a memory module capable of preventing signal breakage, signal attenuation, etc. due to impedance mismatch of memory device control signals and preventing malfunction of memory devices.
本考案のメモリモジュールは、複数のメモリ素子を有
して一つの情報単位を構成するメモリモジュールにおい
て、前記メモリモジュール内のメモリ素子を制御するメ
モリ素子制御信号の伝送路にインピーダンス整合素子を
有している。According to another aspect of the present invention, there is provided a memory module having a plurality of memory elements to form one information unit, and having an impedance matching element in a transmission path of a memory element control signal for controlling the memory elements in the memory module. ing.
次に、本考案の実施例について図面を参照して説明す
る。Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本考案の一実施例のブロック図である。 FIG. 1 is a block diagram of an embodiment of the present invention.
第１図において、メモリコントローラ１よりメモリ素
子制御信号２が複数のメモリモジュール3a〜3cに並列に
出力される。その各々のメモリモジュールにおいて、メ
モリ素子制御信号２はインピーダンス整合素子５を介し
てメモリ素子4a〜4bへ伝達される。メモリ素子制御信号
２は、メモリモジュール3a〜3cの数がどのような数であ
ってもインピーダンス整合素子５があるため、反射波の
影響が最小限に抑えられ、メモリ素子制御信号のインピ
ーダンス不整合に起因する信号割れや信号の減衰等を防
ぎ、メモリ素子の誤動作を防ぐことができる。In FIG. 1, a memory element control signal 2 is output from a memory controller 1 to a plurality of memory modules 3a to 3c in parallel. In each of the memory modules, the memory element control signal 2 is transmitted to the memory elements 4a-4b through the impedance matching element 5. Since the memory element control signal 2 has the impedance matching element 5 regardless of the number of the memory modules 3a to 3c, the influence of the reflected wave can be minimized and the impedance mismatch of the memory element control signal can be suppressed. It is possible to prevent signal breakage, signal attenuation, etc. due to the above, and to prevent malfunction of the memory element.
以上説明したように、本考案は、メモリモジュールの
メモリ素子制御信号伝送路にインピーダンス整合素子を
挿入することにより、メモリ素子制御信号のインピーダ
ンス不整合に起因する信号割れや信号の減衰等を防ぎ、
メモリ素子の誤動作を防ぐことができるという効果を有
する。As described above, according to the present invention, by inserting the impedance matching element in the memory element control signal transmission line of the memory module, it is possible to prevent signal breakage and signal attenuation due to the impedance mismatch of the memory element control signal.
This has an effect of preventing malfunction of the memory element.
第１図は本考案の一実施例のブロック図である。 １……メモリコントローラ、２……メモリ素子制御信
号、3a〜3c……メモリモジュール、4a〜4b……メモリ素
子、５……インピーダンス整合素子。FIG. 1 is a block diagram of an embodiment of the present invention. 1 ... Memory controller, 2 ... Memory element control signal, 3a-3c ... Memory module, 4a-4b ... Memory element, 5 ... Impedance matching element.
Claims (1)
を構成するメモリモジュールにおいて、前記メモリモジ
ュール内のメモリ素子を制御するメモリ素子制御信号の
伝送路にインピーダンス整合素子を有することを特徴と
するメモリモジュール。1. A memory module having a plurality of memory elements to form one information unit, wherein an impedance matching element is provided in a transmission path of a memory element control signal for controlling the memory elements in the memory module. And a memory module.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1130590U JP2505186Y2 (en) | 1990-02-06 | 1990-02-06 | Memory module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1130590U JP2505186Y2 (en) | 1990-02-06 | 1990-02-06 | Memory module |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03104222U JPH03104222U (en) | 1991-10-29 |
| JP2505186Y2 true JP2505186Y2 (en) | 1996-07-24 |
Family
ID=31514838
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1130590U Expired - Lifetime JP2505186Y2 (en) | 1990-02-06 | 1990-02-06 | Memory module |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2505186Y2 (en) |
-
1990
- 1990-02-06 JP JP1130590U patent/JP2505186Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH03104222U (en) | 1991-10-29 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R323531 |
|
| R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |