JPH01296327A - Bus line for computer - Google Patents

Abstract

PURPOSE:To transmit signals without deterioration so as to eliminate malfunctions even at the time of high-speed clocks by forming bus lines constituted of micro-strip lines on a multilayered printed board and providing various apparatuses to the bus lines. CONSTITUTION:Branching filters 4, bus transceivers 5, memories 7 and 8, and devices 9 and 10 are provided to the data buses 2 using micro-strip lines. The transceivers 5 perform two-way amplification, are controlled in direction by the read/write select signal R/W of a CPU 1, and transmit signals between the various apparatuses and CPU 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to the structure of bus lines for a computer's CPU, main memory, and peripheral devices that require high speed.

[Conventional technology]

Conventionally, computer bus line wiring did not perform impedance matching, and the impedance on the output side was
It was designed in such a way that it could be driven as long as it was lower than the combined impedance of multiple inputs, and the wiring only needed to be connected in a direct current manner.

[Problem to be solved by the invention]

However, computers are becoming faster and faster every year, and some have clock frequencies exceeding several hundred MHz. As a result, bus line wiring cannot correctly transmit signal waveforms at high frequencies due to inductance and stray capacitance. In FIG. 5, the human input signal is mixed with noise on the output side, resulting in an output like A in the drawing. If the input resistor voltage of the device connected to the output side falls below the voltage at point P, and the response speed of the device is fast, a malfunction will occur.

[Means to solve the problem]

A bus line consisting of a microstrip line is formed on a multilayer printed board, and a CPU, main memory, etc. are wired thereto. The bus line includes a duplexer, a buffer amplifier with impedance matching, and a bus transceiver (amplifier).
Insert.

[Effect]

With this structure, signals are transmitted without deterioration and no malfunction occurs even when operated with a high-speed clock signal.

〔Example〕

Figure 1 shows an embodiment of the present invention, where l is a CPU, 2 is a data bus using a microstrip line, 3 is an address bus using a microstrip line, and 4 is a broadband demultiplexer that can also transmit DC components. 5 amplifies in both directions,
It is a path transceiver with an amplitude limiting function, and its direction is controlled by the CPU's read/write selection signal W/R. 6
is a buffer amplifier that returns the signal that has been attenuated due to demultiplexing to its original level. 7 and 8 are memories of the main storage device, which are connected to the address bus and the data bus. 9.10 is a peripheral device. Since the address bus and data bus are usually formed of 8 to 32 signals, the duplexer 4, path transceiver 5, and buffer amplifier 6 have the number of circuits corresponding to the number of signals.

FIG. 2 shows an example of a circuit for one signal of a path transceiver. 11 and 12 are three-state buffers having an amplitude limiting function and an amplifying function. Either buffer 11 or 12 is selected by the read/write selection signal W/H of the CPU, and the input impedance is configured to be infinite when not selected and equal to the bus impedance when selected. ing.

FIG. 3 shows another embodiment of the path transceiver, 13
is a circulator, and 14 and 15 are wideband amplifiers. The signal input from terminal P is sent to the circulator and amplifier 1.
4 and the circulator, and is output to terminal q. The signal input from terminal q passes through the circulator to amplifier 15.
and is output to terminal P via a circulator. This circuit is combined with the same number of signals on the bus to form a path transceiver.

Figure 4 is an example of a microstrip line formed on a multilayer printed board, with 16 and 17 as a ground pattern, 18 as a microstrip line pattern formed on the outside, and 19 as a ground pattern with a shielding effect. The microstrip line 20 sandwiched between is an insulator that also serves as a dielectric.

Figure 5 shows a clock signal, a bus input signal, and a bus output signal. Output A has the conventional transmission characteristic without impedance matching, and output B has the first transmission characteristic.
Although the amplitude is attenuated by the 0 splitter which is the transmission characteristic at point B in the figure, the waveform is faithfully transmitted and the noise margin is large with respect to the threshold of the buffer amplifier 6.

〔Effect of the invention〕

As described above, the present invention has the following effects.

(1) The transmission delay time is constant regardless of frequency,
Since the waveform can be transmitted without deterioration, there is no malfunction when operating with a high frequency clock.

(2) Since impedance matching is achieved, constant pressure waves and noise are less mixed in and there are no malfunctions.

(Due to 31 impedance matching, electromagnetic waves emitted from bus lines etc. are extremely weak, making EMI countermeasures easy. This leads to cost reduction.

(4) Computer systems can operate at higher frequencies, improving performance.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIGS. 2 and 3 are circuit diagrams of an embodiment of a path transceiver, FIG. 4 is a perspective view of a microstrip line, and FIG.
The figure is a timing diagram showing a comparison of a clock signal, a bus input signal, and a bus output signal. 1... CPU 2... Data bus 3... Address bus 4... Duplexer 5... Bus transceiver 6... Buffer amplifier 7.8... Memory 9, IO... Peripheral Applicant: SEIKO ELECTRONICS INDUSTRIAL CO., LTD. Patent attorney: Keisuke Hayashi Figure 1 Main house θ eye Busturi L-no circuit 4 yen 3 Figures

Claims (1)

[Claims] A printed wiring board (hereinafter referred to as a printed board), a central processing unit (hereinafter referred to as a CPU) mounted on the printed board, a memory serving as a main storage device, and a microstrip line formed on the printed board. 1. A bus line for a computer, characterized in that a bus line is formed from the microstrip line, and a duplexer and a buffer amplifier are connected to the microstrip line.