JP2503030B2 - Active matrix display device - Google Patents
Active matrix display deviceInfo
- Publication number
- JP2503030B2 JP2503030B2 JP25272787A JP25272787A JP2503030B2 JP 2503030 B2 JP2503030 B2 JP 2503030B2 JP 25272787 A JP25272787 A JP 25272787A JP 25272787 A JP25272787 A JP 25272787A JP 2503030 B2 JP2503030 B2 JP 2503030B2
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- electrode
- gate
- thin film
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011159 matrix material Substances 0.000 title claims description 19
- 239000010408 film Substances 0.000 claims description 16
- 239000010409 thin film Substances 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 7
- 230000007547 defect Effects 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 101100489584 Solanum lycopersicum TFT1 gene Proteins 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000002950 deficient Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000032683 aging Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
Description
【発明の詳細な説明】 〔概要〕 本発明はアクティブマトリクス型表示装置に関し、 閾値不良により歩留低下と経時不良の問題を解決する
ために、電気的な手段で容易に薄膜トランジスタの閾値
を制御することのできるアクティブマトリクス型表示装
置を提供することを目的とし、 対向配置された一対の透明基板と、該一対の透明基板
の一方の表面に、平行に配列された複数本のスキャンバ
スラインと、マトリクス状に配置された複数個の表示電
極と、該表示電極に対応する薄膜トランジスタの第１ゲ
ート電極と，該第１ゲート電極にゲート絶縁膜，動作半
導体層を介して対向配置されたソース電極，ドレイン電
極が、それぞれ当該薄膜トランジスタに対応するスキャ
ンバスライン，対応する表示電極，隣のスキャンバスラ
インに接続され、他方の透明基板の表面に複数本のデー
タバスラインが配設された構成を有する薄膜トランジス
タマトリクスにおいて、前記ソース電極およびドレイン
電極の前記第１ゲート電極と反対側に、絶縁膜を介して
配設された第２ゲート電極を具備するよう構成した。DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an active matrix display device, and in order to solve the problems of yield reduction and aging defects due to defective thresholds, the thresholds of thin film transistors are easily controlled by electrical means. For the purpose of providing an active matrix type display device capable of performing the above, a pair of transparent substrates arranged to face each other, and a plurality of scan bus lines arranged in parallel on one surface of the pair of transparent substrates, A plurality of display electrodes arranged in a matrix, a first gate electrode of a thin film transistor corresponding to the display electrodes, a source electrode arranged to face the first gate electrode via a gate insulating film and an operating semiconductor layer, The drain electrodes are connected to the scan bus line corresponding to the thin film transistor, the corresponding display electrode, and the adjacent scan bus line, In a thin film transistor matrix having a structure in which a plurality of data bus lines are arranged on the surface of the other transparent substrate, the thin film transistor matrix is arranged on the side opposite to the first gate electrode of the source electrode and the drain electrode via an insulating film. And a second gate electrode.
本発明はアクティブマトリクス型表示装置に関する。 The present invention relates to an active matrix type display device.
アクティブマトリクス型の表示装置は、多数の画素を
それぞれ独立に駆動させることができるので、表示容量
の増大に伴ってライン数が増大しても、単純マトリクス
型表示装置のように駆動デューティ比が低下して、コン
トラストの低下や視野角の減少をきたす等の問題が生じ
ない利点を有する。しかし各画素ごとにスイッチング素
子を設けるためコストアップとなり、また構造が複雑と
なることから製造歩留に問題があった。Since the active matrix type display device can drive a large number of pixels independently of each other, even if the number of lines increases as the display capacity increases, the drive duty ratio decreases as in the simple matrix type display device. As a result, there is an advantage that problems such as a decrease in contrast and a viewing angle do not occur. However, since the switching element is provided for each pixel, the cost is increased and the structure is complicated, which causes a problem in manufacturing yield.
そこで本願発明者らは先に、アクティブマトリクス型
表示装置の製造歩留を向上させると同時に、高い表示品
質を実現できるスキャンバス階梯状接続対向マトリクス
方式〔これをゲート接続方式とも言う〕を、特願昭61-2
12696号にて提案した。Therefore, the inventors of the present invention have previously proposed a scan bus ladder connection opposed matrix system [also referred to as a gate connection system] which can improve the manufacturing yield of an active matrix type display device and at the same time realize high display quality. Wish 61-2
Proposed in No. 12696.
上記スキャンバス階梯状接続対向マトリクス方式は、
第５図及び第６図に示す如く、データバスラインDBとス
キャンバスラインSBを別々の透明基板3,3′に配置し、
且つ各表示セルLCを駆動するTFT（薄膜トランジスタ）
１のゲート電極Ｇは対応するスキャンバスラインSBに、
ソース電極Ｓは対応する表示セルLCの表示電極Ｅに接続
し、ドレイン電極Ｄは隣の例えば走査順位が次位のスキ
ャンバスラインSB′に接続した、階梯状接続のスキャン
バス接続群を少なくとも１個設けた構造である。The above scan bus floor ladder connection opposite matrix system,
As shown in FIG. 5 and FIG. 6, the data bus line DB and the scan bus line SB are arranged on different transparent substrates 3, 3 ′,
In addition, TFT (thin film transistor) that drives each display cell LC
The gate electrode G of 1 is connected to the corresponding scan bus line SB,
The source electrode S is connected to the display electrode E of the corresponding display cell LC, and the drain electrode D is connected to the adjacent scan bus line SB ′ having the next highest scanning order, for example. It is a structure provided individually.
この方式は、表示欠陥の一つの大きな要因となってい
たバスラインのクロスオーバがなく、データ電圧波形の
振幅を小さくできることから、クロストークを抑えるこ
とでき、高画質表示が得られるものである。In this method, there is no bus line crossover, which is one of the major causes of display defects, and the amplitude of the data voltage waveform can be reduced, so that crosstalk can be suppressed and high quality display can be obtained.
この方式のアクティブマトリクス回路が本来の動作を
行うためには、これを構成するTFT1がゲートバイアス0V
の状態でオフ状態となる必要がある。即ち、通常用いら
れるエレクトロンアキュムレーション型のTFTの場合、
閾値電圧が正の値をとることが必要である。In order for the active matrix circuit of this method to perform the original operation, the TFT1 that constitutes it must have a gate bias of 0V.
It is necessary to be turned off in the state of. That is, in the case of a commonly used electron accumulation type TFT,
It is necessary that the threshold voltage has a positive value.
しかしTFTの閾値電圧は、プロセスの不安定要因，特
にプラズマを用いたプロセス等での電極の帯電により影
響を受け、これが製造歩留を下げる要因となる。また閾
値は数時間の駆動により変化するため、この閾値の変化
が寿命を決定するということも問題となる。However, the threshold voltage of the TFT is affected by the process instability factor, particularly the charging of the electrode in the process using plasma, which causes the manufacturing yield to be reduced. Further, since the threshold value changes by driving for several hours, it is also a problem that the change of the threshold value determines the life.
本発明は閾値不良により歩留低下と経時不良の問題を
解決するために、電気的な手段で容易にTFTの閾値を制
御することのできるアクティブマトリクス型表示装置を
提供することを目的とする。It is an object of the present invention to provide an active matrix type display device capable of easily controlling the threshold value of a TFT by electrical means in order to solve the problems of yield reduction and deterioration with time due to defective threshold value.
第１図は本発明の原理を説明するための要部構成図で
ある。FIG. 1 is a main part configuration diagram for explaining the principle of the present invention.
同図に示すように本発明は、従来から具備する通常の
ゲート電極を第１ゲート電極G1とし、チャネル部の反対
側に絶縁層を介して形成した第２ゲート電極G2を配設
し、同一行に属する第２ゲート電極を共通に接続してパ
ネル端部に引き出した構成としたものである。As shown in the figure, in the present invention, the usual gate electrode conventionally provided is the first gate electrode G 1, and the second gate electrode G 2 formed on the opposite side of the channel portion with the insulating layer interposed therebetween is provided. The second gate electrodes belonging to the same row are commonly connected and led to the panel end portion.
この第２ゲート電極G2には、動作時にバイアス電圧VB
を印加する。A bias voltage V B is applied to the second gate electrode G 2 during operation.
Is applied.
上記第２ゲート電極G2へのバイアス電圧印加によっ
て、TFT1のチャネル部の電位が影響を受ける結果、TFT1
の特性は第２図に示すように変化する。The application of the bias voltage to the second gate electrode G 2 affects the potential of the channel portion of the TFT 1 as a result.
The characteristic of changes as shown in FIG.
同図にはｎチャネル型のTFTの特性例を示す。 The figure shows an example of the characteristics of an n-channel TFT.
図示したように、第２ゲート電極G2に負のバイアス電
圧VBを印加することによって、ドレイン電流−第１ゲー
ト電圧特性は正の方向に移動し、閾値電圧（図示の例で
は10-11Ａのドレイン電流となるゲート電圧）も正の方
向に移動する。また第２ゲート電極に印加するバイアス
電圧VBを正の電圧とすることにより、閾値電圧は負の方
向に移動する。As shown in the drawing, by applying the negative bias voltage V B to the second gate electrode G 2 , the drain current-first gate voltage characteristic moves in the positive direction and the threshold voltage (10 −11 in the illustrated example). The gate voltage which becomes the drain current of A) also moves in the positive direction. Further, by setting the bias voltage V B applied to the second gate electrode to a positive voltage, the threshold voltage moves in the negative direction.
これを利用し、第２ゲート電極G2へ印加するバイアス
電圧VBを制御することにより、閾値電圧を制御すること
が可能となる。この結果、従来では閾値が負の値となり
表示が行えないパネルについては、正のバイアス印加に
よって閾値を正の値にして良好な表示を行わせることが
できる。また閾値が経時変化によって負の値となる場合
にも、予め第２ゲート電極に正のバイアスを印加してお
くか、あるいはバイアス電圧VBを駆動時間に従って変え
られるようにしておくことにより、表示不良の発生を防
止できる。By utilizing this, by controlling the bias voltage V B applied to the second gate electrode G 2 , it becomes possible to control the threshold voltage. As a result, for a panel which has a negative threshold value and cannot be displayed in the related art, a positive bias can be applied to set the threshold value to a positive value and good display can be performed. In addition, even when the threshold value becomes a negative value due to a change over time, a positive bias is applied to the second gate electrode in advance, or the bias voltage V B can be changed according to the driving time to display It is possible to prevent the occurrence of defects.
第２のゲート電極G2を設け、これに所望のバイアス電
圧を印加することにより、上述した如く閾値電圧を制御
できる理由は、次のように解される。The reason why the threshold voltage can be controlled as described above by providing the second gate electrode G 2 and applying a desired bias voltage to it is understood as follows.
TFT1のスイッチング動作は、ゲート電極（本発明のTF
Tでは第１ゲート電極G1）に正電圧を印加することによ
り、動作半導体層の伝導バンドをフェルミレベルに近づ
け、キャリア電子の蓄積を生じさせ、動作半導体層を導
通状態とすることによって行う。これに裏面の第２ゲー
ト電極G2よりゲートを逆極性の負電圧を印加すると、伝
導バンドをフェルミレベルから遠ざける効果を生じ、キ
ャリア電子の蓄積を生じさせるためには、正方向のゲー
ト電圧を余分に印加することが必要となり、この結果TF
T1の閾値電圧は正の方向にシフトすることとなると考え
られる。The switching operation of TFT1 is performed by the gate electrode (TF of the present invention).
At T, by applying a positive voltage to the first gate electrode G 1 ), the conduction band of the operating semiconductor layer is brought close to the Fermi level, carrier electrons are accumulated, and the operating semiconductor layer is made conductive. When a negative voltage of reverse polarity is applied to the gate from the second gate electrode G 2 on the back surface, the effect of moving the conduction band away from the Fermi level is produced, and in order to cause accumulation of carrier electrons, a positive gate voltage is applied. It is necessary to apply an extra voltage, which results in TF
It is considered that the threshold voltage of T1 is shifted in the positive direction.
なお第１ゲート電極G1に印加される電圧は、当該TFT1
の第１ゲート電極G1が接続されているスキャンバスライ
ンSBの電位VSCAN,nとドレイン電極Ｄが接続されている
次位のスキャンバスラインSB′の電位VSCAN,n+1との差
電圧となる。The voltage applied to the first gate electrode G 1 is
Difference between the potential V SCAN, n + 1 of the voltage V SCAN in the first scan bus line SB to the gate electrode G 1 is connected, n and the drain electrode D is connected to the next order is scan bus lines SB ' It becomes a voltage.
以下本発明の実施例を図面により説明する。 Embodiments of the present invention will be described below with reference to the drawings.
第３図に本発明の第１の実施例を示す。透明基板３上
に第２ゲート電極（例えばCr,Ti,Ni/Cr膜等からなり、
厚さ約1000Å）Ｇ′を形成した後、絶縁膜（例えばSiN,
SiO2膜等からなり、厚さ約2000Å）４を全面に被覆し、
その上層にドレイン電極Ｄ及びソース電極S,動作半導体
層5,ゲート絶縁膜6,及び第１ゲート電極Ｇを形成して、
スタガード型のTFTを形成したものである。FIG. 3 shows a first embodiment of the present invention. A second gate electrode (for example, made of Cr, Ti, Ni / Cr film, etc. on the transparent substrate 3,
After forming G'with a thickness of about 1000Å), an insulating film (eg SiN,
It is made of SiO 2 film, etc.
Forming the drain electrode D and the source electrode S, the operating semiconductor layer 5, the gate insulating film 6, and the first gate electrode G on the upper layer,
This is a staggered TFT.
第４図は本発明の第２の実施例を示す図で、本発明を
逆スタガード型に適用した例である。透明基板３上に、
第１ゲート電極G,ゲート絶縁膜6,動作半導体層5,ドレイ
ン電極Ｄ及びソース電極Ｓを形成して、逆スタガード型
のTFTを構成した後、TFTのチャネル領域を被覆するよう
に選択形成された絶縁膜（SiO2,SiN膜等，からなり、厚
さ約2000Å）４の上に、ソース電極Ｓ及びドレイン電極
Ｄが絶縁されるようにして、第２ゲート電極（Al,Ti膜
等からなり、厚さ約1000Å）Ｇ′を形成する。FIG. 4 is a diagram showing a second embodiment of the present invention, which is an example in which the present invention is applied to an inverted staggered type. On the transparent substrate 3,
After forming the first gate electrode G, the gate insulating film 6, the operating semiconductor layer 5, the drain electrode D and the source electrode S to form an inverted staggered TFT, the TFT is selectively formed so as to cover the channel region of the TFT. The second gate electrode (Al, Ti film, etc.) is formed on the insulating film (SiO 2 , SiN film, etc., having a thickness of about 2000 Å) 4 so that the source electrode S and the drain electrode D are insulated. And a thickness of about 1000Å) G'is formed.
第1,第２の実施例のどちらの場合も第２ゲート電極
Ｇ′として不透明の金属膜を用いているので、チャネル
部への光の照射を防ぐ光シールド層を兼ね、従って光電
流によってTFTのオフ電流が上昇することを同時に防止
できる。In both cases of the first and second embodiments, since the opaque metal film is used as the second gate electrode G ', it also serves as a light shield layer for preventing the irradiation of light to the channel portion, and therefore the TFT is affected by the photocurrent. At the same time, it is possible to prevent the off-current from rising.
これら第１〜第２の実施例のいずれの場合も、第２ゲ
ート電極Ｇ′に印加するバイアス電圧VBを３〜15Vの範
囲で制御することにより、閾値電圧を１〜5Vの範囲で制
御することが可能であった。従って閾値電圧が低すぎる
場合や、経時変化を生じた場合においても、第２ゲート
電圧に適当なバイアス電圧を印加することによって、正
常な表示を得ることができ、製造歩留が向上するととも
に、安定に動作させることが可能となる。In any of these cases the first and second embodiment, by controlling the bias voltage V B to be applied to the second gate electrode G 'in the range of 3～15V, control the threshold voltage in the range of 1~5V It was possible to Therefore, even if the threshold voltage is too low or changes over time, by applying an appropriate bias voltage to the second gate voltage, it is possible to obtain normal display and improve the manufacturing yield. It becomes possible to operate stably.
以上の説明から明らかなように本発明によれば、ゲー
ト接続対向マトリクス方式パネルにおいて、これまで不
良原因となっていたTFTの閾値電圧不良の発生を、第２
ゲート電極の電位を電気的に制御することによってなく
すことができ、歩留の大幅な向上が図れる。またTFTの
閾値の経時変化による表示不良の発生も防止することが
でき、素子寿命の大幅な改善を図ることができる。As is apparent from the above description, according to the present invention, in the gate connection opposed matrix system panel, the occurrence of the TFT threshold voltage defect, which has been the cause of the defect, is
It can be eliminated by electrically controlling the potential of the gate electrode, and the yield can be significantly improved. Further, it is possible to prevent the occurrence of display defects due to the change in the threshold value of the TFT over time, and it is possible to significantly improve the life of the element.
第１図は本発明の要部構成説明図、 第２図は本発明の効果を示す特性図、 第３図は本発明の第１の実施例を示す図、 第４図は本発明の第２の実施例を示す図、 第５図は従来のゲート接続方式の表示パネルの等価回路
図、 第６図は上記ゲート接続方式表示パネルの構成を示す斜
視図である。 図において、１はTFT（薄膜トランジスタ）、3,3′は透
明基板、４は絶縁膜、５は動作半導体層、６はゲート絶
縁膜、Ｄはドレイン電極、Ｓはソース電極、G,G′は第
１および第２ゲート電極、Ｅは表示電極、LCは表示セル
を示す。FIG. 1 is an explanatory view of the essential configuration of the present invention, FIG. 2 is a characteristic diagram showing the effect of the present invention, FIG. 3 is a diagram showing a first embodiment of the present invention, and FIG. 4 is a diagram showing the present invention. FIG. 5 is an equivalent circuit diagram of a conventional gate connection type display panel, and FIG. 6 is a perspective view showing the configuration of the gate connection type display panel. In the figure, 1 is a TFT (thin film transistor), 3 and 3 ′ are transparent substrates, 4 is an insulating film, 5 is an operating semiconductor layer, 6 is a gate insulating film, D is a drain electrode, S is a source electrode, and G and G ′ are First and second gate electrodes, E is a display electrode, and LC is a display cell.
フロントページの続き (72)発明者 井上 淳 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (56)参考文献 特開 昭63−68818（ＪＰ，Ａ) 実開 昭57−88945（ＪＰ，Ｕ)Continued Front Page (72) Inventor Atsushi Inoue 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (56) U)
Claims (2)
明基板（3,3′）と、該一対の透明基板の一方（３）の
表面に、平行に配列された複数本のスキャンバスライン
（SB,SB′）と、マトリクス状に配置された複数個の表
示電極（Ｅ）と、該表示電極に対応する薄膜トランジス
タ（１）の第１ゲート電極（Ｇ）と，該第１ゲート電極
にゲート絶縁膜，動作半導体層を介して対向配置された
ソース電極（Ｓ），ドレイン電極（Ｄ）が、それぞれ当
該薄膜トランジスタに対応するスキャンバスライン（S
B），対応する表示電極（Ｅ），隣のスキャンバスライ
ン（SB′）に接続され、他方の透明基板（３′）の表面
に複数本のデータバスライン（DB）が配設された構成を
有する薄膜トランジスタマトリクスにおいて、 前記ソース電極（Ｓ）およびドレイン電極（Ｄ）の前記
第１ゲート電極（Ｇ）と反対側に、絶縁膜（４）を介し
て配設された第２ゲート電極（Ｇ′）を具備することを
特徴とするアクティブマトリクス型表示装置。1. A pair of transparent substrates (3, 3 ') opposed to each other across a display medium, and a plurality of scan buses arranged in parallel on the surface of one (3) of the pair of transparent substrates. Lines (SB, SB '), a plurality of display electrodes (E) arranged in a matrix, a first gate electrode (G) of the thin film transistor (1) corresponding to the display electrodes, and the first gate electrode A gate electrode and a source electrode (S) and a drain electrode (D), which are arranged to face each other with a gate insulating film and an operating semiconductor layer interposed therebetween, respectively correspond to the scan bus line (S) corresponding to the thin film transistor.
B), corresponding display electrode (E), connected to the adjacent scan bus line (SB '), and a plurality of data bus lines (DB) arranged on the surface of the other transparent substrate (3') In the thin film transistor matrix having, the second gate electrode (G) provided on the opposite side of the source electrode (S) and the drain electrode (D) from the first gate electrode (G) via an insulating film (4). ′) An active matrix type display device characterized by comprising:
膜からなり、薄膜トランジスタ（１）の光シールド層を
兼ねることを特徴とする特許請求の範囲第１項記載のア
クティブマトリクス型表示装置。2. The active matrix type display device according to claim 1, wherein the second gate electrode (G ') is made of an opaque conductive film and also serves as a light shield layer of the thin film transistor (1). .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25272787A JP2503030B2 (en) | 1987-10-06 | 1987-10-06 | Active matrix display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25272787A JP2503030B2 (en) | 1987-10-06 | 1987-10-06 | Active matrix display device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0194670A JPH0194670A (en) | 1989-04-13 |
| JP2503030B2 true JP2503030B2 (en) | 1996-06-05 |
Family
ID=17241422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25272787A Expired - Lifetime JP2503030B2 (en) | 1987-10-06 | 1987-10-06 | Active matrix display device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2503030B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140137729A (en) * | 2013-05-23 | 2014-12-03 | 엘지디스플레이 주식회사 | Liquid crystal display device and method for driving the same |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02156676A (en) * | 1988-12-09 | 1990-06-15 | Fuji Xerox Co Ltd | Thin film semiconductor device |
| US5053347A (en) * | 1989-08-03 | 1991-10-01 | Industrial Technology Research Institute | Amorphous silicon thin film transistor with a depletion gate |
| JP2776083B2 (en) * | 1991-08-23 | 1998-07-16 | 日本電気株式会社 | Liquid crystal display device and manufacturing method thereof |
| JP4723787B2 (en) * | 2002-07-09 | 2011-07-13 | シャープ株式会社 | FIELD EFFECT TRANSISTOR, MANUFACTURING METHOD THEREOF, AND IMAGE DISPLAY DEVICE |
| KR101080356B1 (en) | 2003-10-13 | 2011-11-04 | 삼성전자주식회사 | Thin film transistor, thin film transistor array panel, and display device |
| JP4155317B2 (en) * | 2006-07-11 | 2008-09-24 | セイコーエプソン株式会社 | Electro-optical device and electronic apparatus including the same |
| KR101476817B1 (en) | 2009-07-03 | 2014-12-26 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Display device including transistor and manufacturing method thereof |
| TWI560508B (en) * | 2015-11-11 | 2016-12-01 | Au Optronics Corp | Thin film transistor and operating method thereof |
| CN106920768A (en) * | 2015-12-24 | 2017-07-04 | 中微半导体设备(上海)有限公司 | Multi-region active-matrix temperature control system and temperature control method and its applicable electrostatic chuck and plasma treatment appts |
-
1987
- 1987-10-06 JP JP25272787A patent/JP2503030B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140137729A (en) * | 2013-05-23 | 2014-12-03 | 엘지디스플레이 주식회사 | Liquid crystal display device and method for driving the same |
| KR102023949B1 (en) * | 2013-05-23 | 2019-09-23 | 엘지디스플레이 주식회사 | Liquid crystal display device and method for driving the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0194670A (en) | 1989-04-13 |
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