KR102023949B1 - Liquid crystal display device and method for driving the same - Google Patents

Liquid crystal display device and method for driving the same Download PDF

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Publication number
KR102023949B1
KR102023949B1 KR1020130058583A KR20130058583A KR102023949B1 KR 102023949 B1 KR102023949 B1 KR 102023949B1 KR 1020130058583 A KR1020130058583 A KR 1020130058583A KR 20130058583 A KR20130058583 A KR 20130058583A KR 102023949 B1 KR102023949 B1 KR 102023949B1
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South Korea
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gate
compensation
liquid crystal
control signal
voltage
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KR1020130058583A
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Korean (ko)
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KR20140137729A (en
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황정태
공남용
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엘지디스플레이 주식회사
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • GPHYSICS
    • G02OPTICS
    • G02FDEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1345Conductors connecting electrodes to cell terminals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/08Details of timing specific for flat panels, other than clock recovery

Abstract

The present invention controls the threshold voltage of a thin film transistor (TFT) for each pixel during an initial period of time when an image is displayed on a liquid crystal panel, thereby allowing each pixel to provide uniform luminance, thereby further improving display image quality. And a driving method comprising: a liquid crystal panel having a double gate type TFT (Thin Film Transistor) having a first and a second gate electrode in each of the plurality of pixel regions and a liquid crystal capacitor; At least one gate driver for driving gate lines of the liquid crystal panel; A plurality of data drivers for driving data lines of the liquid crystal panel; A timing controller which modulates and outputs a compensation control signal in units of at least one frame period so as to gradually control threshold voltages of the double gate type TFTs provided in each pixel region during a preset initial image display period; And varying a level of a gate compensation voltage in response to a compensation control signal modulated in units of at least one frame period, and using the compensation gate lines formed in the liquid crystal panel to the second gate electrode of each of the double gate type TFTs. And a power supply for supplying a gate compensation voltage having a variable voltage level.

Description

Liquid crystal display and its driving method {LIQUID CRYSTAL DISPLAY DEVICE AND METHOD FOR DRIVING THE SAME}
The present invention controls the threshold voltage of a thin film transistor (TFT) for each pixel during an initial period of time when an image is displayed on a liquid crystal panel, thereby allowing each pixel to provide uniform luminance, thereby further improving display image quality. And a driving method thereof.
The liquid crystal display displays an image by using electrical and optical characteristics of the liquid crystal. Liquid crystals have different anisotropy in refractive index, dielectric constant, etc. according to molecular long axis direction and short axis direction, and can easily adjust molecular arrangement and optical properties. The liquid crystal display using the same displays an image by adjusting the light transmittance through the polarizing plate by changing the arrangement direction of the liquid crystal molecules according to the size of the electric field.
The liquid crystal display includes a liquid crystal panel in which a plurality of pixels are arranged in a matrix, a gate driver driving a gate line of the liquid crystal panel, a data driver driving a data line of the liquid crystal panel, and the like.
Each pixel arranged in the liquid crystal panel includes a thin film transistor (TFT) and a liquid crystal capacitor connected to the TFT. The liquid crystal capacitor is composed of a pixel electrode connected to the TFT, and a common electrode arranged with the pixel electrode and the liquid crystal interposed therebetween. Such a liquid crystal capacitor charges a difference voltage with a common voltage according to an image display voltage supplied to a pixel electrode through a TFT, and adjusts light transmittance by varying an arrangement of liquid crystal molecules according to the difference voltage.
However, in the conventional liquid crystal display device, in particular, the liquid crystal panel has a characteristic difference such as the threshold voltage (Vth) and the mobility (mobility) of the TFT for each pixel due to process variation, and the amount of current driving the liquid crystal is changed. The luminance deviation occurred between the pixels. In general, the difference in the characteristics of the initial driving TFTs causes stains or patterns on the screen, and the characteristic differences due to deterioration of the TFTs generated while driving the liquid crystals reduce the lifespan of the liquid crystal panel or cause afterimages. .
The present invention is to solve the above problems, by controlling the threshold voltage of the TFT for each pixel during the initial period that the image is displayed on the liquid crystal panel, so that each pixel to provide a uniform brightness irrespective of the threshold voltage of the TFT Accordingly, an object of the present invention is to provide a liquid crystal display and a driving method thereof, which can further improve display image quality.
A liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object includes a double gate type TFT (Tin Film Transistor) having a first and a second gate electrode in each of a plurality of pixel regions and a liquid crystal capacitor. A liquid crystal panel; At least one gate driver for driving gate lines of the liquid crystal panel; A plurality of data drivers for driving data lines of the liquid crystal panel; A timing controller which modulates and outputs a compensation control signal in units of at least one frame period so as to gradually control threshold voltages of the double gate type TFTs provided in each pixel region during a preset initial image display period; And varying a level of a gate compensation voltage in response to a compensation control signal modulated in units of at least one frame period, and using the compensation gate lines formed in the liquid crystal panel to the second gate electrode of each of the double gate type TFTs. And a power supply for supplying a gate compensation voltage having a variable voltage level.
The timing controller counts the image display period of the liquid crystal panel in at least one frame unit by counting at least one of synchronization signals from the outside, and controls the threshold voltage of the double gate type TFTs in preset initial frame periods. A gate voltage controller which modulates and generates the compensation control signal in steps of at least one frame period so as to be generated and outputs the data control signal generator, which generates and outputs a data control signal using at least one of the synchronization signals And a gate control signal generator configured to generate and output a gate control signal using at least one of the synchronization signals.
The compensation control signal is a gate compensation voltage level supplied to the compensation gate line and the second gate electrode of the double gate type TFTs in order to control the threshold voltages of the double gate type TFTs provided in each pixel region for each preset frame period. It is characterized in that the digital control signal of a plurality of bits set.
The gate voltage controller generates and outputs the compensation control signal such that the gate compensation voltage is supplied at a predetermined voltage level for a plurality of preset frame periods starting from the first frame in which the image is displayed. After output for a plurality of preset frame periods, the compensation control signal is modulated and output such that the level of the gate compensation voltage is gradually changed in units of at least one frame and finally floats to a 0V level. .
The power supply unit generates and outputs a common voltage, a gate high and low voltage, a positive DC drive voltage, a power supply voltage, and a plurality of reference gamma voltages by modulating a voltage level of an input power supplied from an external source into a plurality of preset voltage levels. The gate driving voltage generation unit and the gate compensation voltage level of the liquid crystal panel after the gate compensation voltage level is changed in response to at least one frame period in response to the compensation control signal inputted in units of at least one frame period. And a top gate voltage generator for supplying to
In addition, a method of driving a liquid crystal display according to an exemplary embodiment of the present invention for achieving the above object includes a double gate type TFT (Thin Film Transistor) having first and second gate electrodes in each of a plurality of pixel regions; A driving method of a liquid crystal display for displaying an image through a liquid crystal panel provided with a liquid crystal capacitor, wherein the threshold voltages of the double gate type TFTs provided in each pixel region can be gradually controlled during a predetermined initial image display period. Modulating and outputting a compensation control signal in at least one frame period; And varying a level of a gate compensation voltage in response to a compensation control signal modulated in units of at least one frame period, and using the compensation gate lines formed in the liquid crystal panel to the second gate electrode of each of the double gate type TFTs. And supplying a gate compensation voltage having a variable voltage level.
The modulating and outputting the compensation control signal may include counting at least one image display period of the liquid crystal panel in at least one frame unit by counting at least one signal from an external synchronization signal. And modulating and generating the compensation control signal in steps of at least one frame period so that the threshold voltages of the gate type TFTs can be controlled.
The compensation control signal is a gate compensation voltage level supplied to the compensation gate line and the second gate electrode of the double gate type TFTs in order to control the threshold voltages of the double gate type TFTs provided in each pixel region for each preset frame period. It is characterized in that the digital control signal of a plurality of bits set.
The step of modulating and generating the compensation control signal may include generating the compensation control signal so that the gate compensation voltage is supplied at a predetermined voltage level for a plurality of preset frame periods from the first frame at which the image is displayed. And generating and outputting the compensation control signal during a plurality of preset frame periods so that the level of the gate compensation voltage is gradually varied in units of at least one frame so that it is finally floated to 0V level. And modulating and outputting the compensation control signal.
The generating and supplying the level of the compensation voltage by varying the level of the compensation voltage may be performed by varying the gate compensation voltage level by at least one frame period in response to the compensation control signal input after being varied in at least one frame period. And supplying to the compensation gate lines of the panel.
The present invention configures the TFT of each pixel as a double gate type TFT having first and second gate electrodes, and controls the threshold voltage of the TFT for each pixel during the initial period in which an image is displayed on the liquid crystal panel. Accordingly, the present invention can further improve display image quality by allowing each pixel to provide uniform luminance irrespective of the threshold voltage of the TFT.
1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
2A and 2B are pixel configuration diagrams illustrating structures of pixels illustrated in FIG. 1, respectively.
3 is a cross-sectional view showing a cross-sectional structure of the double gate type TFT shown in FIGS. 1 and 2A and 2B, respectively.
4 is a configuration diagram illustrating in detail the timing controller illustrated in FIG. 1.
5 is a configuration diagram showing in detail the power supply unit shown in FIG.
6 is a graph showing current driving characteristics of the double gate type TFT shown in FIGS. 2A and 2B.
Hereinafter, a liquid crystal display and a driving method thereof according to an exemplary embodiment of the present invention having the above characteristics will be described in detail with reference to the accompanying drawings.
1 is a block diagram illustrating a liquid crystal display according to an exemplary embodiment of the present invention.
1 includes a liquid crystal panel 2 including a double gate type TFT (Thin Film Transistor) having first and second gate electrodes in each of a plurality of pixel regions and a liquid crystal capacitor; At least one gate driver 3 driving the gate lines GL1 to GLn of the liquid crystal panel 2; A plurality of data drivers 4 for driving the data lines DL1 to DLm of the liquid crystal panel 2; In order to control the threshold voltages of the double gate type TFTs provided in the respective pixel areas during the preset initial image display period, the compensation control signal is modulated and output in units of at least one frame period, and each gate and data driver ( A timing controller 18 for controlling 3,4; And a second gate of each of the double gate type TFTs through the compensation gate lines CL formed in the liquid crystal panel 2 in response to a compensation control signal modulated in at least one frame period. And a power supply 9 for supplying a gate compensation voltage having a variable voltage level to an electrode.
The liquid crystal panel 2 is a liquid crystal capacitor connected to a double gate type TFT and a double gate type TFT respectively formed in each pixel area defined by the plurality of gate lines GL1 to GLn and the plurality of data lines DL1 to DLm. (Clc). The liquid crystal capacitor Clc is composed of a pixel electrode connected to the double gate type TFT, a common electrode disposed with the pixel electrode and the liquid crystal interposed therebetween. The liquid crystal capacitor Clc charges the difference voltage with the common voltage Vcom according to the image display voltage supplied to the pixel electrode, and adjusts the light transmittance by varying the arrangement of the liquid crystal molecules according to the difference voltage. . In this case, the storage capacitor Cst may be formed by overlapping the pixel electrode with the storage line and the insulating layer interposed therebetween, and a parasitic capacitor Cgs may be further formed between the source electrode and the gate line GL of the double gate type TFT. .
2A and 2B are pixel configuration diagrams illustrating structures of pixels illustrated in FIG. 1, respectively. 3 is a cross-sectional view showing a cross-sectional structure of the double gate type TFT shown in FIGS. 1, 2A, and 2B, respectively.
2A and 2B, the first gate electrode g1 of the double gate type TFT provided in each pixel region is connected to the gate line GL1, and the source electrode s1 is the data line DL1. Are connected to each. The drain electrode s2 is connected to the pixel electrode of the liquid crystal capacitor Clc. The second gate electrode g2 of the double gate type TFT is configured to face the first gate electrode g1, and the second gate electrode g2 is connected to the compensation gate lines CL, respectively, to compensate for the compensation gate line CL. Are supplied with the gate compensation voltage. Meanwhile, as illustrated in FIG. 2A, a compensation capacitor C may be further formed between the second gate electrode g2 and the compensation gate line CL. The compensation capacitor C is charged to the second gate electrode g2 for a predetermined period by charging the gate compensation voltage supplied through the compensation gate line CL according to its capacity.
As shown in FIG. 3, the double gate type TFT is formed on the substrate sb1 and is formed on the first gate electrode g1 and the gate formed on the first gate electrode g1 connected to each gate line GL. A drain electrode formed on the insulating film b1, the gate insulating film b1 and spaced apart from the source electrode s1 and the first electrode s1 connected to each data line DL, and connected to each pixel electrode. (s2), the semiconductor layer o1 forming a channel between the source and drain electrodes s1 and s2, the etch stopper c1 formed on the semiconductor layer o1 to protect the semiconductor layer o1, the source and An interlayer insulating film d1 covering the entire surface of the substrate sb1 including the drain electrodes s1 and s2 and the etch stopper c1, and formed on the interlayer insulating film d1 so as to face the first gate electrode g1. The threshold voltage Vth of the double gate type TFT is controlled according to the gate compensation voltage level applied through CL). The consists of a second gate electrode (g2).
In the double gate type TFT, the threshold voltage Vth is shifted according to the gate compensation voltage applied to the second gate electrode g2. For example, if the gate compensation voltage applied to the second gate electrode g2 is + 1V, the threshold voltage Vth of the double gate type TFT is shifted by -1V. If the gate compensation voltage applied to the second gate electrode g2 is -1V, the threshold voltage Vth of the double gate type TFT is shifted by + 1V.
The present invention compensates the threshold voltage (Vth) of the double gate type TFT in the initial image display period in which the image is displayed by using the characteristics of the double gate type TFT as described above. That is, the threshold voltage Vth of the double gate TFT is supplied to the second gate electrode g2 of the double gate TFT by varying the gate compensation voltage in at least one frame period during the initial image display period during which the image is displayed. To compensate. Here, the structure of the double gate type TFT according to the present invention is not limited to the form as shown in FIG. That is, the double gate type TFT of the present invention can be applied to any structure as long as it has two gate electrodes facing each other to control the threshold voltage Vth.
Each of the plurality of data drivers 4 may be configured as an integrated circuit, and receives the aligned image data and data control signals from the timing controller 18. In particular, each data driver 4 is mounted on a data circuit film 6 provided between the separate source printed circuit boards 8 so that the corresponding data lines DL1 to the display area corresponding to its position are provided. DLm) is driven respectively. Here, the data circuit film 6 may be a tape carrier package (TCP) film or a chip on flexible printed circuit (COF) film.
The data drivers 4 all control the data control signals, for example, the source start signal SSP, the source shift clock SSC, and the source output enable signal from the timing controller 18 at the same timing. Source Output Enable (SOE) signal. Then, at the same timing, the data arranged from the timing controller 18 is converted into an analog voltage, that is, a data voltage. At this time, each data driver 4 selects a gamma voltage corresponding to the gray level value of the data arranged by the timing controller 18 and supplies the selected gamma voltage to each data line DL1 to DLm as an image display voltage.
The gate driver 3 may be configured as an integrated circuit and is provided at one side of the liquid crystal panel 2 to sequentially drive the gate lines GL1 to GLn. The gate driver 3 is mounted in each of the non-display area and the gate circuit film 5 of the liquid crystal panel 2 and electrically connected to the liquid crystal panel 2. The gate driver 3 sequentially supplies scan pulses having a gate high voltage level to the gate lines GL1 to GLn in response to a gate control signal from the timing controller 18. The gate low voltage is supplied for the remaining period during which the scan pulse is not supplied.
The timing controller 18 is provided on a separate control printed circuit board 12 to control the plurality of data drivers 4 and the gate driver 3 according to image data and a plurality of synchronization signals from the outside. For example, when the timing controller 18 is provided in the control printed circuit board 12, the timing controller 18 may be connected to the plurality of connectors 14, the cables 16, the source printed circuit board, and the like, respectively. Supply gate and data control signals. The timing controller 18 aligns image data input from an external system or the like so as to be suitable for driving the liquid crystal panel 2. Each data driver 4 and the gate driver 3 are controlled according to the image data and the plurality of synchronization signals. Specifically, the timing controller 18 arranges the image data input from the outside to be suitable for driving the liquid crystal panel 2 and supplies the data data to each data driver 4. The gate control signal and the data control signal are generated using at least one of a synchronization signal input from an external device, that is, a dot clock, a data enable signal, a horizontal and a vertical synchronization signal, and the gate driver 3 and each data driver are generated. It is supplied to (4), respectively.
In addition, the timing controller 18 steps the compensation control signal in steps of at least one frame period in advance so that the threshold voltage Vth of the double gate type TFTs provided in each pixel area of the liquid crystal panel 2 can be controlled. It is generated by modulating and supplying it to the power supply unit 9. Specifically, the timing controller 18 counts the image display period of the liquid crystal panel 2 in at least one frame unit and modulates the compensation control signal in at least one frame period. Then, the stepwise modulated compensation control signal is supplied to the power supply unit (9). The configuration and driving method of the timing controller 18 of the present invention will be described in more detail with reference to the accompanying drawings.
The power supply unit 9 modulates the voltage level of the input power source Vin supplied from the outside into a plurality of preset voltage levels, so that the common voltage, the positive DC drive voltage, the gate high and low voltages, the reference gamma voltage of the multiple levels, and the like are provided. Are generated and supplied to the liquid crystal panel 2 and the gate and data drivers 3 and 4, respectively. In addition, the power supply unit 9 generates the gate compensation voltage level by varying the level of the gate compensation voltage in response to the compensation control signal that is gradually changed in units of at least one frame period. The gate compensation voltage having a variable voltage level is supplied to the second gate electrode of each double gate type TFT by supplying it to the compensation gate lines CL of the liquid crystal panel 2. The configuration and driving method of the power supply unit 9 of the present invention will also be described in more detail with reference to the accompanying drawings.
4 is a configuration diagram illustrating in detail the timing controller illustrated in FIG. 1.
The timing controller 18 shown in FIG. 4 aligns the image data RGB input from the outside with at least one of the synchronization signals DCLK, Hsync, Vsync, and DE according to driving of the liquid crystal panel 2. Counting the image display period of the liquid crystal panel 2 in at least one frame unit by counting at least one of the image processor 22 and the synchronization signals DCLK, Hsync, Vsync, and DE, and preset initial frame periods. A gate voltage controller 21 for generating and outputting a stepwise modulated compensation control signal in units of at least one frame period so that the threshold voltage Vth of the double gate type TFTs can be controlled, and the synchronization signals DCLK, Hsync, and Vsync. Using a data control signal generator 23 for generating and outputting a data control signal DCS using at least one of the signals DE, and at least one of the synchronization signals DCLK, Hsync, Vsync, and DE. The gate control signal GCS And a resistance and the gate control signal generating unit 24 for outputting.
The image processor 22 aligns the image data RGB input from the outside with at least one of the synchronization signals DCLK, Hsync, Vsync, and DE according to the driving of the liquid crystal panel 2, and arranges the image data. (Data) is supplied to the data driver 4.
The data control signal generator 23 uses at least one of the input synchronization signals DCLK, DE, Hsync, and Vsync, for example, data using the data enable signal DE and the vertical synchronization signal Vsync. Generate and output data control signals for controlling the drive timing of the driver 4.
The gate control signal generator 24 may include a gate using at least one of the input synchronization signals DCLK, DE, Hsync, and Vsync, for example, a data enable signal DE and a horizontal synchronization signal Hsync. Gate control signals for controlling the driving timing of the driver 6 are generated and output.
The gate voltage controller 21 counts at least one of the synchronization signals DCLK, Hsync, Vsync, and DE to count the image display period of the liquid crystal panel 2 in at least one frame unit. The compensation control signal is modulated in steps of at least one frame period so that the threshold voltage Vth of the double gate type TFTs can be controlled in predetermined initial frame periods. The compensation control signal TCS modulated in steps of at least one frame period is supplied to the power supply unit 9. In this case, the compensation control signal TCS is configured to control the threshold voltage Vth of the double gate type TFTs provided in each pixel region step by step for a predetermined frame period, and the second of the compensation gate line CL and the double gate type TFTs. A digital control signal of a plurality of bits which sets the gate compensation voltage level supplied to the gate electrode g2.
In order to stably control the threshold voltage Vth of the double gate type TFTs in the initial driving period after the image starts to be displayed, the gate voltage controller 21 presets a plurality of frame periods from the first frame where the image starts to be displayed. While generating and outputting a compensation control signal TCS so that the gate compensation voltage is supplied at a predetermined voltage level. After the compensation control signal TCS is output for a plurality of preset frame periods, the level of the gate compensation voltage is varied in steps of at least one frame so that the compensation control signal TCS is floated to and maintained at a 0V level. Modulate and output.
More specifically, the gate voltage controller 21 may have a gate compensation voltage of any one of -5V to -20V (for example, -10V) during a plurality of preset frame periods starting from the first frame at which the image is displayed. Generates and outputs a compensation control signal TCS to be supplied to After the compensation control signal TCS is output for a plurality of preset frame periods, the level of the gate compensation voltage is gradually changed in at least one frame unit (for example, every frame unit) (-10V->-). 9V-> -8V, ... -1V) and modulates the compensation control signal TCS so as to remain floating at the 0V level.
FIG. 5 is a configuration diagram illustrating in detail the power supply unit illustrated in FIG. 1.
The power supply unit 9 shown in FIG. 5 modulates the voltage level of the input power Vin supplied from the outside into a plurality of preset voltage levels, so that the common voltage Vcom, the gate high and low voltages VGH and VGL, The panel driving voltage generator 31 generating and outputting a positive DC driving voltage VDD, a power supply voltage VCC, and a plurality of reference gamma voltages, and the compensation control signal that is variable and input in units of at least one frame period. In response to the gate compensation voltage level is varied in at least one frame period, and then supplied to the compensation gate lines CL of the liquid crystal panel 2 to the second gate electrode of each of the double gate type TFTs. A top gate voltage generator 32 is provided to supply a gate compensation voltage VTG having a variable voltage level.
The top gate voltage generator 32 may include a compensation control signal TCS that is changed in units of at least one frame period, for example, a gate compensation voltage of -5V or more for a plurality of preset frame periods from the first frame at which the image is displayed. When the compensation control signal TCS set to be supplied at any level of -20V (for example, -10V) is input, any one of -5V to -20V during a plurality of frame periods in response to the compensation control signal TCS is input. The gate compensation voltage VTG is generated at a level (eg, −10 V) and supplied to the compensation gate lines CL. In addition, the level of the gate compensation voltage is variable (-10V-> -9V-> -8V, ... -1V) in at least one frame unit (for example, every frame unit), and finally, may be floated to 0V. When the compensation control signal TCS is modulated and input, the level of the gate compensation voltage VTG is changed in at least one frame unit (for example, every frame) in response to the modulated input compensation control signal TCS. (-10V-> -9V-> -8V, ... -1V) to output and maintain the gate compensation voltage (VTG) at 0V finally.
FIG. 6 is a graph showing current driving characteristics of the double gate type TFT shown in FIGS. 2A and 2B.
As illustrated in FIG. 6, the double gate type TFT has a characteristic that the threshold voltage Vth is shifted according to the level of the gate compensation voltage VTG applied to the second gate electrode g2. Accordingly, when the gate compensation voltage VTG applied to the second gate electrode g2 is -10V, the threshold voltage Vth of the double gate type TFT is shifted by + 10V. When the gate compensation voltage VTG applied to the second gate electrode g2 is -2V, the threshold voltage Vth of the double gate type TFT DT is shifted by + 2V.
According to an exemplary embodiment of the present invention, the gate compensation voltage VTG is used to control the threshold voltage Vth at the initial stage of displaying an image on the second gate electrode g2 of the double gate TFT by using the driving characteristics of the double gate TFT as described above. ) And apply it.
In particular, the gate voltage controller 21 compensates the gate compensation voltage to be supplied at any level (eg, -10V) from -5V to -20V during a plurality of preset frame periods from the first frame at which the image is displayed. Generate and output a control signal TCS and vary the level of the gate compensation voltage in at least one frame (e.g., every frame) (-10V-> -9V-> -8V, ... -1V). Finally, the compensation control signal TCS may be modulated and output to be finally floated to 0V.
In this case, the top gate voltage generator 32 may perform the -5V to -20V during the plurality of frame periods in response to the compensation control signal TCS input during the plurality of preset frame periods from the first frame at which the image is displayed. The gate compensation voltage VTG is generated at one level (eg, −10V) and supplied to the compensation gate lines CL. In addition, the level of the gate compensation voltage is variable (-10V-> -9V-> -8V, ... -1V) in at least one frame unit (for example, every frame unit), and finally, may be floated to 0V. When the compensation control signal TCS is modulated and input, the level of the gate compensation voltage VTG is changed in at least one frame unit (for example, every frame) in response to the modulated input compensation control signal TCS. (-10V-> -9V-> -8V, ... -1V) to output and maintain the gate compensation voltage (VTG) at 0V finally. Accordingly, the liquid crystal display device of the present invention can further improve the display image quality by allowing each pixel to provide uniform luminance irrespective of the threshold voltage of the TFT.
The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.
2: liquid crystal panel 3: gate driver
4: data driver 18: timing controller
21: gate voltage controller 22: image processor
23: data control signal generator 24: gate control signal generator
31: panel driving voltage generator 32: top gate voltage generator

Claims (10)

  1. A liquid crystal panel having a double gate type TFT (Thin Film Transistor) having first and second gate electrodes in each of the plurality of pixel regions and a liquid crystal capacitor;
    At least one gate driver for driving gate lines of the liquid crystal panel;
    A plurality of data drivers for driving data lines of the liquid crystal panel;
    A timing controller modulating and outputting a compensation control signal in units of at least one frame period so as to control stepwise the threshold voltages of the double gate type TFTs provided in the pixel region during a preset initial image display period; And
    Generated by varying a level of a gate compensation voltage in response to a compensation control signal modulated in units of at least one frame period, and a voltage level to a second gate electrode of each of the double gate type TFTs through compensation gate lines formed in the liquid crystal panel And a power supply for supplying the variable gate compensation voltage.
  2. The method of claim 1,
    The timing controller is
    Counting the image display period of the liquid crystal panel in at least one frame unit by counting at least one of the synchronization signals from the outside, and at least the threshold voltages of the double gate type TFTs can be controlled in preset initial frame periods. A gate voltage controller which modulates and generates and compensates the compensation control signal in units of one frame period;
    A data control signal generator for generating and outputting a data control signal using at least one of the synchronization signals;
    And a gate control signal generator configured to generate and output a gate control signal using at least one of the synchronization signals.
  3. The method of claim 2,
    The compensation control signal is
    In order to control the threshold voltages of the double gate type TFTs provided in each pixel region step by step for a predetermined frame period, a plurality of bits set a level of a gate compensation voltage supplied to the compensation gate line and the second gate electrode of the double gate type TFTs. And a digital control signal.
  4. The method of claim 3, wherein
    The gate voltage controller
    Generating and outputting the compensation control signal such that the gate compensation voltage is supplied at a predetermined voltage level for a plurality of preset frame periods from the first frame at which the image is displayed;
    After the compensation control signal is output for a plurality of preset frame periods, the compensation control signal is modulated and output so that the level of the gate compensation voltage is gradually changed and finally floated in units of at least one frame. Liquid crystal display device.
  5. The method of claim 4, wherein
    The power supply unit
    Panel driving voltage for generating and outputting common voltage, gate high and low voltage, positive polarity DC driving voltage, power supply voltage, and a plurality of reference gamma voltages by modulating the voltage level of the input power supplied from the outside into a plurality of preset voltage levels. Generating unit, and
    A top gate voltage generator configured to vary the gate compensation voltage level in at least one frame period in response to the compensation control signal input by being changed in at least one frame period and to supply the compensation gate lines of the liquid crystal panel. The liquid crystal display device characterized by the above-mentioned.
  6. A driving method of a liquid crystal display device for displaying an image through a double gate type TFT (Thin Film Transistor) having first and second gate electrodes in each of a plurality of pixel regions and a liquid crystal panel having a liquid crystal capacitor,
    Modulating and outputting a compensation control signal in units of at least one frame period so as to control stepwise the threshold voltages of the double gate type TFTs provided in the pixel region during a preset initial image display period; And
    Generated by varying a level of a gate compensation voltage in response to a compensation control signal modulated in units of at least one frame period, and a voltage level to a second gate electrode of each of the double gate type TFTs through compensation gate lines formed in the liquid crystal panel And supplying the variable gate compensation voltage.
  7. The method of claim 6,
    Modulating and outputting the compensation control signal
    Counting the image display period of the liquid crystal panel in at least one frame unit by counting at least one of the synchronization signals from the outside;
    And modulating and generating the compensation control signal in steps of at least one frame period so that the threshold voltages of the double gate type TFTs can be controlled in preset initial frame periods. Driving method.
  8. The method of claim 7, wherein
    The compensation control signal is
    In order to control the threshold voltages of the double gate type TFTs provided in each pixel region step by step for a predetermined frame period, a plurality of bits set a level of a gate compensation voltage supplied to the compensation gate line and the second gate electrode of the double gate type TFTs. And a digital control signal for driving the liquid crystal display device.
  9. The method of claim 8,
    The step of modulating and generating the compensation control signal in step
    Generating and outputting the compensation control signal such that the gate compensation voltage is supplied at a predetermined voltage level during a plurality of preset frame periods from the first frame at which the image is displayed; and
    After the compensation control signal is output for a plurality of preset frame periods, modulating and outputting the compensation control signal so that the level of the gate compensation voltage is gradually varied and finally floated in at least one frame unit. Method of driving a liquid crystal display device comprising a.
  10. The method of claim 9,
    Varying and generating and supplying the level of the compensation voltage
    And varying the gate compensation voltage level in at least one frame period in response to the compensation control signal input in a variable period of at least one frame period and supplying the compensation gate lines to the compensation gate lines of the liquid crystal panel. A method of driving a liquid crystal display device.
KR1020130058583A 2013-05-23 2013-05-23 Liquid crystal display device and method for driving the same KR102023949B1 (en)

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KR20170045428A (en) 2015-10-16 2017-04-27 삼성디스플레이 주식회사 Thin film Transistor substrate and organic light emitting display using the same
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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503030B2 (en) * 1987-10-06 1996-06-05 富士通株式会社 Active matrix display device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503030B2 (en) * 1987-10-06 1996-06-05 富士通株式会社 Active matrix display device

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