JP2025513806A5 - - Google Patents

Info

Publication number
JP2025513806A5
JP2025513806A5 JP2024559554A JP2024559554A JP2025513806A5 JP 2025513806 A5 JP2025513806 A5 JP 2025513806A5 JP 2024559554 A JP2024559554 A JP 2024559554A JP 2024559554 A JP2024559554 A JP 2024559554A JP 2025513806 A5 JP2025513806 A5 JP 2025513806A5
Authority
JP
Japan
Prior art keywords
wafer
stressor film
module
stressor
map
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024559554A
Other languages
English (en)
Japanese (ja)
Other versions
JP2025513806A (ja
Filing date
Publication date
Priority claimed from US17/885,038 external-priority patent/US12381093B2/en
Application filed filed Critical
Publication of JP2025513806A publication Critical patent/JP2025513806A/ja
Publication of JP2025513806A5 publication Critical patent/JP2025513806A5/ja
Pending legal-status Critical Current

Links

JP2024559554A 2022-04-08 2023-02-22 ハイブリッドパターン形成－接合半導体ツール Pending JP2025513806A (ja)

Applications Claiming Priority (9)

Application Number Priority Date Filing Date Title
US202263328823P 2022-04-08 2022-04-08
US202263328825P 2022-04-08 2022-04-08
US63/328,825 2022-04-08
US63/328,823 2022-04-08
US17/885,038 US12381093B2 (en) 2022-04-08 2022-08-10 Hybrid patterning-bonding semiconductor tool
US17/885,097 US12374562B2 (en) 2022-04-08 2022-08-10 Wafer shape control for W2W bonding
US17/885,097 2022-08-10
US17/885,038 2022-08-10
PCT/US2023/013554 WO2023196061A1 (en) 2022-04-08 2023-02-22 Hybrid patterning-bonding semiconductor tool

Publications (2)

Publication Number Publication Date
JP2025513806A JP2025513806A (ja) 2025-04-30
JP2025513806A5 true JP2025513806A5 (enExample) 2026-03-05

Family

ID=88239810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024559554A Pending JP2025513806A (ja) 2022-04-08 2023-02-22 ハイブリッドパターン形成－接合半導体ツール

Country Status (5)

Country Link
US (2) US12374562B2 (enExample)
JP (1) JP2025513806A (enExample)
KR (2) KR20240170930A (enExample)
TW (2) TW202401600A (enExample)
WO (2) WO2023196061A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20240371705A1 (en) * 2023-05-04 2024-11-07 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer bonding apparatus and method
WO2025122404A1 (en) * 2023-12-04 2025-06-12 Applied Materials, Inc. Control of anisotropic deformation with directional stress modulation for device manufacturing
US20250194165A1 (en) * 2023-12-11 2025-06-12 Applied Materials, Inc. Unification of backside stress mitigation with frontside protection in semiconductor manufacturing processing
EP4576085A1 (en) * 2023-12-22 2025-06-25 ASML Netherlands B.V. System and method for stress release in die bonding
US20250218788A1 (en) * 2023-12-28 2025-07-03 Applied Materials, Inc. Substrate stress management using direct selective area processing
US20250226265A1 (en) * 2024-01-04 2025-07-10 Tokyo Electron Limited Correcting of design and mask shape position due to die and wafer distortion for bonding
US20250259943A1 (en) * 2024-02-13 2025-08-14 Tokyo Electron Limited Die shape control for die to wafer bond enhancement
US20250308953A1 (en) * 2024-03-26 2025-10-02 Applied Materials, Inc. In-Line Validation of Substrate Bonding Surface
US20250308949A1 (en) * 2024-03-29 2025-10-02 Tokyo Electron Limited Die to wafer bonding method and apparatus with thermal contact die shape control
US20260043750A1 (en) * 2024-08-08 2026-02-12 Kla Corporation System and method for wafer shape pairing for improved post-bonding performance

Family Cites Families (20)

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Publication number Priority date Publication date Assignee Title
US7144827B2 (en) * 2002-01-17 2006-12-05 Silecs Oy Poly(organosiloxane) materials and methods for hybrid organic-inorganic dielectrics for integrated circuit applications
US7449284B2 (en) * 2004-05-11 2008-11-11 Miradia Inc. Method and structure for fabricating mechanical mirror structures using backside alignment techniques
US7852101B2 (en) * 2005-09-07 2010-12-14 Nec Corporation Semiconductor device testing apparatus and power supply unit for semiconductor device testing apparatus
US9184041B2 (en) 2013-06-25 2015-11-10 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit with backside structures to reduce substrate warp
US9397051B2 (en) 2013-12-03 2016-07-19 Invensas Corporation Warpage reduction in structures with electrical circuitry
FR3033643B1 (fr) * 2015-03-13 2020-07-17 Unity Semiconductor Dispositif et procede pour detecter des defauts dans des zones de liaison entre des echantillons tels que des wafers
JP6731805B2 (ja) * 2016-07-12 2020-07-29 東京エレクトロン株式会社 接合システム
JP6727069B2 (ja) * 2016-08-09 2020-07-22 東京エレクトロン株式会社 接合装置および接合システム
JP6717267B2 (ja) 2017-07-10 2020-07-01 株式会社Sumco シリコンウェーハの製造方法
US10872873B2 (en) * 2017-11-14 2020-12-22 Taiwan Semiconductor Manufacturing Co., Ltd. Method for bonding wafers and bonding tool
KR20200064133A (ko) * 2017-11-28 2020-06-05 가부시키가이샤 니콘 적층 기판의 제조 방법 및 제조 장치
CN112424908B (zh) * 2018-07-25 2025-06-13 株式会社尼康 接合方法以及接合装置
US11621249B2 (en) * 2018-09-04 2023-04-04 Monolithic 3D Inc. 3D semiconductor device and structure
US11721554B2 (en) * 2019-03-18 2023-08-08 Intel Corporation Stress compensation for wafer to wafer bonding
US11410948B2 (en) 2019-09-25 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structure and manufacturing method thereof
KR102767982B1 (ko) 2019-10-15 2025-02-14 에스케이하이닉스 주식회사 웨이퍼 지지 구조체
WO2021188846A1 (en) * 2020-03-19 2021-09-23 Invensas Bonding Technologies, Inc. Dimension compensation control for directly bonded structures
US11335607B2 (en) * 2020-07-09 2022-05-17 Tokyo Electron Limited Apparatus and methods for wafer to wafer bonding
JP7728160B2 (ja) * 2021-12-16 2025-08-22 キオクシア株式会社 露光装置、及び半導体装置の製造方法
US20230275063A1 (en) * 2022-02-28 2023-08-31 Samsung Electronic Co., Ltd. 3d-stacked semiconductor device with improved alignment using carrier wafer patterning

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