JP2025504087A - メモリアクセス動作を実行するための技法 - Google Patents

メモリアクセス動作を実行するための技法 Download PDF

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Publication number
JP2025504087A
JP2025504087A JP2024545864A JP2024545864A JP2025504087A JP 2025504087 A JP2025504087 A JP 2025504087A JP 2024545864 A JP2024545864 A JP 2024545864A JP 2024545864 A JP2024545864 A JP 2024545864A JP 2025504087 A JP2025504087 A JP 2025504087A
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JP
Japan
Prior art keywords
vector
capability
memory
instruction
registers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024545864A
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English (en)
Japanese (ja)
Other versions
JP2025504087A5 (enExample
Inventor
クリストファー ジャック ボットマン、フランソワ
クリストファー グロカット、トーマス
Original Assignee
アーム・リミテッド
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Publication date
Application filed by アーム・リミテッド filed Critical アーム・リミテッド
Publication of JP2025504087A publication Critical patent/JP2025504087A/ja
Publication of JP2025504087A5 publication Critical patent/JP2025504087A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
JP2024545864A 2022-02-07 2022-12-20 メモリアクセス動作を実行するための技法 Pending JP2025504087A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB2201544.0 2022-02-07
GB2201544.0A GB2615352B (en) 2022-02-07 2022-02-07 Technique for performing memory access operations
PCT/GB2022/053313 WO2023148467A1 (en) 2022-02-07 2022-12-20 Technique for performing memory access operations

Publications (2)

Publication Number Publication Date
JP2025504087A true JP2025504087A (ja) 2025-02-06
JP2025504087A5 JP2025504087A5 (enExample) 2025-12-23

Family

ID=80461352

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024545864A Pending JP2025504087A (ja) 2022-02-07 2022-12-20 メモリアクセス動作を実行するための技法

Country Status (9)

Country Link
US (1) US20250156182A1 (enExample)
EP (1) EP4476612A1 (enExample)
JP (1) JP2025504087A (enExample)
KR (1) KR20240140968A (enExample)
CN (1) CN118647971A (enExample)
GB (1) GB2615352B (enExample)
IL (1) IL314155A (enExample)
TW (1) TW202347121A (enExample)
WO (1) WO2023148467A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12417099B2 (en) * 2022-04-02 2025-09-16 Intel Corporation Circuitry and methods for informing indirect prefetches using capabilities

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2520571B (en) * 2013-11-26 2020-12-16 Advanced Risc Mach Ltd A data processing apparatus and method for performing vector processing
GB2544996B (en) * 2015-12-02 2017-12-06 Advanced Risc Mach Ltd An apparatus and method for managing bounded pointers
US20190205137A1 (en) * 2017-12-29 2019-07-04 Lawrence Meadows Methods and apparatus for multi-load and multi-store vector instructions
US11163569B2 (en) * 2019-12-28 2021-11-02 Intel Corporation Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety
TWI891893B (zh) * 2020-09-02 2025-08-01 美商賽發馥股份有限公司 執行指令的積體電路及記憶體保護的方法
US20230195461A1 (en) * 2021-12-16 2023-06-22 Intel Corporation Circuitry and methods for implementing capabilities using narrow registers

Also Published As

Publication number Publication date
WO2023148467A1 (en) 2023-08-10
EP4476612A1 (en) 2024-12-18
GB2615352B (en) 2024-01-31
TW202347121A (zh) 2023-12-01
US20250156182A1 (en) 2025-05-15
KR20240140968A (ko) 2024-09-24
IL314155A (en) 2024-09-01
GB2615352A (en) 2023-08-09
WO2023148467A9 (en) 2024-08-08
CN118647971A (zh) 2024-09-13

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