KR20240140968A - 메모리 액세스 동작을 수행하기 위한 기술 - Google Patents

메모리 액세스 동작을 수행하기 위한 기술 Download PDF

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Publication number
KR20240140968A
KR20240140968A KR1020247029477A KR20247029477A KR20240140968A KR 20240140968 A KR20240140968 A KR 20240140968A KR 1020247029477 A KR1020247029477 A KR 1020247029477A KR 20247029477 A KR20247029477 A KR 20247029477A KR 20240140968 A KR20240140968 A KR 20240140968A
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KR
South Korea
Prior art keywords
vector
capability
memory
memory access
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
KR1020247029477A
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English (en)
Korean (ko)
Inventor
프랑수아 크리스토퍼 자크 봇맨
토마스 크리스토퍼 그로컷
Original Assignee
에이알엠 리미티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 에이알엠 리미티드 filed Critical 에이알엠 리미티드
Publication of KR20240140968A publication Critical patent/KR20240140968A/ko
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing

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  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Complex Calculations (AREA)
  • Executing Machine-Instructions (AREA)
  • Advance Control (AREA)
KR1020247029477A 2022-02-07 2022-12-20 메모리 액세스 동작을 수행하기 위한 기술 Pending KR20240140968A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB2201544.0 2022-02-07
GB2201544.0A GB2615352B (en) 2022-02-07 2022-02-07 Technique for performing memory access operations
PCT/GB2022/053313 WO2023148467A1 (en) 2022-02-07 2022-12-20 Technique for performing memory access operations

Publications (1)

Publication Number Publication Date
KR20240140968A true KR20240140968A (ko) 2024-09-24

Family

ID=80461352

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020247029477A Pending KR20240140968A (ko) 2022-02-07 2022-12-20 메모리 액세스 동작을 수행하기 위한 기술

Country Status (9)

Country Link
US (1) US20250156182A1 (enExample)
EP (1) EP4476612A1 (enExample)
JP (1) JP2025504087A (enExample)
KR (1) KR20240140968A (enExample)
CN (1) CN118647971A (enExample)
GB (1) GB2615352B (enExample)
IL (1) IL314155A (enExample)
TW (1) TW202347121A (enExample)
WO (1) WO2023148467A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12417099B2 (en) * 2022-04-02 2025-09-16 Intel Corporation Circuitry and methods for informing indirect prefetches using capabilities

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2520571B (en) * 2013-11-26 2020-12-16 Advanced Risc Mach Ltd A data processing apparatus and method for performing vector processing
GB2544996B (en) * 2015-12-02 2017-12-06 Advanced Risc Mach Ltd An apparatus and method for managing bounded pointers
US20190205137A1 (en) * 2017-12-29 2019-07-04 Lawrence Meadows Methods and apparatus for multi-load and multi-store vector instructions
US11163569B2 (en) * 2019-12-28 2021-11-02 Intel Corporation Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety
TWI891893B (zh) * 2020-09-02 2025-08-01 美商賽發馥股份有限公司 執行指令的積體電路及記憶體保護的方法
US20230195461A1 (en) * 2021-12-16 2023-06-22 Intel Corporation Circuitry and methods for implementing capabilities using narrow registers

Also Published As

Publication number Publication date
WO2023148467A1 (en) 2023-08-10
EP4476612A1 (en) 2024-12-18
GB2615352B (en) 2024-01-31
TW202347121A (zh) 2023-12-01
US20250156182A1 (en) 2025-05-15
JP2025504087A (ja) 2025-02-06
IL314155A (en) 2024-09-01
GB2615352A (en) 2023-08-09
WO2023148467A9 (en) 2024-08-08
CN118647971A (zh) 2024-09-13

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