GB2615352B - Technique for performing memory access operations - Google Patents
Technique for performing memory access operations Download PDFInfo
- Publication number
- GB2615352B GB2615352B GB2201544.0A GB202201544A GB2615352B GB 2615352 B GB2615352 B GB 2615352B GB 202201544 A GB202201544 A GB 202201544A GB 2615352 B GB2615352 B GB 2615352B
- Authority
- GB
- United Kingdom
- Prior art keywords
- technique
- memory access
- access operations
- performing memory
- operations
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
- G06F9/30043—LOAD or STORE instructions; Clear instruction
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30105—Register structure
- G06F9/30109—Register structure having multiple operands in a single register
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30181—Instruction operation extension or modification
- G06F9/30192—Instruction operation extension or modification according to data descriptor, e.g. dynamic data typing
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Complex Calculations (AREA)
- Executing Machine-Instructions (AREA)
- Advance Control (AREA)
Priority Applications (9)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB2201544.0A GB2615352B (en) | 2022-02-07 | 2022-02-07 | Technique for performing memory access operations |
| EP22835100.3A EP4476612A1 (en) | 2022-02-07 | 2022-12-20 | Technique for performing memory access operations |
| PCT/GB2022/053313 WO2023148467A1 (en) | 2022-02-07 | 2022-12-20 | Technique for performing memory access operations |
| KR1020247029477A KR20240140968A (ko) | 2022-02-07 | 2022-12-20 | 메모리 액세스 동작을 수행하기 위한 기술 |
| JP2024545864A JP2025504087A (ja) | 2022-02-07 | 2022-12-20 | メモリアクセス動作を実行するための技法 |
| US18/835,476 US20250156182A1 (en) | 2022-02-07 | 2022-12-20 | Technique for performing memory access operations |
| CN202280090725.7A CN118647971A (zh) | 2022-02-07 | 2022-12-20 | 用于执行存储器存取操作的技术 |
| IL314155A IL314155A (en) | 2022-02-07 | 2022-12-20 | Technique for performing memory access operations |
| TW112103610A TW202347121A (zh) | 2022-02-07 | 2023-02-02 | 用於執行記憶體存取操作之技術 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB2201544.0A GB2615352B (en) | 2022-02-07 | 2022-02-07 | Technique for performing memory access operations |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2615352A GB2615352A (en) | 2023-08-09 |
| GB2615352B true GB2615352B (en) | 2024-01-31 |
Family
ID=80461352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2201544.0A Active GB2615352B (en) | 2022-02-07 | 2022-02-07 | Technique for performing memory access operations |
Country Status (9)
| Country | Link |
|---|---|
| US (1) | US20250156182A1 (enExample) |
| EP (1) | EP4476612A1 (enExample) |
| JP (1) | JP2025504087A (enExample) |
| KR (1) | KR20240140968A (enExample) |
| CN (1) | CN118647971A (enExample) |
| GB (1) | GB2615352B (enExample) |
| IL (1) | IL314155A (enExample) |
| TW (1) | TW202347121A (enExample) |
| WO (1) | WO2023148467A1 (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12417099B2 (en) * | 2022-04-02 | 2025-09-16 | Intel Corporation | Circuitry and methods for informing indirect prefetches using capabilities |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150149744A1 (en) * | 2013-11-26 | 2015-05-28 | Arm Limited | Data processing apparatus and method for performing vector processing |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2544996B (en) * | 2015-12-02 | 2017-12-06 | Advanced Risc Mach Ltd | An apparatus and method for managing bounded pointers |
| US20190205137A1 (en) * | 2017-12-29 | 2019-07-04 | Lawrence Meadows | Methods and apparatus for multi-load and multi-store vector instructions |
| US11163569B2 (en) * | 2019-12-28 | 2021-11-02 | Intel Corporation | Hardware apparatuses, methods, and systems for individually revocable capabilities for enforcing temporal memory safety |
| TWI891893B (zh) * | 2020-09-02 | 2025-08-01 | 美商賽發馥股份有限公司 | 執行指令的積體電路及記憶體保護的方法 |
| US20230195461A1 (en) * | 2021-12-16 | 2023-06-22 | Intel Corporation | Circuitry and methods for implementing capabilities using narrow registers |
-
2022
- 2022-02-07 GB GB2201544.0A patent/GB2615352B/en active Active
- 2022-12-20 WO PCT/GB2022/053313 patent/WO2023148467A1/en not_active Ceased
- 2022-12-20 EP EP22835100.3A patent/EP4476612A1/en active Pending
- 2022-12-20 CN CN202280090725.7A patent/CN118647971A/zh active Pending
- 2022-12-20 IL IL314155A patent/IL314155A/en unknown
- 2022-12-20 JP JP2024545864A patent/JP2025504087A/ja active Pending
- 2022-12-20 US US18/835,476 patent/US20250156182A1/en active Pending
- 2022-12-20 KR KR1020247029477A patent/KR20240140968A/ko active Pending
-
2023
- 2023-02-02 TW TW112103610A patent/TW202347121A/zh unknown
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150149744A1 (en) * | 2013-11-26 | 2015-05-28 | Arm Limited | Data processing apparatus and method for performing vector processing |
Non-Patent Citations (2)
| Title |
|---|
| "Capability Hardware Enhanced RISC Instructions: CHERI Instruction-Set Architecture (Version 8)" URL: https://www.cl.cam.ac.uk/techreports/UCAM-CL-TR-951.pdf * |
| "FPnew: An Open-Source Multi-Format Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing", Cornell University Library, 2020 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2023148467A1 (en) | 2023-08-10 |
| EP4476612A1 (en) | 2024-12-18 |
| TW202347121A (zh) | 2023-12-01 |
| US20250156182A1 (en) | 2025-05-15 |
| KR20240140968A (ko) | 2024-09-24 |
| JP2025504087A (ja) | 2025-02-06 |
| IL314155A (en) | 2024-09-01 |
| GB2615352A (en) | 2023-08-09 |
| WO2023148467A9 (en) | 2024-08-08 |
| CN118647971A (zh) | 2024-09-13 |
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