JP2024534530A - より高い接続密度をサポートするためのマルチダイ集積回路パッケージ、及び関連する製造方法 - Google Patents

より高い接続密度をサポートするためのマルチダイ集積回路パッケージ、及び関連する製造方法 Download PDF

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Publication number
JP2024534530A
JP2024534530A JP2024517528A JP2024517528A JP2024534530A JP 2024534530 A JP2024534530 A JP 2024534530A JP 2024517528 A JP2024517528 A JP 2024517528A JP 2024517528 A JP2024517528 A JP 2024517528A JP 2024534530 A JP2024534530 A JP 2024534530A
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die
package
substrate
interconnects
vertical
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JP2024517528A
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Japanese (ja)
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JP2024534530A5 (cg-RX-API-DMAC10.html
Inventor
ダルコ・ポポヴィッチ
デュロダミ・リスク
ユエ・リ
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クアルコム，インコーポレイテッド
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Publication of JP2024534530A publication Critical patent/JP2024534530A/ja
Publication of JP2024534530A5 publication Critical patent/JP2024534530A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

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  • Lead Frames For Integrated Circuits (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
JP2024517528A 2021-09-24 2022-08-24 より高い接続密度をサポートするためのマルチダイ集積回路パッケージ、及び関連する製造方法 Pending JP2024534530A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/484,475 US12062648B2 (en) 2021-09-24 2021-09-24 Multiple (multi-) die integrated circuit (IC) packages for supporting higher connection density, and related fabrication methods
US17/484,475 2021-09-24
PCT/US2022/075390 WO2023049589A1 (en) 2021-09-24 2022-08-24 Multi-die integrated circuit packages for supporting higher connection density, and related fabrication methods

Publications (2)

Publication Number Publication Date
JP2024534530A true JP2024534530A (ja) 2024-09-20
JP2024534530A5 JP2024534530A5 (cg-RX-API-DMAC10.html) 2025-08-20

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JP2024517528A Pending JP2024534530A (ja) 2021-09-24 2022-08-24 より高い接続密度をサポートするためのマルチダイ集積回路パッケージ、及び関連する製造方法

Country Status (7)

Country Link
US (1) US12062648B2 (cg-RX-API-DMAC10.html)
EP (1) EP4406024A1 (cg-RX-API-DMAC10.html)
JP (1) JP2024534530A (cg-RX-API-DMAC10.html)
KR (1) KR20240069727A (cg-RX-API-DMAC10.html)
CN (1) CN117957654A (cg-RX-API-DMAC10.html)
TW (1) TW202320247A (cg-RX-API-DMAC10.html)
WO (1) WO2023049589A1 (cg-RX-API-DMAC10.html)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230268319A1 (en) * 2021-10-14 2023-08-24 Advanced Micro Devices, Inc. Stacking semiconductor devices by bonding front surfaces of different dies to each other
US12463156B2 (en) * 2021-11-10 2025-11-04 Intel Corporation Packaging architectures for sub-terahertz radio frequency devices
US11791320B2 (en) * 2021-11-22 2023-10-17 Qualcomm Incorporated Integrated circuit (IC) packages employing a package substrate with a double side embedded trace substrate (ETS), and related fabrication methods
US12622317B2 (en) * 2021-12-21 2026-05-05 Intel Corporation Packaging architecture for modular die interoperability
US12436467B2 (en) * 2021-12-23 2025-10-07 Intel Corporation Simulating die rotation to minimize area overhead of reticle stitching for stacked dies
TWI875390B (zh) * 2023-12-20 2025-03-01 力成科技股份有限公司 堆疊式封裝結構
CN117790437B (zh) * 2023-12-29 2026-05-08 泉州市三安集成电路有限公司 射频模块和射频模块的制备方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101624973B1 (ko) 2009-09-23 2016-05-30 삼성전자주식회사 패키지 온 패키지 타입의 반도체 패키지 및 그 제조방법
KR101128063B1 (ko) 2011-05-03 2012-04-23 테세라, 인코포레이티드 캡슐화 층의 표면에 와이어 본드를 구비하는 패키지 적층형 어셈블리
CN104064551B (zh) 2014-06-05 2018-01-16 华为技术有限公司 一种芯片堆叠封装结构和电子设备
JP2016529716A (ja) 2014-07-07 2016-09-23 インテル アイピー コーポレーション パッケージオンパッケージ積層マイクロ電子構造体
US10453785B2 (en) * 2014-08-07 2019-10-22 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming double-sided fan-out wafer level package

Also Published As

Publication number Publication date
TW202320247A (zh) 2023-05-16
US20230102167A1 (en) 2023-03-30
EP4406024A1 (en) 2024-07-31
US12062648B2 (en) 2024-08-13
KR20240069727A (ko) 2024-05-20
CN117957654A (zh) 2024-04-30
WO2023049589A1 (en) 2023-03-30

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