JP2024503352A - スキューマッチングのために構成されたコア層中に相互接続を備える基板 - Google Patents

スキューマッチングのために構成されたコア層中に相互接続を備える基板 Download PDF

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Publication number
JP2024503352A
JP2024503352A JP2023540569A JP2023540569A JP2024503352A JP 2024503352 A JP2024503352 A JP 2024503352A JP 2023540569 A JP2023540569 A JP 2023540569A JP 2023540569 A JP2023540569 A JP 2023540569A JP 2024503352 A JP2024503352 A JP 2024503352A
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JP
Japan
Prior art keywords
match
interconnect
interconnects
dielectric layer
electrical path
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023540569A
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English (en)
Japanese (ja)
Other versions
JP2024503352A5 (enExample
Inventor
パティル、アニケット
ブオト、ジョアン・レイ・ビラーバ
ウィ、ホン・ボク
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Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2024503352A publication Critical patent/JP2024503352A/ja
Publication of JP2024503352A5 publication Critical patent/JP2024503352A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
    • H05K3/4694—Partitioned multilayer circuits having adjacent regions with different properties, e.g. by adding or inserting locally circuit layers having a higher circuit density
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H10W44/212—Coaxial feed-throughs in substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/223—Differential pair signal lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Structure Of Printed Boards (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Combinations Of Printed Boards (AREA)
JP2023540569A 2021-01-13 2021-12-10 スキューマッチングのために構成されたコア層中に相互接続を備える基板 Pending JP2024503352A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/148,257 2021-01-13
US17/148,257 US11955409B2 (en) 2021-01-13 2021-01-13 Substrate comprising interconnects in a core layer configured for skew matching
PCT/US2021/062859 WO2022154914A1 (en) 2021-01-13 2021-12-10 Substrate comprising interconnects in a core layer configured for skew matching

Publications (2)

Publication Number Publication Date
JP2024503352A true JP2024503352A (ja) 2024-01-25
JP2024503352A5 JP2024503352A5 (enExample) 2024-11-20

Family

ID=79283142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023540569A Pending JP2024503352A (ja) 2021-01-13 2021-12-10 スキューマッチングのために構成されたコア層中に相互接続を備える基板

Country Status (7)

Country Link
US (1) US11955409B2 (enExample)
EP (1) EP4278381A1 (enExample)
JP (1) JP2024503352A (enExample)
KR (1) KR20230130628A (enExample)
CN (1) CN116686396A (enExample)
BR (1) BR112023013292A2 (enExample)
WO (1) WO2022154914A1 (enExample)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298273A (ja) * 2000-04-17 2001-10-26 Hitachi Ltd 電子部品内蔵実装基板及びそれを用いた半導体パッケージ
US7180011B1 (en) * 2006-03-17 2007-02-20 Lsi Logic Corporation Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design
JP2014032978A (ja) * 2012-07-31 2014-02-20 Ibiden Co Ltd インダクタ部品、インダクタ部品の製造方法及び配線板
WO2019194200A1 (ja) * 2018-04-04 2019-10-10 太陽誘電株式会社 部品内蔵基板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8319111B2 (en) 2006-10-04 2012-11-27 Ngk Spark Plug Co., Ltd. Wiring board having wiring laminate portion with via conductors embedded in resin insulating layers
JP2012009510A (ja) 2010-06-22 2012-01-12 Sumitomo Bakelite Co Ltd 金属微細パターン付き基材、プリント配線板、及び半導体装置、並びに、金属微細パターン付き基材及びプリント配線板の製造方法
JP2013093405A (ja) 2011-10-25 2013-05-16 Ngk Spark Plug Co Ltd 配線基板及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001298273A (ja) * 2000-04-17 2001-10-26 Hitachi Ltd 電子部品内蔵実装基板及びそれを用いた半導体パッケージ
US7180011B1 (en) * 2006-03-17 2007-02-20 Lsi Logic Corporation Device for minimizing differential pair length mismatch and impedance discontinuities in an integrated circuit package design
JP2014032978A (ja) * 2012-07-31 2014-02-20 Ibiden Co Ltd インダクタ部品、インダクタ部品の製造方法及び配線板
WO2019194200A1 (ja) * 2018-04-04 2019-10-10 太陽誘電株式会社 部品内蔵基板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
（社）エレクトロニクス実装学会, プリント回路技術便覧, vol. 第３版, JPN6025045802, 2006, pages 335 - 336, ISSN: 0005828879 *

Also Published As

Publication number Publication date
WO2022154914A1 (en) 2022-07-21
TW202232703A (zh) 2022-08-16
BR112023013292A2 (pt) 2023-10-31
CN116686396A (zh) 2023-09-01
EP4278381A1 (en) 2023-11-22
US11955409B2 (en) 2024-04-09
KR20230130628A (ko) 2023-09-12
US20220223499A1 (en) 2022-07-14

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