JP2024093745A - Method for manufacturing wiring board - Google Patents

Abstract

A support is stably peeled off from a glass substrate while suppressing damage to the glass substrate.
[Solution] A method for manufacturing a wiring board includes bonding a first support 12 to the second surface side of a glass substrate 10 having a first surface S1 and a second surface S2 opposing each other, and including a first region IR in which a first conductor layer is formed, a second region OR surrounding the first region, and a third region ER surrounding the second region and including an end of the first surface; forming a first conductor layer on the first surface side; removing a first deposit 200 including the first conductor layer that is deposited on at least a portion of the side surfaces of the glass substrate and the first support; and separating the first support from the glass substrate.
[Selection diagram] Figure 9

Description

The present invention relates to a method for manufacturing a wiring board.

Electronic devices are becoming more functional and smaller. Accordingly, even higher precision is required for multilayer wiring boards, such as interposers, that are mounted on electronic devices. An interposer is a multilayer wiring board with through electrodes that penetrate the core material. Interposers have the function of relaying components with different inter-terminal distances, such as integrated circuit (IC) chips and printed circuit boards, which have different wiring design rules, via through electrodes.

In recent years, glass interposers that use a glass substrate as the core material have been attracting attention. Glass interposers have low manufacturing costs because they are obtained by forming through electrodes and the like on an inexpensive, large-area glass substrate and then dicing it into individual pieces. On the other hand, when the thickness of the glass substrate becomes as thin as about 100 μm, the glass substrate is prone to cracking and other defects during manufacturing. To prevent such defects, a method has been proposed of reinforcing the glass substrate with a support.

For example, Patent Document 1 describes a method in which a support is attached to a glass substrate via a peeling layer, and the support is peeled off and removed after the wiring is formed. Specifically, first, a first wiring is formed on a first surface of the glass substrate. Next, the first wiring side of the glass substrate on which the first wiring is formed is supported by a support. Then, a laser modified portion that is the starting point of the through hole formation is formed on the glass substrate by irradiating a laser from the surface opposite to the first surface. Next, etching is performed using hydrofluoric acid from the surface opposite to the first surface of the glass substrate toward the first surface, and the through hole is formed while thinning the glass substrate. Next, after the through hole is formed, a through electrode is formed inside the through hole, and a second wiring is formed on the surface opposite to the first surface of the glass substrate, and the first wiring and the second wiring are connected via the through electrode. Then, after the second wiring is formed, the support is removed from the glass substrate. In this way, problems such as cracking of the glass substrate during manufacturing are suppressed.

Patent Document 2 describes a process for laminating a support onto a glass substrate. On the other hand, Patent Document 2 does not describe a process for peeling the support from the glass substrate.

Patent Document 3 describes a process for peeling the support from the glass substrate. However, Patent Document 3 does not describe a method for peeling the support or any concerns that may arise during peeling.

International Publication No. 2019/235617 Patent No. 7011215 Patent No. 6176253

When peeling the support from the glass substrate, the peelability between the glass substrate and the resin layer, or at the side of the laminate of the support, has not been considered. This may result in unintended chipping or cracking of the glass substrate. For this reason, it is difficult to stably peel the support without damaging the glass substrate.

The present invention aims to provide a technology that can stably peel a support from a glass substrate while minimizing damage to the glass substrate.

According to one aspect of the present invention, there is provided a method for manufacturing a wiring board, comprising: bonding a first support to the second surface side of a glass substrate having a first surface and a second surface facing each other, the glass substrate including a first region in which a first conductor layer is formed, a second region surrounding the first region, and a third region surrounding the second region and including an end of the first surface; forming the first conductor layer on the first surface side; removing a first deposit that is deposited on at least a portion of the side surfaces of the glass substrate and the first support and includes the first conductor layer; and separating the first support from the glass substrate.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, in which the first deposit and a third region of the glass substrate are removed in removing the first deposit.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, in which the third region of the glass substrate is removed by a dicing process.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, in which the third region of the glass substrate is removed by irradiating it with laser light.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, in which the third region of the glass substrate is removed by a scribing process and a breaking process.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, in which the width of the third region is greater than 0 mm and equal to or less than 1 mm.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, in which, in removing the first deposit, the first deposit is removed by irradiating it with laser light.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, in which, in removing the first deposit, the first deposit and a third region of the glass substrate are removed, but the first support is not removed.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, further comprising forming a first insulating layer on the first surface, the first deposit further including the first insulating layer.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, further comprising irradiating the glass substrate to which the first support is attached with a laser to form a modified portion in the glass substrate, and etching the modified portion to form a through hole in the glass substrate.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, comprising bonding a second support to the first surface side of the glass substrate, forming a second conductor layer on the second surface side, removing a second deposit that is deposited on at least a portion of the side surfaces of the glass substrate and the second support and includes the second conductor layer, and separating the second support from the glass substrate.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, in which the glass substrate further includes a fourth region provided between the second region and the third region, and in removing the second deposit, the second deposit and the fourth region of the glass substrate are removed.

According to the present invention, it is possible to suppress the occurrence of cracks or chips in the glass substrate when peeling the support from the glass substrate, and to stably peel the support.

FIG. 1 is a cross-sectional view of a wiring board according to a first embodiment. FIG. 2 is an enlarged cross-sectional view showing a part of the wiring board shown in FIG. FIG. 3 is a plan view showing a glass substrate used in manufacturing the wiring board according to the first embodiment. FIG. 4 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 5 is a cross-sectional view showing one step in the method for manufacturing the wiring board according to the first embodiment. FIG. 6 is a plan view of the glass substrate according to the first embodiment. FIG. 7 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 8 is a cross-sectional view showing one step in the method for manufacturing the wiring board according to the first embodiment. FIG. 9 is a cross-sectional view of an end portion of a composite body showing one step in the method for manufacturing a wiring board according to the first embodiment. FIG. 10 is a cross-sectional view of an end portion of a composite body showing one step in the method for manufacturing a wiring board according to the first embodiment. FIG. 11 is a cross-sectional view showing one step in the method for manufacturing the wiring board according to the first embodiment. FIG. 12 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 13 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 14 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 16 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 16 is a cross-sectional view showing a step in the method for manufacturing the wiring board according to the first embodiment. FIG. 17 is a cross-sectional view of an end portion of a composite body, illustrating a step in a method for manufacturing a wiring board according to a first modified example of the first embodiment. FIG. 18 is a cross-sectional view of an end portion of a composite body, illustrating a step in a method for manufacturing a wiring board according to a second modified example of the first embodiment. FIG. 19 is a plan view of a glass substrate according to the second embodiment. FIG. 20 is a cross-sectional view of an end portion of a composite body showing a step in a method for manufacturing a wiring board according to the second embodiment. FIG. 21 is a cross-sectional view of an end portion of a composite body showing a step in a method for manufacturing a wiring board according to the second embodiment.

Below, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is a more specific embodiment of any of the above aspects. The items described below can be incorporated into each of the above aspects, either alone or in combination.

The embodiments shown below are merely examples of configurations for embodying the technical idea of the present invention, and the technical idea of the present invention is not limited by the materials, shapes, structures, etc. of the components described below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In addition, elements having the same or similar functions are given the same reference symbols in the drawings referred to below, and duplicate explanations will be omitted. In addition, the drawings are schematic, and the relationship between dimensions in one direction and dimensions in another direction, and the relationship between the dimensions of one component and the dimensions of another component, etc. may differ from the actual ones.

In this disclosure, "surface" may refer not only to the surface of a plate-like member, but also to the interface of a layer contained in the plate-like member that is approximately parallel to the surface of the plate-like member. Additionally, "upper surface" and "lower surface" refer to the surface shown at the top or bottom of a drawing when a plate-like member or a layer contained in the plate-like member is illustrated. Additionally, the "upper surface" and "lower surface" may also be referred to as the "first surface" and the "second surface".

In addition, "side" refers to the surface of a plate-shaped member or a layer contained in a plate-shaped member, or a portion of the thickness of a layer. Furthermore, a portion of a surface and a side surface may be collectively referred to as the "end portion."

"Up" also means the vertically upward direction when a plate-like member or layer is placed horizontally. Furthermore, "up" and its opposite "down" are sometimes referred to as the "positive Z-axis direction" and the "negative Z-axis direction," and the horizontal direction is sometimes referred to as the "X-axis direction" and the "Y-axis direction."

<1> First embodiment <1.1> Configuration of wiring board First, an example of the configuration of the wiring board 1 will be described with reference to Fig. 1 and Fig. 2. Fig. 1 is a cross-sectional view of the wiring board according to the first embodiment of the present invention. Fig. 2 is an enlarged view of a region R1 in the wiring board shown in Fig. 1. In the following description, when "s" is added to the end of a reference symbol, it indicates that the material is cut to fit the size of the wiring board 1. For example, a glass substrate 10s, which will be described later, indicates that the glass substrate 10 is cut to the size of the wiring board 1.

As shown in Figures 1 and 2, the wiring board 1 is a glass core wiring board using a glass substrate. The wiring board 1 is connected to, for example, a printed wiring board or a silicon chip, not shown. The example in Figure 1 shows a case where the wiring board 1 is a wiring board used as an interposer, that is, a glass interposer.

The wiring board 1 includes a glass substrate 10s, a first conductor layer 20, a dielectric layer 31, an upper electrode 32, an interlayer insulating film 40s, a build-up layer 50, an insulating layer 60s, a conductor layer 70, a second conductor layer 80, an interlayer insulating film 90s, a build-up layer 100, an insulating layer 110s, and a conductor layer 120. The first conductor layer 20, the dielectric layer 31, and the upper electrode 32 form a capacitor 30. That is, the wiring board 1 includes a capacitor 30. The wiring board 1 may also include an inductor (not shown).

The glass substrate 10s is a transparent glass material having optical transparency. The components of the glass substrate 10s and the mixing ratio of the components are not limited. An example of the glass substrate 10s is a glass material mainly composed of silicate, but other glass materials may also be used. Specific examples of the glass substrate 10s include non-alkali glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, photosensitive glass, etc., with non-alkali glass being more preferable.

The thickness of the glass substrate 10s is preferably in the range of 50 μm or more and 150 μm or less. When the wiring substrate 1 is connected to a silicon chip, the linear expansion coefficient of the glass substrate 10s is determined taking into consideration the difference in linear expansion coefficient with the silicon chip. In this case, the linear expansion coefficient of the glass substrate 10s is preferably in the range of 0.5 ppm/K or more and 8.0 ppm/K or less, and more preferably in the range of 1.0 ppm/K or more and 4.0 ppm/K or less.

The glass substrate 10s has a first surface S1 and a second surface S2 facing each other. The first surface S1 and the second surface S2 are approximately parallel. In the following, a plane parallel to the first surface S1 and the second surface S2 is referred to as the XY plane. The directions intersecting each other in the XY plane are referred to as the X direction and the Y direction. The direction intersecting the XY plane is referred to as the Z direction. In the Z direction, the direction from the second surface S2 to the first surface S1 is also referred to as the upward direction. In the Z direction, the direction from the first surface S1 to the second surface S2 is also referred to as the downward direction. The first surface S1 is also referred to as the front surface or upper surface of the glass substrate 10s. The second surface S2 is also referred to as the back surface or lower surface of the glass substrate 10s. In addition, the surface of the glass substrate 10s facing the XY direction is referred to as a side surface.

The glass substrate 10s has one or more through holes HR, each of which reaches from the first surface S1 to the second surface S2. In other words, the glass substrate 10s has one or more through holes HR penetrating the glass substrate 10 in the Z direction. In the example of FIG. 1, five through holes HR are shown, but the number of through holes HR is arbitrary. As shown in FIG. 2, the through holes HR taper from the second surface S2 to the first surface S1. More specifically, for example, the through holes HR have a tapered shape. And, the opening diameter (or cross-sectional area) of the through holes HR on the first surface S1 side is smaller than the opening diameter (or cross-sectional area) of the through holes HR on the second surface S2 side.

First, we will explain the structure of the first surface side of the glass substrate 10s (also referred to as the "front side of the wiring substrate 1").

The first conductor layer 20 is provided on the first surface S1. The first conductor layer 20 functions as a first wiring layer. For example, the first conductor layer 20 includes a land portion, a wiring portion, and a lower electrode portion of the capacitor 30 described below. For example, the land portion of the first conductor layer 20 is a region that surrounds the opening of the through hole HR on the first surface S1 side, and is a region that does not function as the lower electrode of the capacitor 30. The lower electrode portion is a region that functions as the lower electrode of the capacitor 30. The wiring portion of the first conductor layer 20 functions as a wiring that connects, for example, the land portion and the lower electrode portion of the first conductor layer 20.

The first conductor layer 20 has a multi-layer structure. Specifically, the first conductor layer 20 includes a hydrofluoric acid-resistant metal layer 21 and a metal layer 22.

The hydrofluoric acid-resistant metal layer 21 is provided on the first surface S1 of the glass substrate 10. In other words, the hydrofluoric acid-resistant metal layer 21 is in contact with the first surface S1. The hydrofluoric acid-resistant metal layer 21 is made of a metal material that is more resistant to etching by hydrofluoric acid than the glass substrate 10s. That is, the hydrofluoric acid-resistant metal layer 21 has a lower etching rate by hydrofluoric acid than the glass substrate 10s. The hydrofluoric acid-resistant metal layer 21 is, for example, an alloy layer made of a group consisting of Cr and Ni. The thickness of the hydrofluoric acid-resistant metal layer 21 is preferably in the range of 10 nm to 1000 nm.

The metal layer 22 is provided on the hydrofluoric acid resistant metal layer 21. The metal layer 22 includes, for example, a seed layer and a copper layer. For example, the seed layer and the copper layer are laminated in this order on the hydrofluoric acid resistant metal layer 21. The material of the seed layer is appropriately selected from the group consisting of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, and Cu ₃ N _4. The thickness of the seed layer is preferably in the range of 100 nm to 1000 nm, more preferably in the range of 100 nm to 500 nm. The thickness of the copper layer is preferably in the range of 2 μm to 20 μm. The seed layer is provided when the copper layer is formed by electrolytic plating. If the copper layer is formed using other methods such as electroless plating or sputtering, the seed layer may be omitted.

The dielectric layer 31 and the upper electrode 32 are stacked in this order on the lower electrode portion of the first conductor layer 20. The upper electrode 32, the dielectric layer 31, and the lower electrode portion of the first conductor layer 20 form the capacitor 30. More specifically, the capacitor 30 is a MIM (Metal-Insulator-Metal) capacitor.

From the viewpoint of insulation and relative dielectric constant, the dielectric layer 31 can be made of at least one material selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate. The thickness of the dielectric layer 31 is preferably in the range of 10 nm (0.01 μm) to 5 μm, and more preferably in the range of 50 nm (0.05 μm) to 1 μm. If the thickness of the dielectric layer 31 is less than 10 nm (0.01 μm), it is difficult to maintain insulation, and the function as a capacitor may not be expressed. If the thickness of the dielectric layer 31 is more than 5 μm, the manufacturing process described below takes time and is not suitable for mass production.

The upper electrode 32 includes, for example, a seed layer and a metal layer. The seed layer and the metal layer are stacked in this order on the dielectric layer 31. The metal layer of the upper electrode 32 can be made of copper, nickel, chromium, palladium, gold, rhodium, iridium, or the like. From the viewpoints of electrical conductivity and cost, copper is preferred for the metal layer of the upper electrode 32.

In the example shown in FIG. 1, the lower electrode portion of the first conductor layer 20 covers the opening of the through hole HR on the first surface S1 side. That is, the lower electrode portion is provided on the through hole HR. The lower electrode portion may be spaced apart from the through hole HR. When the lower electrode portion is provided so as to cover the opening of the through hole HR on the first surface S1 side, it becomes possible to reduce the electrical resistance caused by the wiring connecting the capacitor 30 and the second conductor layer 80 described below, or to shorten the wiring length.

In this embodiment, the capacitor 30 is provided on the first surface S1 side, but the capacitor may be provided on the second surface S2 side. Also, a capacitor may be provided on each of the first surface S1 side and the second surface S2 side. Also, the capacitor 30 may be omitted.

The interlayer insulating film 40s has a multi-layer structure. For example, the interlayer insulating film 40s includes interlayer insulating films 41s and 42s. For example, the interlayer insulating films 41s and 42s are stacked in this order on the first surface S1.

The build-up layer 50 has a wiring structure of one or more layers. In the example of FIG. 1, the build-up layer 50 has a wiring structure of two layers. For example, the build-up layer 50 includes conductor layers 51 and 52.

The interlayer insulating film 41s is provided on the first surface S1. The interlayer insulating film 41s covers the first conductor layer 20, the dielectric layer 31, and the upper electrode 32. In the XY plane, the interlayer insulating film 41s has through holes at the positions of the land portion of the first conductor layer 20 and the upper electrode 32. For example, the interlayer insulating film 41s is an insulating resin layer. For example, a liquid resin or a film-like resin in which a filler is filled in a thermosetting resin is mainly used as the insulating resin layer. The thermosetting resin preferably contains at least one type of material selected from the group consisting of epoxy resin, polyimide resin, and polyamide resin. The filler preferably contains materials such as silica, titanium oxide, and urethane.

The conductor layer 51 is provided on the interlayer insulating film 41s. The conductor layer 51 includes a land portion and a wiring portion provided on the surface of the interlayer insulating film 41s facing the Z direction, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 41s. The land portion of the conductor layer 51 is, for example, a region surrounding the opening of the through hole provided in the interlayer insulating film 41s. The wiring portion of the conductor layer 51 functions, for example, as wiring connecting between the multiple land portions of the conductor layer 51 or connecting the land portion of the conductor layer 51 and the conductor layer 52. The via portion of the conductor layer 51 connects, for example, the land portion or the upper electrode 32 of the first conductor layer 20 to the land portion of the conductor layer 51.

The conductor layer 51 includes a seed layer and a copper layer. The seed layer and copper layer of the conductor layer 51 are stacked in this order on the interlayer insulating film 41s. The seed layer of the conductor layer 51 may be made of the materials exemplified for the seed layer of the first conductor layer 20 described above.

The interlayer insulating film 42s is provided on the interlayer insulating film 41s. The interlayer insulating film 42s covers the land portion and the wiring portion of the conductor layer 51. The interlayer insulating film 42s has a through hole at the position of the land portion of the conductor layer 51 in the XY plane. For example, the interlayer insulating film 42s is an insulating resin layer. For example, the insulating resin layer included in the interlayer insulating film 42s can use the materials exemplified for the insulating resin layer included in the interlayer insulating film 41s described above.

The conductor layer 52 is provided on the interlayer insulating film 42s. The conductor layer 52 includes a pad portion and a wiring portion provided on the surface of the interlayer insulating film 42s facing the Z direction, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 42s. The pad portion of the conductor layer 52 is, for example, a region surrounding the opening of the through hole provided in the interlayer insulating film 42s. The wiring portion of the conductor layer 52 functions, for example, as wiring connecting between multiple pad portions of the conductor layer 52 or connecting the pad portion of the conductor layer 52 and the conductor layer 70. The via portion of the conductor layer 52 connects, for example, the land portion of the conductor layer 51 and the pad portion of the conductor layer 52.

The conductor layer 52 includes a seed layer and a copper layer. The seed layer and copper layer of the conductor layer 52 are stacked in this order on the interlayer insulating film 42s. The seed layer of the conductor layer 52 can be made of the materials exemplified for the seed layer of the first conductor layer 20 described above.

The insulating layer 60s is provided on the interlayer insulating film 42s (interlayer insulating film 40s). The insulating layer 60s covers the pad portion and wiring portion of the conductor layer 52. Through holes are provided in the insulating layer 60s at the positions of the pad portions of the conductor layer 52 in the XY plane. The insulating layer 60s is made of, for example, solder resist.

The conductor layer 70 is a bump for connecting the front side of the wiring board 1 to an external printed wiring board. The conductor layer 70 fills the through hole of the insulating layer 60s. The conductor layer 70 is connected to the pad portion of the conductor layer 52. The conductor layer 70 has a portion protruding from the insulating layer 60s. The conductor layer 70 is made of, for example, solder.

Next, the structure of the through hole HR and the second surface side (also referred to as the "rear side of the wiring board 1") of the glass substrate 10s will be described.

The second conductor layer 80 includes a portion provided on the second surface S2 and a portion provided in the through hole HR. The portion provided on the second surface S2 of the second conductor layer 80 functions as a second wiring layer. The portion provided on the second surface S2 of the second conductor layer 80 includes a land portion and a wiring portion. The land portion of the second conductor layer 80 is, for example, a region surrounding the opening of the through hole HR on the second surface S2 side. The wiring portion of the second conductor layer 80 functions as, for example, a wiring that connects a plurality of land portions of the second conductor layer 80. The portion provided in the through hole HR of the second conductor layer 80 contacts the side surface of the through hole HR. In addition, the portion provided in the through hole HR of the second conductor layer 80 contacts the hydrofluoric acid resistant metal layer 21 (first conductor layer 20) at the opening of the first surface S1 of the through hole HR. The portion provided in the through hole HR of the second conductor layer 80 functions as a via portion of the second conductor layer 80. The via portion of the second conductor layer 80, for example, connects the first conductor layer 20 and the land portion of the second conductor layer 80.

For example, the second conductor layer 80 may be formed conformally on the side and bottom surfaces of the through hole HR (surfaces in contact with the hydrofluoric acid-resistant metal layer 21 on the first surface S1 side) and on the second surface S2. In other words, the second conductor layer 80 may be formed so that the difference in film thickness on the side and bottom surfaces of the through hole HR and on the second surface S2 is relatively small. The through hole HR may be filled with the second conductor layer 80.

The second conductor layer 80 has a multi-layer structure. For example, the second conductor layer 80 includes a seed layer and a copper layer. For example, the seed layer and copper layer of the second conductor layer 80 are laminated in this order on the glass substrate 10s. The seed layer of the second conductor layer 80 can be made of the materials exemplified for the seed layer of the first conductor layer 20 described above.

The interlayer insulating film 90s has a multi-layer structure. For example, the interlayer insulating film 90s includes interlayer insulating films 91s and 92s. For example, the interlayer insulating films 91s and 92s are stacked in this order on the interlayer insulating film 90s.

The build-up layer 100 has a wiring structure of one or more layers. In the example of FIG. 1, the build-up layer 100 has a wiring structure of two layers. For example, the build-up layer 100 includes conductor layers 101 and 102.

The interlayer insulating film 91s is provided on the second surface S2. The interlayer insulating film 91s covers the second conductor layer 80. A through hole is provided in the interlayer insulating film 91s at the position of the land portion of the second conductor layer 80 in the XY plane. For example, the interlayer insulating film 91s is an insulating resin layer. The insulating resin layer included in the interlayer insulating film 91s can be made of the materials exemplified for the insulating resin layer included in the interlayer insulating film 41s described above.

The conductor layer 101 is provided on the interlayer insulating film 91s. The conductor layer 101 includes a land portion and a wiring portion provided on the surface of the interlayer insulating film 91s facing the Z direction, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 91s. The land portion of the conductor layer 101 is, for example, a region surrounding the opening of the through hole provided in the interlayer insulating film 91s. The wiring portion of the conductor layer 101 functions, for example, as wiring connecting between the multiple land portions of the conductor layer 101 or connecting the land portion of the conductor layer 101 and the conductor layer 102. The via portion of the conductor layer 101 connects, for example, the land portion or wiring portion of the second conductor layer 80 and the land portion of the conductor layer 101.

The conductor layer 101 includes a seed layer and a copper layer. The seed layer and copper layer of the conductor layer 101 are stacked in this order on the interlayer insulating film 91s. The seed layer of the conductor layer 101 can be made of the materials exemplified for the seed layer of the first conductor layer 20 described above.

The interlayer insulating film 92s is provided on the interlayer insulating film 91s. The interlayer insulating film 92s covers the land portion and the wiring portion of the conductor layer 101. The interlayer insulating film 92s has a through hole at the position of the land portion of the conductor layer 101 in the XY plane. For example, the interlayer insulating film 92s is an insulating resin layer. The insulating resin layer included in the interlayer insulating film 92s can be made of the materials exemplified for the insulating resin layer included in the interlayer insulating film 41s described above.

The conductor layer 102 is provided on the interlayer insulating film 92s. The conductor layer 102 includes a pad portion and a wiring portion provided on the surface of the interlayer insulating film 92s facing the Z direction, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 92s. The pad portion of the conductor layer 102 is, for example, a region surrounding the opening of the through hole provided in the interlayer insulating film 92s. The wiring portion of the conductor layer 102 functions, for example, as wiring connecting between multiple pad portions of the conductor layer 102 or connecting the pad portion of the conductor layer 102 and the conductor layer 120. The via portion of the conductor layer 102 connects, for example, the land portion of the conductor layer 101 and the pad portion of the conductor layer 102.

The conductor layer 102 includes a seed layer and a copper layer. The seed layer and copper layer of the conductor layer 102 are stacked in this order on the interlayer insulating film 92s. The seed layer of the conductor layer 102 can be made of the materials exemplified for the seed layer of the first conductor layer 20 described above.

The insulating layer 110s is provided on the interlayer insulating film 92s (interlayer insulating film 90s). The insulating layer 110s covers the pad portion and the wiring portion of the conductor layer 102. The insulating layer 110s has a through hole at the position of the pad portion of the conductor layer 102 in the XY plane. The insulating layer 110s is made of, for example, solder resist.

The conductor layer 120 is a bump for connecting the back side of the wiring board 1 to an external printed wiring board. The conductor layer 120 fills the through hole of the insulating layer 110s. The conductor layer 120 is connected to the pad portion of the conductor layer 102. The conductor layer 120 has a portion protruding from the insulating layer 110s. The conductor layer 120 is made of, for example, solder.

<1.2> Manufacturing Method of Wiring Board Next, an example of a manufacturing method of the wiring board 1 will be described with reference to Figs. 3 to 16. In the manufacturing process of the wiring board 1, first to fourteenth steps described below are performed. Fig. 3 is a plan view showing a glass substrate 10 used in manufacturing the wiring board 1. Figs. 4 to 16 are cross-sectional views showing a step in the manufacturing method of the wiring board 1. Of these, Figs. 4, 5, 7, and 8, and Figs. 11 to 16 are cross-sectional views taken along line A-A in Fig. 3. Fig. 6 is a plan view of the glass substrate 10. Figs. 9 and 10 are cross-sectional views of an end of a composite showing a step in the manufacturing method of the wiring board 1.

<1.2.1> First step First, a glass substrate 10 having a first surface S1 as a front surface and a second surface S2 as a back surface is prepared. For example, contaminants are removed from the surface of a non-alkali glass plate by ultrasonic cleaning or the like to obtain the glass substrate 10.

The manufacturing method of the glass substrate 10 is not particularly limited. Examples of manufacturing methods of the glass substrate 10 include the float method, the down-draw method, the fusion method, the up-draw method, and the roll-out method.

As shown in FIG. 3, the glass substrate 10 is a large-sized glass substrate having larger dimensions in the X and Y directions compared to the glass substrate 10s. In the XY plan view (when viewed in the Z direction), the glass substrate 10 has a central portion IR, an outer peripheral portion OR, and an end portion ER. The central portion IR is a region in which a plurality of glass substrates 10s are arranged in a matrix. The outer peripheral portion OR is an outer region surrounding the central portion IR. The end portion ER is a region surrounding the outer peripheral portion OR, and includes the end portion of the glass substrate 10. The thickness of the glass substrate 10 is preferably in the range of 75 μm or more and 200 μm or less.

<1.2.2> Second step Next, as shown in Fig. 4, the support 12 is bonded to the second surface S2 via the adhesive layer 11. To bond the support 12 to the glass substrate 10, for example, a laminator, a vacuum pressure press, a vacuum bonding machine, etc. can be used. In the example of Fig. 4, the central portion IR shows an excerpt of the glass substrate 10s of one wiring substrate 1. The same applies to Figs. 5 to 8 and Figs. 11 to 16.

The adhesive layer 11 is an adhesive layer for temporarily fixing the support 12 to the glass substrate 10. The adhesive layer 11 is, for example, a functional group formed on the second surface S2. An example of the functional group used as the adhesive layer 11 is a hydroxyl group.

For ease of explanation, in Figs. 4 to 16, the adhesive layer 11 is illustrated as a layer having a thickness. However, when a functional group formed on the second surface S2 is used as the adhesive layer 11, the thickness of the adhesive layer 11 is negligibly small compared to the glass substrate 10 and the support 12. For this reason, the adhesive layer 11 can also be expressed as an interface between the glass substrate 10 and the support 12.

The support 12 is the first support and is a thin-plate carrier. From the viewpoint of adhesion, it is desirable that the support 12 is made of the same material as the glass substrate 10. That is, when the glass substrate 10 is made of alkali-free glass, it is preferable that the support 12 is also made of alkali-free glass. The thickness of the support 12 may be set appropriately according to the thickness of the glass substrate 10. In consideration of the transportability of the glass substrate 10, it is preferable that the thickness of the support 12 is within the range of 300 μm or more and 1500 μm or less.

<1.2.3> Third step Next, as shown in Fig. 5, the glass substrate 10 is irradiated with laser light to form one or more modified portions 13 in the glass substrate 10. The direction of irradiation of the laser light may be from the first surface S1 to the second surface S2, or from the second surface S2 to the first surface S1. As shown in Fig. 5, when the modified portion 13 is formed from the first surface S1 to the second surface S2, the modified portion 13 may be formed to reach the adhesive layer 11 and the support 12.

The modified area 13 is, for example, a portion that is heated by laser light irradiation, resulting in a difference in crystallinity, etc., between the modified area 13 and an area not irradiated with laser light. As shown in FIG. 6, the modified area 13 is formed at a position corresponding to a through hole to be formed in the glass substrate 10. The modified area 13 extends, for example, in the Z direction.

The wavelength of the laser light used to form the modified portion 13 is 535 nm or less. The preferred wavelength of the laser light is 355 nm or more and 535 nm or less. If the wavelength of the laser light is less than 355 nm, it may be difficult to obtain sufficient laser output, and stable laser modification may be difficult. On the other hand, if the wavelength of the laser light is greater than 535 nm, the irradiation spot becomes larger, making small-area laser modification difficult. In addition, if the wavelength of the laser light is greater than 535 nm, microcracks may occur due to the influence of heat, making the glass substrate 10 more likely to break.

When using a pulsed laser, it is desirable for the laser pulse width to be in the range of picoseconds to femtoseconds. If the laser pulse width is nanoseconds or longer, it becomes difficult to control the amount of energy per pulse, and microcracks occur, making the glass substrate 10 more likely to break.

The energy of the laser pulse is selected to a preferred value depending on the composition of the glass substrate 10 and the type of laser modification to be produced, and is preferably in the range of 5 μJ or more and 150 μJ or less. By increasing the energy of the laser pulse, it is possible to increase the length of the modified portion in proportion to the energy of the laser pulse.

7, a first conductor layer 20 is formed on the first surface S1 so as to cover the modified portion 13. That is, in the XY plane, the first conductor layer 20 is formed at a position where the modified portion 13 is formed.

More specifically, for example, first, the hydrofluoric acid resistant metal layer 21 and the seed layer of the metal layer 22 are formed in this order on the first surface S1. That is, the seed layer is formed on the hydrofluoric acid resistant metal layer 21. The hydrofluoric acid resistant metal layer 21 is formed by, for example, sputtering. The seed layer is formed by, for example, sputtering or electroless plating.

Next, the first conductor layer 20 is formed, for example, by a semi-additive process (SAP). More specifically, a mask pattern having openings at positions corresponding to the copper layer of the metal layer 22 is first formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on the photoresist layer. According to one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated on the seed layer. Then, the mask pattern is formed by sequentially performing pattern exposure and development of the dry photoresist. The mask pattern may be formed using a liquid resist.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This causes copper to be deposited on the seed layer at the positions of the openings in the mask pattern, forming a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and stripped off.

Next, the entire surface of the copper layer side of the composite including the copper layer and the glass substrate 10 is etched in the exposed portion of the seed layer (the portion where the copper layer is not provided) until the seed layer and the hydrofluoric acid-resistant metal layer 21 are removed.

In addition, in the fourth step, the hydrofluoric acid-resistant metal layer 21 and the metal layer 22 are deposited on at least a portion of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12.

<1.2.5> Fifth step Next, a dielectric layer 31 and an upper electrode 32 are formed in this order on the lower electrode of the first conductor layer 20. This forms the capacitor 30 shown in Fig. 7. The upper electrode 32 can be formed, for example, by the same method as the seed layer and copper layer of the first conductor layer 20.

Then, an interlayer insulating film 41 is formed on the first surface S1 side of the glass substrate 10. At this time, the capacitor 30 and the first conductor layer 20 are covered with the interlayer insulating film 41. In other words, the interlayer insulating film 41 is provided on the surface of the composite including the capacitor 30, the first conductor layer 20, and the glass substrate 10, facing the capacitor 30. In the following description, the glass substrate 10 and other members (materials) formed on the glass substrate 10 are collectively referred to as the "composite". The structure of the composite differs depending on the manufacturing process of the wiring substrate 1.

When the interlayer insulating film 41 is a liquid resin, the interlayer insulating film 41 is formed by a spin coating method. When the interlayer insulating film 41 is a film-like resin, the interlayer insulating film 41 is formed by heating and pressurizing under a vacuum using a vacuum laminator. According to one example, the interlayer insulating film 41 is formed by laminating ABF-GXT31 (32.5 μm thick), an insulating resin film manufactured by Ajinomoto Fine-Techno Co., Ltd., onto the composite, and then pre-curing the laminate.

In addition, in the fifth step, the dielectric layer 31, the upper electrode 32, and the interlayer insulating film 41 are deposited on at least a portion of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12.

8, the composite including the glass substrate 10 and the interlayer insulating film 41 is supported by the support 15. More specifically, the interlayer insulating film 41 and the support 15 are bonded together via the adhesive layer 14 so that the interlayer insulating film 41 of the composite faces the support 15.

For the adhesive layer 14, a resin or a functional group formed on the support 15 is used. Examples of resins include resins that absorb light such as UV light and become peelable by generating heat, sublimating, or changing in quality, resins that become peelable by foaming due to heat, resins whose adhesion changes depending on temperature, adhesive resins, etc. According to one example, Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation is used for the adhesive layer 14.

The support 15 is a second support and is a thin-plate carrier. It is preferable that the support 15 is made of the same material as the glass substrate 10. That is, when the glass substrate 10 is made of alkali-free glass, it is preferable that the support 15 is also made of alkali-free glass. The thickness of the support 15 may be set appropriately according to the thickness of the glass substrate 10. In consideration of the transportability of the glass substrate 10, it is preferable that the thickness of the support 15 is in the range of 300 μm or more and 1500 μm or less.

<1.2.7> Seventh step Next, as shown in FIG. 9, the end ER of the glass substrate 10, that is, the four end sides including the side of the glass substrate 10, are removed (cut). Hereinafter, this is also referred to as a cutting process of the four sides of the glass substrate 10. More specifically, the end ER of the composite including the glass substrate 10, the adhesive layers 11 and 14, the supports 12 and 15, and the interlayer insulating film 41 and the deposit 200 deposited on the side of the composite are removed. After the completion of the sixth step, the deposit 200 is deposited on at least a part of the side of the glass substrate 10, the adhesive layer 11, and the support 12 by the fourth and fifth steps. For example, the deposit 200 includes the hydrofluoric acid resistant metal layer 21, the metal layer 22, the dielectric layer 31, the upper electrode 32, and the interlayer insulating film 41. The deposit 200 may be deposited so as to cover the entire side of the glass substrate 10, the adhesive layer 11, and the support 12.

For example, in the fourth step, when the seed layer of the hydrofluoric acid resistant metal layer 21 and the metal layer 22 is formed on the first surface S1, the seed layer of the hydrofluoric acid resistant metal layer 21 and the metal layer 22 is also deposited on at least a part of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12. When electrolytic copper plating is performed using the seed layer as a power supply layer, copper is deposited on the seed layer at the position of the opening of the mask pattern, but copper is also deposited on the part of the end ER that cannot be masked. Therefore, copper is deposited on at least a part of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12. That is, the hydrofluoric acid resistant metal layer 21 and the metal layer 22 are deposited on at least a part of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12. In the fifth step, when forming the dielectric layer 31 and the upper electrode 32, similar to the fourth step, the dielectric layer 31 and the upper electrode 32 are deposited on at least a part of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12 so as to cover the hydrofluoric acid resistant metal layer 21 and the metal layer 22. Furthermore, when forming the interlayer insulating film 41, the interlayer insulating film 41 is deposited on at least a part of the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12 so as to cover the upper electrode 32.

If the deposit 200 is deposited so as to cover the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12, i.e., the bonding surface between the glass substrate 10 and the support 12, in the next eighth step, when the glass substrate 10 and the support 12 are peeled off, the end of the glass substrate 10 is caught during the peeling, which makes it easy for the glass to crack or chip. Therefore, in the seventh step, the end ER of the composite is cut to remove the deposit 200 on the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12. By removing the deposit 200, the occurrence of cracking or chipping of the glass can be suppressed in the next peeling step of the support 12. This makes it possible to stably peel off the glass substrate 10 and the support 12. In other words, the decrease in the manufacturing yield of the wiring substrate 1 can be suppressed.

The width of the end ER is greater than 0 mm and less than 10 mm. If the width of the end ER is 10 mm or more, there is a possibility that it may overlap with the effective pattern in the glass substrate 10, i.e., the central portion IR. Preferably, the end ER is cut so that its width is greater than 0 mm and not more than 1 mm. By cutting within a range of 1 mm or less, the effective surface (central portion IR) can be sufficiently secured.
Specifically, the edge ER is removed by a dicing process using a diamond blade. By performing the process on all four sides of the glass substrate 10, all of the covered portions of the edge can be removed. As another method, the edge ER can be removed by a process using laser light irradiation or a scribing process.

In the example of FIG. 9, the size of the glass substrate 10 is the same as the size of the support 12, but the size of the glass substrate 10 and the size of the support 12 may be different.

<1.2.8> Eighth Step Next, the adhesive layer 11 and the support 12 are separated from the glass substrate 10. As shown in Fig. 10, for example, on the side surface of the composite, the adhesive layer 11, i.e., the vicinity of the bonding surface between the glass substrate 10 and the support 12, is set as a peeling initiation point N. Then, by applying a mechanical load from the peeling initiation point N toward the central portion IR, peeling can be advanced with the peeling initiation point N as the physical initiation point. As a result, the support 12 is removed as shown in Fig. 11.

More specifically, a scribing process is performed on the peeling starting point N. The scribing process includes a process of pressing a jig having a tapered tip, such as a razor blade, against the peeling starting point N so that the tip is located within the peeling starting point N. Then, with the jig pressed against the peeling starting point N, a force is applied in a direction that pulls the glass substrate 10 and the support 12 away from each other. Alternatively, with the jig pressed against the peeling starting point N, a fluid such as a liquid or gas may be introduced between the glass substrate 10 and the support 12 from the position of the peeling starting point N. This allows the support 12 to be separated from the glass substrate 10 more smoothly.

If any residue of the adhesive layer 11 remains on the glass substrate 10 after the peeling process of the adhesive layer 11 and the support 12, plasma cleaning, ultrasonic cleaning, water cleaning, solvent cleaning using alcohol, etc. may be performed.

<1.2.9> Ninth step Next, the second surface S2 of the glass substrate 10 from which the adhesive layer 11 and the support 12 have been peeled off is etched with an etching solution containing hydrogen fluoride. As a result, as shown in Fig. 12, the second surface S2 is recessed and through holes HR are formed at the positions of the modified portions 13. The modified portions 13 of the glass substrate 10 have a higher etching rate than other portions. Therefore, this etching process can simultaneously thin the glass substrate 10 and form the through holes HR.

The amount of etching by the etching process is appropriately set according to the thickness of the glass substrate 10. For example, if the thickness of the glass substrate 10 before the etching process is 200 μm, it is preferable that the amount of etching of the glass substrate 10 is within a range of 50 μm or more and 150 μm or less. This allows the thickness of the glass substrate 10 after the etching process to be within a range of 50 μm or more and 150 μm or less.

In this etching process, the hydrofluoric acid resistant metal layer 21 serves as an etching stopper film. In addition, the through hole HR obtained by the above etching has a truncated cone shape in which the opening diameter (or cross-sectional area) on the second surface S2 side is larger than the opening diameter (or cross-sectional area) on the first surface S1 side in FIG. 12.

The etching solution containing hydrogen fluoride is, for example, an aqueous hydrogen fluoride solution. The etching solution may further contain one or more inorganic acids selected from the group consisting of nitric acid, hydrochloric acid, and sulfuric acid.

The hydrogen fluoride concentration of the etching solution is, for example, in the range of 1.0% by mass to 6.0% by mass, and preferably in the range of 2.0% by mass to 5.0% by mass. The inorganic acid concentration is, for example, in the range of 1.0% by mass to 20.0% by mass, and preferably in the range of 3.0% by mass to 16.0% by mass. It is desirable to perform the etching process at an etching rate of 1.0 μm/min or less using an etching solution in which the concentrations of each component are set within the above ranges. It is desirable to keep the temperature of the etching solution during the etching process in the range of 10°C to 40°C.

<1.2.10> Tenth Step Next, the second conductor layer 80 is formed so as to cover the through hole HR.

Specifically, first, a seed layer of the second conductor layer 80 is formed as a continuous film that covers the sidewall of the through hole HR, the surface of the hydrofluoric acid-resistant metal layer 21 exposed by the etching process, and the second surface S2. The seed layer is formed, for example, by sputtering or electroless plating.

Next, the second conductor layer 80 as shown in FIG. 13 is obtained, for example, by a semi-additive process.

Specifically, first, a mask pattern with openings at positions corresponding to the copper layer included in the second conductor layer 80 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. In one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and stripped off. Next, the entire surface of the copper layer side of the composite including the copper layer and the glass substrate 10 is etched until the exposed portion of the seed layer is removed.

In this manner, the second conductor layer 80 is obtained. As described above, the second conductor layer 80 includes a land portion and a wiring portion.

Next, a process similar to the process for forming the interlayer insulating film 41 in the fifth step is performed on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the second conductor layer 80, to provide an interlayer insulating film 91. The interlayer insulating film 91 may be formed of a material different from that of the interlayer insulating film 41.

14, the adhesive layer 14 and the support 15 are separated from the composite including the glass substrate 10, the first conductor layer 20, the second conductor layer 80, etc. When separating the adhesive layer 14 and the support 15, a peeling method such as UV light irradiation, heat treatment, physical peeling, etc. is appropriately selected depending on the material of the adhesive layer 14.

If residues of the adhesive layer 14 remain on the interlayer insulating film 41 after the peeling process of the adhesive layer 14 and the support 15, plasma cleaning, ultrasonic cleaning, water cleaning, solvent cleaning using alcohol, etc. may be performed.

<1.2.12> Twelfth Step Next, as shown in FIG. 15, the build-up layer 50 is provided on the first surface S1 side, and the build-up layer 100 is provided on the second surface S2 side.

The order in which the build-up layers 50 and 100 are formed is arbitrary. The process for forming the build-up layers 50 and 100 is the same except that the surfaces on which they are formed are different. Here, the formation of the build-up layer 50 will be described as an example.

First, a blind via is formed in the interlayer insulating film 41 by laser processing. After that, a desmear process is performed to remove residues generated by the laser processing. This exposes the land portion of the first conductor layer 20 and the upper electrode 32. Note that the laser used to form the blind via may be different from the laser used to form the modified portion 13. For example, a pulsed laser such as a carbon dioxide laser or a UV-YAG laser is preferably used to form the blind via. When a pulsed laser is used, the laser pulse width is preferably in the range of microseconds.

Next, the seed layer contained in the conductor layer 51 is formed as a continuous film on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the first conductor layer 20 by sputtering or electroless plating.

Next, the conductor layer 51 is obtained, for example, by a semi-additive process.

Specifically, first, a mask pattern having openings at positions corresponding to the copper layer included in the conductor layer 51 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. According to one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the first conductor layer 20 side is etched until the exposed portion of the seed layer is removed. In this manner, the conductor layer 51 is obtained.

Next, an interlayer insulating film 42 is provided on the interlayer insulating film 41, and then a blind via is formed in the interlayer insulating film 42 by laser processing. After that, a desmear process is performed to remove residues generated by the laser processing. This exposes the land portion of the conductor layer 51. Note that the laser used to form the blind via may be different from the laser used to form the modified portion 13. For example, a pulsed laser such as a carbon dioxide laser or a UV-YAG laser is preferably used to form the blind via. When a pulsed laser is used, the laser pulse width is preferably in the range of microseconds.

Next, the seed layer contained in the conductor layer 52 is formed as a continuous film on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the first conductor layer 20 by sputtering or electroless plating.

Next, the conductor layer 52 is obtained, for example, by a semi-additive process.

Specifically, first, a mask pattern having openings at positions corresponding to the copper layer included in the conductor layer 52 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. According to one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the first conductor layer 20 side is etched until the exposed portion of the seed layer is removed. In this manner, the conductor layer 52 is formed, and the build-up layer 50 is obtained.

In addition, a process similar to the process for forming the build-up layer 50 described above is performed on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the second conductor layer 80 to obtain the build-up layer 100.

<1.2.13> Thirteenth Step Next, an insulating layer 60 is provided on the interlayer insulating film 42. For example, a solder resist is provided on the interlayer insulating film 42, and is patterned using a photolithography method or the like. This exposes the pad portions of the conductor layer 52. Thereafter, a surface treatment is performed on the exposed pad portions of the conductor layer 52, and then the conductor layer 70 is provided.

Similarly, an insulating layer 110 is provided on the interlayer insulating film 92. For example, a solder resist is provided on the interlayer insulating film 92, and then patterned using a photolithography method or the like. This exposes the pad portion of the conductor layer 102. After that, a surface treatment is performed on the exposed pad portion of the conductor layer 102, and then the conductor layer 120 is provided.

Surface treatments include treatments using nickel and gold, treatments using nickel, palladium, or gold, immersion tin plating (IT), and organic solderability preservative (OSP).

In this way, the structure shown in Figure 16 is obtained.

<1.2.14> Fourteenth Step: Thereafter, the outer peripheral portion OR is separated from the obtained composite, and the inside of the central portion IR is divided into individual regions corresponding to a plurality of glass substrates 10s.

In this manner, the wiring board 1 shown in Figure 1 is obtained.

<1.3> Effects The above-described technology provides the following effects, for example.

<1.3.1> Handling Ease According to the above-described manufacturing method, the glass substrate 10 is less likely to be damaged, and excellent handling ease can be achieved. This will be described below.

When through holes are formed in a glass substrate, its mechanical strength may decrease. In addition, a relatively thin glass substrate, for example, a substrate having a thickness of 100 μm or less, is prone to cracking during transportation for forming conductive parts such as circuits on the glass substrate, and is difficult to handle.

According to the above-mentioned manufacturing method, before the first conductor layer 20 and the like are formed, the support 12 is bonded to the second surface S2 side of the glass substrate 10. As a result, the composite including the glass substrate 10 and the support 12 can have high strength. In addition, before the support 12 is peeled off, the support 15 is bonded to the first surface S1 side on which the first conductor layer 20 and the like are formed. As a result, the strength of the composite is further increased. Therefore, even after the support 12 is peeled off from the composite, the glass substrate 10 is unlikely to break. Therefore, according to the above-mentioned manufacturing method, the glass substrate 10 is unlikely to break and is easy to handle.

<1.3.2> Productivity Furthermore, according to the above-described manufacturing method, high productivity can be achieved, as will be described below.

When forming the modified portion 13, if excessive energy is applied to the glass substrate 10 by the laser light, microcracks may occur in the glass substrate 10. For this reason, restrictions may be imposed on the irradiation conditions (process window), such as the wavelength and laser pulse width of the laser light, and the laser irradiation position.

According to the above-mentioned manufacturing method, the glass substrate 10 to which the support 12 is bonded is irradiated with laser light to form the modified portion 13. This makes it possible to increase the mechanical strength of the glass substrate 10 during laser light irradiation compared to when the glass substrate 10 to which the support 12 is not bonded is irradiated with laser light. This makes it possible to ease the processing conditions for laser light irradiation. In addition, it becomes possible to form the modified portion 13 at a desired position on the glass substrate 10. Therefore, the above-mentioned manufacturing method makes it possible to achieve high productivity.

<1.3.3> Yield Furthermore, according to the above-described manufacturing method, damage to the glass substrate 10 can be suppressed when the support 12 is peeled off from the glass substrate 10, and a high yield can be achieved. This will be described below.

When peeling the support 12 from the glass substrate 10, damage such as cracks and chips may occur to the glass substrate 10. In other words, damage to the glass substrate 10 during the process of peeling the support 12 from the glass substrate 10 may reduce the yield.

According to the above-mentioned manufacturing method, the end ER of the glass substrate 10 in the state where the supports 12 and 15 are bonded together is removed. This makes it possible to remove the deposits 200 on the side surfaces of the glass substrate 10, the adhesive layer 11, and the support 12. Therefore, when peeling the glass substrate 10 from the support 12, it is possible to suppress the occurrence of cracks or chips in the glass caused by the end of the glass substrate 10 getting caught during peeling. This makes it possible to stably peel the glass substrate 10 from the support 12. Therefore, according to the above-mentioned manufacturing method, it is possible to achieve a high manufacturing yield.

<1.4> Modifications Various modifications are possible to the above-described method for manufacturing the wiring board 1. Three modifications will be described below.

<1.4.1> First Modification First, the first modification will be described with reference to Fig. 17. Fig. 17 is a cross-sectional view of an end of a composite showing one step in a manufacturing method of a wiring board 1. In the first modification, an example of a method for removing deposits 200 on the side surface of glass substrate 10 when the size of support 12 is larger than the size of glass substrate 10 will be described.

As shown in FIG. 17, in the seventh step of the first embodiment, only the deposit 200 on the side of the glass substrate 10 and the adhesive layer 11 may be removed. That is, the hydrofluoric acid resistant metal layer 21, the metal layer 22, the dielectric layer 31, the upper electrode 32, and the interlayer insulating film 41 deposited on the side of the glass substrate 10 and the adhesive layer 11 are removed. In the first modified example, the glass substrate 10, the adhesive layers 11 and 14, and the supports 12 and 15 are not cut. By not cutting the support 12, the support 12 can play the role of a guide when making the marking in the eighth step of the first embodiment. This allows the support 12 to be peeled off stably. The deposit 200 may be removed by a process using laser light irradiation or an etching process.

<1.4.2> Second Modification Next, a second modification will be described with reference to Fig. 18. Fig. 18 is a cross-sectional view of an end portion of a composite showing one step in a manufacturing method of a wiring board 1. In the second modification, an example of a method for removing deposits 200 on the side surface of a glass substrate 10, which is different from the first modification, will be described.

As shown in FIG. 18, in the seventh step of the first embodiment, if the size of the support 12 is larger than the size of the glass substrate 10, the support 12 does not need to be cut. That is, the support 15 to the glass substrate 10 (adhesive layer 11) are removed. As in the first modified example, by not cutting the support 12, the support 12 can serve as a guide when making scribes in the eighth step of the first embodiment. This allows the support 12 to be peeled off stably. A dicing process is preferable for cutting the glass substrate 10.

<1.4.3> Third Modification Next, the third modification will be described. In the third modification, a case where a scribing process is applied to remove the end ER in the seventh step will be described. The scribing process is a process for making scratches on the surface of the cut object. For this reason, in the case of a composite in which the support 12, the glass substrate 10, and the support 15 are bonded together, it is preferable to perform the scribing process on both sides of the composite. After the scribing process is performed on both sides of the composite, the breaking process is performed. For this reason, the process requires one more step than other methods, but as with other methods, it is possible to cut off the end and stably peel off the support.

<2> Second embodiment Next, a second embodiment will be described. In the second embodiment, a case where a step of removing the end of the glass substrate 10 is added before the eleventh step in the first embodiment, similarly to the seventh step, will be described. The following mainly describes the points that are different from the first embodiment.

<2.1> Planar Configuration of Glass Substrate First, the planar configuration of the glass substrate will be described with reference to Fig. 19. Fig. 19 is a plan view showing a glass substrate 10 used in manufacturing the wiring substrate 1.

As shown in FIG. 19, the glass substrate 10 has a central portion IR, an outer peripheral portion OR, and ends ER1 and ER2 in the XY plane view (when viewed in the Z direction). End ER2 is a region that surrounds the outer peripheral portion OR. End ER1 is a region that surrounds end ER2 and includes the end of the glass substrate 10.

2.2 Manufacturing Method of Wiring Board Next, an example of a manufacturing method of the wiring board 1 will be described with reference to Fig. 20 and Fig. 21. Fig. 20 and Fig. 21 are cross-sectional views of an end portion of a composite body showing one step in the manufacturing method of the wiring board 1.

As shown in FIG. 20, in the seventh step of the first embodiment, the deposit 200 and the end ER1 are removed.

21, after performing the 10th step of the first embodiment, and before performing the 11th step, the end ER2 of the glass substrate 10, i.e., the four end sides including the side surfaces, are removed (cut) in the same manner as in the 7th step. More specifically, the deposit 210 deposited on the end ER2 of the composite including the glass substrate 10, the adhesive layer 14, the support 15, and the interlayer insulating films 41 and 91 and on the side surfaces of the composite is removed. For example, after the 10th step is completed, the deposit 210 from the 10th step is deposited on the side surfaces of the glass substrate 10, the side surfaces of the interlayer insulating film 41, the side surfaces of the adhesive layer 14, and part of the side surfaces of the support 15. For example, the deposit 210 includes the second conductor layer 80 and the interlayer insulating film 91. The deposit 210 may be deposited so as to cover the entire sides of the glass substrate 10, the interlayer insulating film 41, the adhesive layer 14, and the support 15.

By treating the edge of the glass substrate 10 in the same manner as in step 7, the support 15 can be stably peeled off in step 11.

The first to third modified examples of the first embodiment may be applied to the processing of the end of the glass substrate 10 of the second embodiment.

The following describes the tests conducted in relation to the present invention.

Example 1
The first to eighth steps of the first embodiment were carried out to manufacture 20 glass substrates 10 from which the support 12 was peeled off. In the seventh step, the cutting process of the four sides of the glass substrate 10 was carried out by dicing using a dicing blade.

Here, the size of the glass substrate 10 was 150 μm thick, 200 mm long in the X direction, and 200 mm long in the Y direction. The size of the support 12 was 500 μm thick, and the dimensions in the X direction and Y direction were the same as those of the glass substrate 10. The material of both the glass substrate 10 and the support 12 was non-alkali glass.

The edge of the glass substrate 10 after the peeling process was observed with an optical microscope for cracks and chips, and the number of glass substrates 10 that were deemed NG (NG number) was calculated. When calculating the number of NG, a glass substrate 10 that was found to have even one crack or chip was deemed NG.

Example 2
Twenty glass substrates 10 were manufactured similarly to those manufactured in Example 1, except that the X-direction length and the Y-direction length of the glass substrate 10 were changed to 320 mm and 400 mm, respectively. For these glass substrates 10, the NG number was calculated by the same method as in Example 1.

(Comparative Example 1)
Twenty glass substrates were manufactured similarly to those manufactured in Example 1, except that the cutting process of the four sides of the glass substrate 10 in the seventh step was omitted. The number of defective glass substrates was calculated for these glass substrates in the same manner as in Example 1.

(Comparative Example 2)
Twenty glass substrates were manufactured similarly to those manufactured in Example 2, except that the cutting process of the four sides of the glass substrate 10 in the seventh step was omitted. The number of defective glass substrates was calculated in the same manner as in Example 2 for these glass substrates.

(result)
The results are shown in Table 1 below.

As shown in Table 1, when cutting was performed on all four sides of the glass substrate 10, a smaller number of NGs was achieved, regardless of the size of the glass substrate 10, than in Comparative Examples 1 and 2, in which no cutting was performed. In Comparative Examples 1 and 2, snagging occurred during peeling, which became the starting point for NGs with a relatively high frequency. In contrast, in Examples 1 and 2, in which cutting was performed, a number of 0 NGs was achieved, regardless of the size of the glass substrate 10.

As described above, by implementing the present invention, chipping, cracking, etc. of the glass substrate can be reduced, and the glass substrate can be stably peeled off from the support.

1...wiring board, 10, 10s...glass substrate, 11...adhesive layer, 12...support, 13...modified portion, 14...adhesive layer, 15...support, 20...first conductor layer, 21...hydrofluoric acid-resistant metal layer, 22...metal layer, 30...capacitor, 31...dielectric layer, 32...upper electrode, 40, 40s, 41, 41s, 42, 42s...interlayer insulating film, 50...build-up layer, 51, 52...conductor layer, 60, 60s... Insulating layer, 70... conductor layer, 80... second conductor layer, 90, 90s, 91, 91s, 92, 92s... interlayer insulating film, 100... build-up layer, 101, 102... conductor layer, 110, 110s... insulating layer, 120... conductor layer, 200, 210... deposit, S1... first surface, S2... second surface, IR... center, OR... outer periphery, ER, ER1, ER2... end, N... peeling start point, HR... through hole.

Claims (12)

a first support is attached to a second surface side of a glass substrate having a first surface and a second surface opposed to each other, the first surface side including a first region in which a first conductor layer is formed, a second region surrounding the first region, and a third region surrounding the second region and including an end portion of the first surface;
forming the first conductor layer on the first surface side;
removing a first deposit including the first conductor layer, the first deposit being deposited on at least a portion of a side surface of the glass substrate and the first support;
and separating the first support from the glass substrate.
A method for manufacturing a wiring board. In removing the first deposit, the first deposit and a third region of the glass substrate are removed.
A method for manufacturing the wiring board according to claim 1. The third region of the glass substrate is removed by a dicing process.
The method for manufacturing the wiring board according to claim 2. the third region of the glass substrate is removed by laser light irradiation;
The method for manufacturing the wiring board according to claim 2. The third region of the glass substrate is removed by a scribing process and a breaking process.
The method for manufacturing the wiring board according to claim 2. The width of the third region is greater than 0 mm and less than or equal to 1 mm.
The method for manufacturing the wiring board according to claim 2. In removing the first deposit, the first deposit is removed by laser light irradiation.
A method for manufacturing the wiring board according to claim 1. In removing the first deposit, the first deposit and a third region of the glass substrate are removed, and the first support is not removed.
A method for manufacturing the wiring board according to claim 1. forming a first insulating layer on the first surface;
the first deposit further comprises the first insulating layer;
A method for manufacturing the wiring board according to claim 1. irradiating the glass substrate to which the first support is attached with a laser to form a modified portion on the glass substrate;
and performing an etching process on the modified portion to form a through hole in the glass substrate.
A method for manufacturing the wiring board according to claim 1. bonding a second support to the first surface side of the glass substrate;
forming a second conductor layer on the second surface side;
removing a second deposit that is deposited on at least a portion of a side surface of the glass substrate and the second support and includes the second conductor layer;
and separating the second support from the glass substrate.
A method for manufacturing the wiring board according to claim 1. the glass substrate further includes a fourth region provided between the second region and the third region,
In removing the second deposit, the second deposit and a fourth region of the glass substrate are removed.
The method for manufacturing the wiring board according to claim 11.