JP2024062689A - Method for manufacturing wiring board - Google Patents

Abstract

A support is stably peeled off from a glass substrate while suppressing damage to the glass substrate.
[Solution] A method for manufacturing a wiring board includes providing a first support 12 on a second surface S2 side of a glass substrate 10 having a first surface S1 and a second surface S2 opposing each other, forming a first conductor layer 20 on the first surface S1 side of the glass substrate 10 on which the first support 12 is provided, performing a first etching process to form a groove G between the glass substrate 10 and the first support 12 at the end face of the glass substrate 10 on which the first support 12 is provided, and separating the first support 12 from the glass substrate 10 on which the first conductor layer 20 is formed, using the groove G as a starting point for separation.
[Selected figure] Figure 8

Description

The present invention relates to a method for manufacturing a wiring board.

Electronic devices are becoming more functional and smaller. Accordingly, even higher precision is required for multilayer wiring boards, such as interposers, that are mounted on electronic devices. An interposer is a multilayer wiring board with through electrodes that penetrate the core material. Interposers have the function of relaying components with different inter-terminal distances, such as integrated circuit (IC) chips and printed circuit boards, which have different wiring design rules, via through electrodes.

In recent years, glass interposers that use a glass substrate as the core material have been attracting attention. Glass interposers have low manufacturing costs because they are obtained by forming through electrodes and other elements on an inexpensive, large-area glass substrate and then dicing it into individual pieces. On the other hand, as the glass substrate becomes thinner, it is more susceptible to damage such as cracks occurring during manufacturing. To prevent such damage, a method has been proposed of reinforcing the glass substrate with a support.

For example, Patent Document 1 describes a method in which a support is attached to a glass substrate via a peeling layer, and the support is peeled off and removed after the formation of wiring. Specifically, first, a first wiring is formed on a first surface of the glass substrate. Next, the first wiring side of the glass substrate on which the first wiring is formed is supported by a support. Then, a modified portion that serves as a starting point for the formation of a through hole is formed on the glass substrate by irradiating the glass substrate from the surface opposite to the first surface with laser light. Next, etching is performed using hydrofluoric acid from the surface opposite to the first surface of the glass substrate toward the first surface, and the glass substrate is thinned while the through hole is formed. Next, after the through hole is formed, a through electrode is formed inside the through hole, and a second wiring is formed on the surface opposite to the first surface of the glass substrate, and the first wiring and the second wiring are connected via the through electrode. Then, after the second wiring is formed, the support is separated from the glass substrate. In this way, problems such as cracking of the glass substrate during manufacturing are suppressed.

Patent Document 2 describes a process for laminating a support onto a glass substrate. On the other hand, Patent Document 2 does not describe a process for peeling the support from the glass substrate.

Patent Document 3 describes a process for peeling the support from the glass substrate. However, Patent Document 3 does not describe a method for peeling the support or any concerns that may arise during peeling.

International Publication No. 2019/235617 Patent No. 7011215 Patent No. 6176253

When peeling the support from the glass substrate, there is a possibility that unintended chipping or cracking may occur in the glass substrate. For this reason, it is difficult to stably peel the support without damaging the glass substrate.

The present invention aims to provide a technology that can stably peel a support from a glass substrate while minimizing damage to the glass substrate.

According to one aspect of the present invention, there is provided a method for manufacturing a wiring substrate, comprising: providing a first support on the second surface side of a glass substrate having a first surface and a second surface opposed to each other; forming a first conductor layer on the first surface side of the glass substrate on which the first support is provided; performing a first etching process to form a groove between the glass substrate and the first support at the end surface of the glass substrate on which the first support is provided; and separating the first support from the glass substrate on which the first conductor layer is formed, using the groove as a starting point for separation.

According to another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, in which the separating step includes pressing a jig having a tapered tip so that the tip is positioned within the groove, and applying a force in a direction that pulls the glass substrate and the first support apart from each other.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring substrate according to the above aspect, in which the separating step includes pressing a jig having a tapered tip so that the tip is positioned within the groove, and introducing a fluid between the glass substrate and the first support from the position of the groove.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, further comprising providing a second support on the first surface side of the glass substrate on which the first conductor layer is formed before separating the first support.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, further comprising forming a second conductor layer on the second surface side of the glass substrate from which the first support has been separated, and separating the second support from the glass substrate on which the second conductor layer has been formed.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, further comprising at least one of forming a first build-up layer on the first surface side of the glass substrate from which the second support is separated, and forming a second build-up layer on the second surface side of the glass substrate from which the second support is separated.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, further comprising: irradiating a glass substrate on which the first support is provided with laser light to form a modified portion on the glass substrate; and performing a second etching process on the glass substrate from which the first support has been separated to form a through hole at the position of the modified portion.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, further comprising forming a second conductor layer on the second surface side of the glass substrate in which the through hole is formed, the second conductor layer including a portion provided on the second surface, a portion provided on the side wall of the through hole, and a portion of the first conductor layer that contacts the portion covering the through hole.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to the above aspect, in which the first conductor layer includes a copper layer and a hydrofluoric acid-resistant metal layer provided between the glass substrate and the copper layer and in contact with the second conductor layer.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to any of the above aspects, in which the first support is directly bonded to the glass substrate.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to any of the above aspects, in which the first support is bonded to the glass substrate via an adhesive layer.

According to yet another aspect of the present invention, a method for manufacturing a wiring board is provided in which the first support is larger than the glass substrate when viewed in a direction intersecting the first surface and the second surface.

According to yet another aspect of the present invention, there is provided a method for manufacturing a wiring board according to any of the above aspects, in which the depth of the groove is 10 μm or more and 5 mm or less.

The present invention provides a technology that can stably peel off a support from a glass substrate while minimizing damage to the glass substrate.

FIG. 1 is a cross-sectional view of a wiring board according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view showing a part of the wiring board shown in FIG. FIG. 3 is a plan view showing a glass substrate used in manufacturing the wiring board shown in FIG. FIG. 4 is a cross-sectional view showing one step in the method of manufacturing the wiring board shown in FIG. 5 is a cross-sectional view showing another step in the method for manufacturing the wiring board shown in FIG. FIG. 6 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 7 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 8 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 9 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 10 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 11 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 12 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. 13 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. 14 is a cross-sectional view showing still another step in the method for manufacturing the wiring board shown in FIG. FIG. 15 is a cross-sectional view showing a step in the method for manufacturing a wiring board according to the first modification. FIG. 16 is a cross-sectional view showing a step in a method for manufacturing a wiring board according to the second modification.

Below, an embodiment of the present invention will be described with reference to the drawings. The embodiment described below is a more specific embodiment of any of the above aspects. The items described below can be incorporated into each of the above aspects, either alone or in combination.

The embodiments shown below are merely examples of configurations for embodying the technical idea of the present invention, and the technical idea of the present invention is not limited by the materials, shapes, structures, etc. of the components described below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In addition, elements having the same or similar functions are given the same reference symbols in the drawings referred to below, and duplicate explanations will be omitted. In addition, the drawings are schematic, and the relationship between dimensions in one direction and dimensions in another direction, and the relationship between the dimensions of one component and the dimensions of another component, etc. may differ from the actual ones.

<1> Embodiment <1.1> Wiring Board Fig. 1 is a cross-sectional view of a wiring board according to an embodiment of the present invention Fig. 2 is an enlarged cross-sectional view of a part of the wiring board shown in Fig. 1 .

The wiring board 1 is a glass core wiring board. The wiring board 1 is connected to, for example, a printed wiring board or a silicon chip (not shown). The example in FIG. 1 shows a case where the wiring board 1 is a wiring board used as an interposer, that is, a glass interposer.

The wiring board 1 includes a glass substrate 10s, a first conductor layer 20, a dielectric layer 31, an upper electrode 32, an interlayer insulating film 40s, a build-up layer 50, an insulating layer 60s, a conductor layer 70, a second conductor layer 80, an interlayer insulating film 90s, a build-up layer 100, an insulating layer 110s, and a conductor layer 120. A capacitor 30 is built into the wiring board 1. An inductor (not shown) may also be built into the wiring board 1.

The glass substrate 10s is a transparent glass material having optical transparency. The components of the glass substrate 10s and the mixing ratio of the components are not particularly limited. An example of the glass substrate 10s is a glass material mainly composed of silicate, but other glass materials may also be used. Specific examples of the glass substrate 10s include non-alkali glass, alkali glass, borosilicate glass, quartz glass, sapphire glass, photosensitive glass, etc., with non-alkali glass being more preferable.

The thickness of the glass substrate 10s is preferably in the range of 50 μm or more and 150 μm or less. When the wiring substrate 1 is connected to a silicon chip, the linear expansion coefficient of the glass substrate 10s is determined taking into consideration the difference in linear expansion coefficient with the silicon chip. In this case, the linear expansion coefficient of the glass substrate 10s is preferably in the range of 0.5 ppm/K or more and 8.0 ppm/K or less, and more preferably in the range of 1.0 ppm/K or more and 4.0 ppm/K or less.

The glass substrate 10s has a first surface S1 and a second surface S2 that face each other. The first surface S1 and the second surface S2 are parallel to each other. The glass substrate 10s has one or more through holes, here a plurality of through holes, each of which extends from the first surface S1 to the second surface S2. Each of the through holes tapers from the second surface S2 to the first surface S1.

In the following, the plane parallel to the first surface S1 and the second surface S2 is referred to as the XY plane. The directions that intersect with each other in the XY plane are referred to as the X direction and the Y direction. The direction that intersects with the XY plane is referred to as the Z direction. In the Z direction, the direction from the second surface S2 to the first surface S1 is also referred to as the upward direction. In the Z direction, the direction from the first surface S1 to the second surface S2 is also referred to as the downward direction. The first surface S1 is also referred to as the front surface or upper surface of the glass substrate 10s. The second surface S2 is also referred to as the back surface or lower surface of the glass substrate 10s.

The first conductor layer 20 is a conductor pattern provided on the first surface S1. This conductor pattern includes a land portion, a wiring portion, and a lower electrode of the capacitor 30. The first conductor layer 20 is the first wiring layer.

The first conductor layer 20 has a multi-layer structure. Specifically, the first conductor layer 20 includes a metal layer 22 facing the first surface S1 and a hydrofluoric acid-resistant metal layer 21 interposed between the metal layer 22 and the glass substrate 10.

The hydrofluoric acid-resistant metal layer 21 covers the opening of the through hole on the first surface S1 side provided in the glass substrate 10s. The hydrofluoric acid-resistant metal layer 21 is made of a metal material that has superior resistance to etching by hydrofluoric acid compared to the glass substrate 10s. The hydrofluoric acid-resistant metal layer 21 is, for example, an alloy layer obtained from the group consisting of Cr and Ni. The thickness of the hydrofluoric acid-resistant metal layer 21 is preferably in the range of 10 nm to 1000 nm.

The metal layer 22 is provided on the hydrofluoric acid resistant metal layer 21. The metal layer 22 is, for example, a seed layer and a copper layer laminated in this order. The material of the seed layer is appropriately selected from the group consisting of, for example, Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, and _Cu3N4 . The thickness of the seed layer is preferably in the range of 100 nm to ₁₀₀₀ nm, more preferably in the range of 100 nm to 500 nm. The thickness of the copper layer is preferably in the range of 2 μm to 20 μm. The seed layer is provided when the copper layer is formed by electrolytic plating. When the copper layer is formed by other methods such as electroless plating or sputtering, the seed layer may be omitted.

The dielectric layer 31 and the upper electrode 32 are stacked in this order on a portion of the first conductor layer 20. The portion of the first conductor layer 20 facing the upper electrode 32 is the lower electrode. The upper electrode 32, the dielectric layer 31, and the lower electrode form the capacitor 30, specifically, the MIM capacitor.

From the viewpoint of insulation and dielectric constant, the dielectric layer 31 can be made of at least one material selected from alumina, silica, silicon nitride, tantalum oxide, titanium oxide, calcium titanate, barium titanate, and strontium titanate. The thickness of the dielectric layer 31 is preferably in the range of 10 nm to 5 μm, and more preferably in the range of 50 nm to 1 μm. If the thickness of the dielectric layer 31 is less than 10 nm, it is difficult to maintain insulation, and the function as a capacitor may not be expressed. If the thickness of the dielectric layer 31 is more than 5 μm, the manufacturing process described below takes time and is not suitable for mass production.

The upper electrode 32 is, for example, provided with a seed layer and a metal layer in this order. The metal layer provided on the seed layer of the upper electrode 32 can be made of copper, nickel, chromium, palladium, gold, rhodium, iridium, etc. From the viewpoints of electrical conductivity and cost, copper is preferably used as the metal layer provided on the seed layer of the upper electrode 32.

In the example shown in FIG. 1, the lower electrode covers the opening on the first surface S1 side of the through hole provided in the glass substrate 10s. The lower electrode may be spaced apart from the through hole provided in the glass substrate 10s. When the lower electrode is provided so as to cover the opening on the first surface S1 side of the through hole provided in the glass substrate 10s, it is possible to reduce the electrical resistance caused by the wiring and shorten the wiring length.

Note that here, the capacitor 30 is installed facing the first surface S1, but the capacitor may be installed on the second surface S2 side. Alternatively, the capacitor 30 may be grounded facing the first surface S1, and another capacitor may be further installed on the second surface S2 side. The capacitor 30 may be omitted.

The interlayer insulating film 40s has a multi-layer structure. Specifically, the interlayer insulating film 40s is made up of interlayer insulating films 41s and 42s stacked in this order.

The build-up layer 50 has a wiring structure of one or more layers. In the example of FIG. 1, the build-up layer 50 has a two-layer stacked wiring structure. Specifically, the build-up layer 50 has conductor layers 51 and 52 stacked in this order. The build-up layer 50 is the first build-up layer.

The interlayer insulating film 41s covers the first surface S1 and embeds the first conductor layer 20, the dielectric layer 31, and the upper electrode 32. The interlayer insulating film 41s has through holes at the positions of the land portions included in the first conductor layer 20 and at the position of the upper electrode 32. According to one example, the interlayer insulating film 41s is an insulating resin layer. As the insulating resin layer, a liquid resin or a film-like resin in which a filler is filled in a thermosetting resin is mainly used. As the thermosetting resin, it is preferable to include at least one type of material from among epoxy resin, polyimide resin, and polyamide resin. As the filler, it is preferable to include a material such as silica, titanium oxide, and urethane.

The conductor layer 51 is a conductor pattern provided on the interlayer insulating film 41s. This conductor pattern includes a land portion and a wiring portion provided on the main surface of the interlayer insulating film 41s, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 41s. Each of the via portions included in the conductor layer 51 connects the land portion or the upper electrode 32 included in the first conductor layer 20 to the land portion included in the conductor layer 51.

The conductor layer 51 includes a seed layer and a copper layer. The seed layer and copper layer included in the conductor layer 51 are stacked in this order on the interlayer insulating film 41s. The seed layer included in the conductor layer 51 can be made of the materials exemplified for the seed layer included in the first conductor layer 20 described above.

The interlayer insulating film 42s covers the upper surface of the interlayer insulating film 41s and embeds the land portion and wiring portion included in the conductor layer 51. The interlayer insulating film 42s has a through hole at the position of the land portion included in the conductor layer 51. According to one example, the interlayer insulating film 42s is an insulating resin layer. The insulating resin layer included in the interlayer insulating film 42s can be made of the materials exemplified for the insulating resin layer included in the interlayer insulating film 41s described above.

The conductor layer 52 is a conductor pattern provided on the interlayer insulating film 42s. This conductor pattern includes a pad portion and a wiring portion provided on the main surface of the interlayer insulating film 42s, and a via portion covering the sidewall of a through hole provided in the interlayer insulating film 42s. Each of the via portions included in the conductor layer 52 connects a land portion included in the conductor layer 51 to a pad portion included in the conductor layer 52.

The conductor layer 52 includes a seed layer and a copper layer. The seed layer and copper layer included in the conductor layer 52 are stacked in this order on the interlayer insulating film 42s. The seed layer included in the conductor layer 52 can be made of the materials exemplified for the seed layer included in the first conductor layer 20 described above.

The insulating layer 60s at least partially covers the interlayer insulating film 42s and embeds the pad portion and wiring portion included in the conductor layer 52. The insulating layer 60s has a through hole at the position of the pad portion included in the conductor layer 52. The insulating layer 60s is made of, for example, solder resist.

The conductor layer 70 is a bump for connecting the front side of the wiring board 1 to an external printed wiring board. The conductor layer 70 has a portion above the insulating layer 60s. The conductor layer 70 is made of, for example, solder.

The second conductor layer 80 is a conductor pattern including a portion covering the second surface S2 of the glass substrate 10s, a portion covering the sidewall of the through hole provided in the glass substrate 10s, and a portion of the first conductor layer 20 that contacts the portion covering the through hole provided in the glass substrate 10s. This conductor pattern includes a land portion, a wiring portion, and a via portion. The portion of the second conductor layer 80 that covers the second surface S2 is the second conductor layer and includes a land portion and a wiring portion. The via portion included in the second conductor layer 80 is composed of a portion of the second conductor layer 80 that covers the sidewall of the through hole provided in the glass substrate 10s, and a portion of the first conductor layer 20 that contacts the portion covering the through hole provided in the glass substrate 10s.

The second conductor layer 80 covers the sidewalls of the through holes in the glass substrate 10s, the portion of the first conductor layer 20 that covers the through holes in the glass substrate 10s, and the area of the second surface S2 that surrounds the opening on the second surface S2 side of the through holes in the glass substrate 10s. The second conductor layer 80 is conformal to these surfaces.

The second conductor layer 80 has a multi-layer structure. Specifically, the second conductor layer 80 includes a seed layer and a copper layer. The seed layer and copper layer included in the second conductor layer 80 are laminated in this order on the glass substrate 10s. The seed layer included in the second conductor layer 80 can be made of the materials exemplified for the seed layer included in the first conductor layer 20 described above.

The interlayer insulating film 90s has a multi-layer structure. Specifically, the interlayer insulating film 90s is formed by stacking interlayer insulating films 91s and 92s in this order.

The build-up layer 100 has a wiring structure of one or more layers. In the example of FIG. 1, the build-up layer 100 has a two-layer stacked wiring structure. Specifically, the build-up layer 100 has conductor layers 101 and 102 stacked in this order. The build-up layer 100 is the second build-up layer.

The interlayer insulating film 91s covers the second surface S2 and embeds the second conductor layer 80. The interlayer insulating film 91s has a through hole at the position of the land portion included in the second conductor layer 80. According to one example, the interlayer insulating film 91s is an insulating resin layer. The insulating resin layer included in the interlayer insulating film 91s can be made of the materials exemplified for the insulating resin layer included in the interlayer insulating film 41s described above.

The conductor layer 101 is a conductor pattern provided on the interlayer insulating film 91s. This conductor pattern includes a land portion and a wiring portion provided on the main surface of the interlayer insulating film 91s, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 91s. Each of the via portions included in the conductor layer 101 connects a land portion included in the second conductor layer 80 to a land portion included in the conductor layer 101.

The conductor layer 101 includes a seed layer and a copper layer. The seed layer and copper layer included in the conductor layer 101 are stacked in this order on the interlayer insulating film 91s. The seed layer included in the conductor layer 101 can be made of the materials exemplified for the seed layer included in the first conductor layer 20 described above.

The interlayer insulating film 92s covers the lower surface of the interlayer insulating film 91s and embeds the land portion and wiring portion included in the conductor layer 101. The interlayer insulating film 92s has a through hole at the position of the land portion included in the conductor layer 101. According to one example, the interlayer insulating film 92s is an insulating resin layer. The insulating resin layer included in the interlayer insulating film 92s can be made of the materials exemplified for the insulating resin layer included in the interlayer insulating film 41s described above.

The conductor layer 102 is a conductor pattern provided on the interlayer insulating film 92s. This conductor pattern includes a pad portion and a wiring portion provided on the main surface of the interlayer insulating film 92s, and a via portion covering the side wall of a through hole provided in the interlayer insulating film 92s. Each of the via portions included in the conductor layer 102 connects a land portion included in the conductor layer 101 to a pad portion included in the conductor layer 102.

The conductor layer 102 includes a seed layer and a copper layer. The seed layer and copper layer included in the conductor layer 102 are stacked in this order on the interlayer insulating film 92s. The seed layer included in the conductor layer 102 can be made of the materials exemplified for the seed layer included in the first conductor layer 20 described above.

The insulating layer 110s at least partially covers the interlayer insulating film 92s and embeds the pad portion and wiring portion included in the conductor layer 102. The insulating layer 110s has a through hole at the position of the pad portion included in the conductor layer 102. The insulating layer 110s is made of, for example, solder resist.

The conductor layer 120 is a bump for connecting the back side of the wiring board 1 to an external printed wiring board. The conductor layer 120 has a portion below the insulating layer 110s. The conductor layer 120 is made of, for example, solder.

<1.2> Method for Manufacturing Wiring Board The above-mentioned wiring board 1 can be manufactured, for example, by the following method.

Figure 3 is a plan view showing a glass substrate used in the manufacture of the wiring board shown in Figure 1. Figures 4 to 14 are cross-sectional views showing a step in the manufacturing method of the wiring board shown in Figure 1. Of these, Figures 4 to 7 and Figures 9 to 14 are cross-sectional views taken along line A-A in Figure 3. Figure 8 is a cross-sectional view showing an enlarged end of the composite shown in Figure 7.

<1.2.1> First step First, a glass substrate 10 having a first surface S1 as a front surface and a second surface S2 as a back surface is prepared. For example, contaminants are removed from the front surface of a non-alkali glass plate by ultrasonic cleaning or the like to obtain the glass substrate 10.

The manufacturing method of the glass substrate 10 is not particularly limited. Examples of manufacturing methods of the glass substrate 10 include the float method, the down-draw method, the fusion method, the up-draw method, and the roll-out method.

As shown in FIG. 3, the glass substrate 10 is a large-sized glass substrate having larger dimensions in the X and Y directions compared to the glass substrate 10s. When viewed in the Z direction, the glass substrate 10 has a central portion IR and end portions OR. The central portion IR is a region in which a plurality of glass substrates 10s are arranged in a matrix. The end portions OR are regions outside the central portion IR and include the ends of the glass substrate 10. The thickness of the glass substrate 10 is preferably in the range of 75 μm or more and 200 μm or less.

4, the support 12 is bonded to the second surface S2 via the adhesive layer 11. In order to bond the support 12 to the glass substrate 10, for example, a laminator, a vacuum pressure press, a reduced pressure bonding machine, or the like can be used.

The adhesive layer 11 is an adhesive layer for temporarily fixing the support 12 to the glass substrate 10. The adhesive layer 11 is, for example, a functional group formed on the second surface S2. An example of the functional group used as the adhesive layer 11 is a hydroxyl group.

For ease of explanation, in Figs. 4 to 14, the adhesive layer 11 is illustrated as a layer having a thickness. However, when a functional group formed on the second surface S2 is used as the adhesive layer 11, the thickness of the adhesive layer 11 is negligibly small compared to the glass substrate 10 and the support 12. For this reason, the adhesive layer 11 can also be expressed as an interface between the glass substrate 10 and the support 12. In this case, the support 12 can also be expressed as being directly bonded to the glass substrate 10.

The support 12 is the first support, and is a thin-plate carrier. From the viewpoint of adhesion, it is desirable that the support 12 is made of the same material as the glass substrate 10. That is, when the glass substrate 10 is made of alkali-free glass, it is preferable that the support 12 is also made of alkali-free glass. The thickness of the support 12 may be set appropriately according to the thickness of the glass substrate 10. In consideration of the transportability of the glass substrate 10, it is preferable that the thickness of the support 12 is within the range of 300 μm or more and 1500 μm or less.

<1.2.3> Third step Next, the glass substrate 10 is irradiated with laser light to form one or more modified portions 13 on the glass substrate 10. The irradiation direction of the laser light may be from the first surface S1 to the second surface S2, or from the second surface S2 to the first surface S1.

The modified portion 13 is, for example, a portion that is heated by laser irradiation, resulting in a difference in crystallinity, etc., between the modified portion 13 and a portion not irradiated with laser light. The modified portion 13 is formed at a position corresponding to a through hole to be formed in the glass substrate 10. The modified portion 13 extends, for example, in the Z direction. When the modified portion 13 is formed from the first surface S1 toward the second surface S2, the modified portion 13 may be formed to reach the adhesive layer 11 and the support 12, as shown in FIG. 5.

The wavelength of the laser light used here is 535 nm or less. The preferred wavelength of the laser light is 355 nm or more and 535 nm or less. If the wavelength of the laser light is less than 355 nm, it may be difficult to obtain sufficient laser output, and stable laser modification may be difficult. On the other hand, if the wavelength of the laser light is greater than 535 nm, the irradiation spot becomes large, making small-area laser modification difficult. In addition, microcracks may occur due to the influence of heat, making the glass substrate 10 more likely to break.

When using a pulsed laser, it is desirable for the laser pulse width to be in the range of picoseconds to femtoseconds. If the laser pulse width is nanoseconds or longer, it becomes difficult to control the amount of energy per pulse, and microcracks occur, making the glass substrate 10 more likely to break.

The energy of the laser pulse is selected to a preferred value depending on the glass composition and the type of laser modification to be produced, and is preferably in the range of 5 μJ to 150 μJ. By increasing the energy of the laser pulse, it is possible to increase the length of the modified portion 13 in proportion to the energy of the laser pulse.

<1.2.4> Fourth Step Next, as shown in FIG. 6 , a first conductor layer 20 is formed on the first surface S1 so as to cover the modified portion 13.

For example, first, the hydrofluoric acid resistant metal layer 21 and the seed layer included in the metal layer 22 are formed in this order on the first surface S1. Here, each of the hydrofluoric acid resistant metal layer 21 and the seed layer is formed as a continuous film. The hydrofluoric acid resistant metal layer 21 is formed, for example, by sputtering. The seed layer is formed, for example, by sputtering or electroless plating.

Next, the first conductor layer 20 as shown in FIG. 6 is obtained, for example, by a semi-additive process (SAP).

Specifically, first, a mask pattern with openings at positions corresponding to the copper layer contained in the metal layer 22 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. According to one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and stripped off. Next, the entire surface of the copper layer side of the composite including the copper layer and the glass substrate 10 is etched until the exposed portion of the seed layer is removed.

In this manner, the first conductor layer 20 is obtained. As described above, the first conductor layer 20 includes a land portion, a wiring portion, and a lower electrode.

<1.2.5> Fifth step Next, a dielectric layer 31 and an upper electrode 32 are formed in this order on the lower electrode included in the first conductor layer 20 to obtain the capacitor 30 shown in Fig. 6. The upper electrode 32 can be formed, for example, by the same method as described above for the seed layer and copper layer included in the first conductor layer 20.

Then, an interlayer insulating film 41 is provided on the surface of the composite including the capacitor 30 and the glass substrate 10 facing the capacitor 30. In the case of a liquid resin, the interlayer insulating film 41 is formed by a spin coating method. In the case of a film-like resin, the interlayer insulating film 41 is formed by heating and pressurizing under a vacuum using a vacuum laminator. In one example, the interlayer insulating film 41 is formed by laminating ABF-GXT31 (32.5 μm thick), an insulating resin film manufactured by Ajinomoto Fine-Techno Co., Ltd., onto the above surface and pre-curing it.

7, the composite including the glass substrate 10 and the interlayer insulating film 41 is supported on the support 15. Here, the composite and the support 15 are bonded together via the adhesive layer 14 so that the interlayer insulating film 41 of the composite faces the support 15.

For the adhesive layer 14, a resin or a functional group formed on the support 15 is used. Examples of resins include resins that absorb light such as UV light and become peelable by generating heat, sublimating, or changing in quality, resins that become peelable by foaming due to heat, resins whose adhesion changes depending on temperature, adhesive resins, etc. According to one example, Riva Alpha (registered trademark) manufactured by Nitto Denko Corporation is used for the adhesive layer 14.

The support 15 is a second support and is a thin-plate carrier. It is preferable that the support 15 is made of the same material as the glass substrate 10. That is, when the glass substrate 10 is made of alkali-free glass, it is preferable that the support 15 is also made of alkali-free glass. The thickness of the support 15 may be set appropriately according to the thickness of the glass substrate 10. In consideration of the transportability of the glass substrate 10, it is preferable that the thickness of the support 15 is within a range of 300 μm or more and 1500 μm or less.

<1.2.7> Seventh step Next, the composite supported on the support 15 is immersed in an etching solution to perform an etching process. The etching process in the seventh step is the first etching process. As a result, the glass substrate 10, the adhesive layer 11, and a part of the support 12 are removed. In addition, scratches such as microcracks that have occurred on the glass substrate 10 and the support 12 in the various steps so far are removed. Note that the etching solution easily permeates between the glass substrate 10 including the adhesive layer 11 and the support 12, so the etching rate is higher than other parts. Therefore, at the end surface of the glass substrate 10 where the support 12 is provided, a groove G that becomes the starting point of peeling is formed between the glass substrate 10 and the support 12 as shown in FIG. 8.

Groove G extends along the XY plane from the end of the composite toward the inside of the composite. Groove G can be observed through the glass substrate 10 or the support 12 with a microscope or the like. Groove G can also be observed by directly observing the end of the composite with a stereomicroscope or the like, or by breaking it and observing it with an electron microscope or the like. Groove G can be observed on all four sides of the composite, but it is sufficient that it is formed at the site from which peeling begins.

The depth P of the groove G is preferably in the range of 10 μm or more and 5 mm or less, and more preferably in the range of 50 μm or more and 500 μm or less. If the depth P is less than 10 μm, it is inappropriate because it is difficult to make the groove G function as a starting point for peeling. If the depth P is more than 5 mm, it is not useful because the etching process will proceed excessively, resulting in a reduction in the dimensions of the glass substrate 10 and increased damage to other components by the etching solution.

The etching solution is preferably a solution capable of dissolving and removing glass, such as hydrofluoric acid. In addition, an etching solution with high permeability is more preferable, since it allows grooves G to be formed in a shorter period of time. The concentration, temperature, additives, etc. of the etching solution can be appropriately adjusted according to the size and glass composition of the glass substrate 10 and support 12. This allows the amount of penetration between the glass substrate 10 and support 12, and the amount of etching, to be controlled to appropriate values.

9, the adhesive layer 11 and the support 12 are separated from the glass substrate 10. When separating the adhesive layer 11 and the support 12 from the glass substrate 10, a mechanical load is applied to the groove G, so that the peeling can proceed with the groove G as a physical starting point.

More specifically, a scribing process is performed on the groove G. The scribing process involves pressing a jig having a tapered tip, such as a razor blade, against the groove G so that the tip is positioned within the groove G. Then, with the jig pressed against the groove G, a force is applied in a direction that pulls the glass substrate 10 and the support 12 away from each other. Alternatively, with the jig pressed against the groove G, a fluid such as liquid or gas may be introduced between the glass substrate 10 and the support 12 from the position of the groove G. This allows the support 12 to be separated from the glass substrate 10 more smoothly.

If residual adhesive layer 11 remains on glass substrate 10 after peeling process of adhesive layer 11 and support 12, plasma cleaning, ultrasonic cleaning, water cleaning, solvent cleaning using alcohol, etc. may be performed.

<1.2.9> Ninth step Next, the second surface S2 of the glass substrate 10 from which the adhesive layer 11 and the support 12 have been peeled off is etched with an etching solution containing hydrogen fluoride. The etching process in the ninth step is a second etching process. As a result, as shown in FIG. 10, the second surface S2 is retracted and through holes H are formed at the positions of the modified portions 13. The modified portions 13 of the glass substrate 10 have a higher etching rate than other portions. Therefore, this etching process can simultaneously thin the glass substrate 10 and form the through holes H.

The amount of etching by the etching process is appropriately set according to the thickness of the glass substrate 10. For example, if the thickness of the glass substrate 10 before the etching process is 200 μm, it is preferable that the amount of etching of the glass substrate 10 is within a range of 50 μm or more and 150 μm or less. This allows the thickness of the glass substrate 10 after the etching process to be within a range of 50 μm or more and 150 μm or less.

In this etching process, the hydrofluoric acid resistant metal layer 21 serves as an etching stopper film. In addition, the through hole H obtained by the above etching has a truncated cone shape in which the diameter (or cross-sectional area) on the second surface S2 side is larger than the diameter (or cross-sectional area) on the first surface S1 side in FIG. 10.

The etching solution containing hydrogen fluoride is, for example, an aqueous solution of hydrogen fluoride. The etching solution may further contain one or more inorganic acids selected from the group consisting of nitric acid, hydrochloric acid, and sulfuric acid.

The hydrogen fluoride concentration of the etching solution is, for example, in the range of 1.0% by mass to 6.0% by mass, and preferably in the range of 2.0% by mass to 5.0% by mass. The inorganic acid concentration is, for example, in the range of 1.0% by mass to 20.0% by mass, and preferably in the range of 3.0% by mass to 16.0% by mass. It is desirable to perform the etching process at an etching rate of 1.0 μm/min or less using an etching solution in which the concentrations of each component are set within the above ranges. It is desirable to keep the temperature of the etching solution during the etching process in the range of 10°C to 40°C.

<1.2.10> Tenth Step Next, the second conductor layer 80 is formed to cover the through hole H.

Specifically, first, the seed layer included in the second conductor layer 80 is formed as a continuous film that covers the sidewall of the through hole H, the surface of the hydrofluoric acid-resistant metal layer 21 exposed by the etching process, and the second surface S2. The seed layer is formed, for example, by sputtering or electroless plating.

Next, the second conductor layer 80 as shown in FIG. 11 is obtained, for example, by a semi-additive process.

Specifically, first, a mask pattern with openings at positions corresponding to the copper layer included in the second conductor layer 80 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. In one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and stripped off. Next, the entire surface of the copper layer side of the composite including the copper layer and the glass substrate 10 is etched until the exposed portion of the seed layer is removed.

In this manner, the second conductor layer 80 is obtained. As described above, the second conductor layer 80 includes a land portion and a wiring portion.

Next, a process similar to the process for forming the interlayer insulating film 41 in the fifth step is performed on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the second conductor layer 80, to provide an interlayer insulating film 91. The interlayer insulating film 91 may be formed of a material different from that of the interlayer insulating film 41.

12, the adhesive layer 14 and the support 15 are separated from the composite including the glass substrate 10, the first conductor layer 20, the second conductor layer 80, etc. When separating the adhesive layer 14 and the support 15, a peeling method such as UV light irradiation, heat treatment, physical peeling, etc. is appropriately selected depending on the material of the adhesive layer 14.

If residual adhesive layer 14 remains on interlayer insulating film 41 after peeling process of adhesive layer 14 and support 15, plasma cleaning, ultrasonic cleaning, water cleaning, solvent cleaning using alcohol, etc. may be performed.

<1.2.12> Twelfth Step Next, as shown in FIG. 13, the build-up layer 50 is provided on the first surface S1 side, and the build-up layer 100 is provided on the second surface S2 side.

The order in which the build-up layers 50 and 100 are formed is arbitrary. The process for forming the build-up layers 50 and 100 is the same except that the surfaces on which they are formed are different. Here, the formation of the build-up layer 50 will be described as an example.

First, a blind via is formed in the interlayer insulating film 41 by laser processing. After that, a desmear process is performed to remove residues generated by the laser processing. This exposes the land portion of the first conductor layer 20 and the upper electrode 32. Note that the laser used to form the blind via may be different from the laser used to form the modified portion 13. For example, a pulsed laser such as a carbon dioxide laser or a UV-YAG laser is preferably used to form the blind via. When a pulsed laser is used, the laser pulse width is preferably in the range of microseconds.

Next, the seed layer contained in the conductor layer 51 is formed as a continuous film on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the first conductor layer 20 by sputtering or electroless plating.

Next, the conductor layer 51 is obtained, for example, by a semi-additive process.

Specifically, first, a mask pattern with openings at positions corresponding to the copper layer included in the conductor layer 51 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. In one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the first conductor layer 20 side is etched until the exposed portion of the seed layer is removed. In this manner, the conductor layer 51 is obtained.

Next, an interlayer insulating film 42 is provided on the interlayer insulating film 41, and then a blind via is formed in the interlayer insulating film 42 by laser processing. After that, a desmear process is performed to remove residues generated by the laser processing. This exposes the land portion of the conductor layer 51. Note that the laser used to form the blind via may be different from the laser used to form the modified portion 13. For example, a pulsed laser such as a carbon dioxide laser or a UV-YAG laser is preferably used to form the blind via. When a pulsed laser is used, the laser pulse width is preferably in the range of microseconds.

Next, the seed layer contained in the conductor layer 52 is formed as a continuous film on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the first conductor layer 20 by sputtering or electroless plating.

Next, the conductor layer 52 is obtained, for example, by a semi-additive process.

Specifically, first, a mask pattern with openings at positions corresponding to the copper layer included in the conductor layer 52 is formed on the seed layer. The mask pattern is formed, for example, by providing a photoresist layer on the seed layer, and then performing pattern exposure and development on this photoresist layer. In one example, RD1225, a dry photoresist manufactured by Showa Denko Materials, is laminated onto the seed layer, and the dry photoresist is sequentially subjected to pattern exposure and development to obtain a mask pattern made of resin. A liquid resist may be used to form the mask pattern.

Next, electrolytic copper plating is performed using the seed layer as a power supply layer. This deposits copper on the seed layer at the positions of the openings in the mask pattern, resulting in a copper layer.

Then, the mask pattern is removed. For example, the dry film resist is dissolved and peeled off. Next, the entire surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the first conductor layer 20 side is etched until the exposed portion of the seed layer is removed. In this manner, the conductor layer 52 is formed, and the build-up layer 50 is obtained.

In addition, a process similar to the process for forming the build-up layer 50 described above is carried out on the surface of the composite including the first conductor layer 20, the second conductor layer 80, and the glass substrate 10 on the side of the second conductor layer 80 to obtain the build-up layer 100.

<1.2.13> Thirteenth Step Next, an insulating layer 60 is provided on the interlayer insulating film 42. For example, a solder resist is provided on the interlayer insulating film 42, and is patterned using a photolithography method or the like. This exposes the pad portions of the conductor layer 52. Thereafter, a surface treatment is performed on the exposed pad portions of the conductor layer 52, and then the conductor layer 70 is provided.

Similarly, an insulating layer 110 is provided on the interlayer insulating film 92. For example, a solder resist is provided on the interlayer insulating film 92, and then patterned using a photolithography method or the like. This exposes the pad portion of the conductor layer 102. After that, a surface treatment is performed on the exposed pad portion of the conductor layer 102, and then the conductor layer 120 is provided.

Surface treatments include treatments using nickel and gold, treatments using nickel, palladium, or gold, immersion tin plating (IT), and organic solderability preservative (OSP).

In this way, the structure shown in Figure 14 is obtained.

<1.2.14> Fourteenth Step: Thereafter, the end portion OR is separated from the obtained composite body, and the inside of the central portion IR is divided into individual regions corresponding to a plurality of glass substrates 10s.

In this manner, the wiring board 1 shown in Figure 1 is obtained.

<1.3> Effects The above-described technology provides the following effects, for example.

<1.3.1> Handling Ease According to the above-described manufacturing method, the glass substrate 10 is less likely to be damaged, and excellent handling ease can be achieved. This will be described below.

When through holes are formed in a glass substrate, its mechanical strength may decrease. In addition, thin glass substrates, for example, those with a thickness of 100 μm or less, are prone to cracking during transportation to form conductive parts such as circuits, and are difficult to handle.

In the above-described manufacturing method, the support 12 is bonded to the glass substrate 10 before the first conductor layer 20 and the like are formed. This allows the composite including the glass substrate 10 and the support 12 to have high strength. In addition, before peeling off the support 12, the support 15 is bonded to the first surface S1 side on which the first conductor layer 20 and the like are formed. This further increases the strength of the composite. Therefore, even after peeling off the support 12, the glass substrate 10 is unlikely to break. Therefore, according to the above-described manufacturing method, the glass substrate 10 is unlikely to break and is easy to handle.

<1.3.2> Productivity Furthermore, according to the above-described manufacturing method, high productivity can be achieved, as will be described below.

When forming the modified portion 13, excessive energy may be applied to the glass substrate 10 by the laser light, which may cause microcracks in the glass substrate 10. For this reason, restrictions may be imposed on the irradiation conditions (process window), such as the wavelength and laser pulse width of the laser light, and the laser irradiation position.

According to the above-mentioned manufacturing method, the glass substrate 10 bonded to the support 12 is irradiated with laser light to form the modified portion 13. This makes it possible to increase the mechanical strength of the glass substrate 10 during laser light irradiation compared to when the glass substrate 10 that is not bonded to the support 12 is irradiated with laser light. This makes it possible to ease the processing conditions for laser irradiation. In addition, it becomes possible to form the modified portion 13 at a desired position on the glass substrate 10. Therefore, the above-mentioned manufacturing method makes it possible to achieve high productivity.

<1.3.3> Yield Furthermore, according to the above-described manufacturing method, damage to the glass substrate 10 can be suppressed when the support 12 is peeled off from the glass substrate 10, and a high yield can be achieved. This will be described below.

When peeling the support 12 from the glass substrate 10, damage such as cracks and chips may occur to the glass substrate 10. In other words, damage to the glass substrate 10 during the process of peeling the support 12 from the glass substrate 10 may reduce the yield.

In the manufacturing method described with reference to FIG. 8, before peeling the support 12 from the glass substrate 10, a groove G is formed between the glass substrate 10 and the support 12 by etching. The etching is performed so that the depth P of the groove G is in the range of 10 μm or more and 5 mm or less, more preferably in the range of 50 μm or more and 500 μm or less. This makes it easy to perform a scribing process using a razor blade or the like when peeling the support 12 from the glass substrate 10. This makes it possible to suppress the occurrence of microcracks that accompany the peeling process.

In addition, in this etching process, the edge of the glass substrate 10 is etched overall. This makes it possible to remove microcracks that have occurred in the glass substrate 10 in the process prior to the etching process. Therefore, the above-mentioned manufacturing method can improve the yield.

<1.4> Modifications Various modifications are possible to the above-described wiring board 1.

<1.4.1> Adhesive Layer For example, the adhesive layer provided between the glass substrate 10 and the support 12 is not limited to one that contains a functional group, and may contain a resin.

Figure 15 is a cross-sectional view showing a step in the method for manufacturing a wiring board according to the first modified example. Figure 15 corresponds to Figure 8 in the embodiment. The example in Figure 15 shows the process for forming groove G when adhesive layer 11A is used instead of adhesive layer 11.

The adhesive layer 11A is, for example, a resin. Examples of the resin include resins that become peelable by absorbing light such as UV light and generating heat, sublimating, or changing in quality, resins that become peelable by foaming due to heat, resins whose adhesion changes depending on temperature, and adhesive resins. According to one example, REVALPHA (registered trademark) manufactured by Nitto Denko Corporation is used as the adhesive layer 11A.

In the first modified example, an etching process is performed by immersing the composite in which the support 12 is bonded via the adhesive layer 11A in an etching solution. This removes a portion of the glass substrate 10 and the support 12. On the other hand, since the etching rate of the adhesive layer 11A is significantly lower than that of the glass substrate 10 and the support 12, most of the adhesive layer 11A remains without being removed.

The etching solution easily penetrates between the glass substrate 10 and the adhesive layer 11A, so the etching rate is higher than in other areas. As a result, a groove G that serves as the starting point for peeling is formed between the adhesive layer 11A and the glass substrate 10, as shown in FIG. 15. The depth P of the groove G is preferably in the range of 10 μm to 5 mm, as in the case of FIG. 8, and more preferably in the range of 50 μm to 500 μm.

The etching solution also easily penetrates between the support 12 and the adhesive layer 11A, so the etching rate is higher than in other areas. This can also form a groove between the adhesive layer 11A and the support 12. If the depth of the groove formed between the adhesive layer 11A and the support 12 exceeds a predetermined depth, for example, 5 mm, there is a possibility that detachment will occur in the adhesive layer 11A. The detached adhesive layer 11A is a source of foreign matter and can cause defects in subsequent processes, which is undesirable.

Therefore, in the first modified example, the adhesive layer 11A is bonded between the glass substrate 10 and the support 12 so that the adhesive layer 11A has higher adhesion to the support 12 than to the glass substrate 10. This allows the amount of etching solution to penetrate between the support 12 and the adhesive layer 11A to be less than the amount of etching solution to penetrate between the glass substrate 10 and the adhesive layer 11A. Therefore, as shown in FIG. 15, the depth of the groove between the support 12 and the adhesive layer 11A can be made smaller than the depth P of the groove G. This makes it possible to suppress the generation of foreign matter sources.

In addition, in the first modified example, during the peeling process, UV light irradiation, heating process, cooling process, physical peeling, and other processes are performed depending on the material used for the adhesive layer 11A. By performing these processes, the adhesion between the glass substrate 10 and the adhesive layer 11A can be reduced, making it easier to peel off from the glass substrate 10. Therefore, the occurrence of microcracks associated with the peeling process can be suppressed, and the yield can be improved.

<1.4.2> Support Body Furthermore, for example, the size of the support body that is attached to the glass substrate 10 via the adhesive layer 11A may be different from that of the glass substrate 10 .

Figure 16 is a cross-sectional view showing one step in the method for manufacturing a wiring board according to the second modified example. Figure 16 corresponds to Figure 15 in the first modified example. The example in Figure 16 shows the formation process of groove G when support 12A is bonded to glass substrate 10 via adhesive layer 11A instead of support 12.

The support 12A has a larger area along the XY plane than the glass substrate 10. This makes it easier to insert a razor blade or the like into the groove G during the peeling process. This makes it easier to perform the peeling process and reduces the possibility of unintentional damage to the glass substrate 10.

<1.4.3> Other Modifications Other modifications of the above-described wiring board 1 are possible.

For example, the seed layer included in each of the first conductor layer 20, the upper electrode 32, the build-up layer 50, the second conductor layer 80, and the build-up layer 100 may have a multi-layer structure including an adhesion layer. For example, a sputtering method or an electroless plating method is used to form the adhesion layer. For example, titanium is suitable as a material for the adhesion layer. In consideration of forming the adhesion layer as a continuous film and productivity, it is preferable that the thickness of the adhesion layer is in the range of 5 nm or more and 100 nm or less.

The following describes the tests conducted in relation to the present invention.

(Example 1)
Fifty glass substrates 10 were manufactured by carrying out the bonding process with the support 12 in the sixth step, the etching process in the seventh step, and the peeling process in the eighth step.

Here, the size of the glass substrate 10 was 150 μm thick, 200 mm long in the X direction, and 200 mm long in the Y direction. The size of the support 12 was 500 μm thick, and the dimensions in the X direction and Y direction were the same as those of the glass substrate 10. The material of both the glass substrate 10 and the support 12 was non-alkali glass.

In the etching process, the glass substrate 10 was immersed in a hydrofluoric acid etching solution with a hydrofluoric acid concentration of 2% for 10 minutes, and then washed with water and dried. The edge of the glass substrate 10 after the etching process was then observed with an optical microscope, and the depth P of the groove G was measured.

In addition, the presence or absence of cracks at the edge of the glass substrate 10 after the peeling process was observed with an optical microscope, and the number of glass substrates 10 that were deemed NG (NG number) was calculated. When calculating the NG number, glass substrates 10 that were found to have a crack or crack in even one place were deemed to be NG.

(Example 2)
Fifty glass substrates 10 were manufactured similarly to those manufactured in Example 1, except that the X-direction length and Y-direction length of the glass substrate 10 were changed to 320 mm and 400 mm, respectively. For these glass substrates 10, the depth P was measured and the number of NGs was calculated in the same manner as in Example 1.

(Comparative Example 1)
Fifty glass substrates were manufactured in the same manner as in Example 1 except that the etching treatment was omitted. For these glass substrates, the depth P was measured and the number of NG defects was calculated in the same manner as in Example 1.

(Comparative Example 2)
Fifty glass substrates were manufactured in the same manner as in Example 2 except that the etching treatment was omitted. For these glass substrates, the depth P was measured and the number of NG defects was calculated in the same manner as in Example 2.

(result)
The results are shown in Table 1 below.

As shown in Table 1, when the etching process was performed, a groove G having a depth P in the range of 50 μm or more and 130 μm or less could be formed between the glass substrate 10 and the support 12, regardless of the size of the glass substrate 10. On the other hand, when the etching process was not performed, no groove G was formed between the glass substrate 10 and the support 12, regardless of the size of the glass substrate 10.

In addition, when an etching process was performed during the peeling process, a smaller number of NGs was achieved than when an etching process was not performed, regardless of the size of the glass substrate 10. Furthermore, when an etching process was performed, a number of NGs of 0 was achieved, regardless of the size of the glass substrate 10.

Reference Signs List 1...wiring board, 10, 10s...glass substrate, 11, 11A...adhesive layer, 12, 12A...support, 13...modified portion, 14...adhesive layer, 15...support, 20...first conductor layer, 21...hydrofluoric acid resistant metal layer, 22...metal layer, 30...capacitor, 31...dielectric layer, 32...upper electrode, 40, 40s, 41, 41s, 42, 42s...interlayer insulating film, 50...build-up layer , 51, 52...conductor layer, 60, 60s...insulating layer, 70...conductor layer, 80...second conductor layer, 90, 90s, 91, 91s, 92, 92s...interlayer insulating film, 100...build-up layer, 101, 102...conductor layer, 110, 110s...insulating layer, 120...conductor layer, S1...first surface, S2...second surface, IR...center, OR...end, G...groove, P...depth, H...through hole.

Claims (13)

providing a first support on a second surface side of a glass substrate having a first surface and a second surface opposed to each other;
forming a first conductor layer on the first surface side of the glass substrate on which the first support is provided;
performing a first etching process to form a groove between the glass substrate and the first support at an end surface of the glass substrate on which the first support is provided;
Separating the first support from the glass substrate on which the first conductor layer is formed, using the groove as a separation starting point;
Equipped with
A method for manufacturing a wiring board. the separating step includes pressing a jig having a tapered tip so that the tip is positioned within the groove, and applying a force in a direction to separate the glass substrate and the first support from each other.
The method according to claim 1 . the separating step includes pressing a jig having a tapered tip so that the tip is positioned within the groove, and introducing a fluid between the glass substrate and the first support from a position of the groove.
The method according to claim 1 . The method further includes providing a second support on the first surface side of the glass substrate on which the first conductor layer is formed before separating the first support.
The method according to claim 1 . forming a second conductor layer on the second surface side of the glass substrate from which the first support is separated;
Separating the second support from the glass substrate on which the second conductor layer is formed;
Further comprising:
The method according to claim 4. forming a first build-up layer on the first surface side of the glass substrate from which the second support has been separated;
forming a second build-up layer on the second surface side of the glass substrate from which the second support has been separated;
Further comprising at least one of
The method according to claim 5. irradiating a laser beam onto the glass substrate on which the first support is provided, to form a modified portion on the glass substrate;
performing a second etching process on the glass substrate from which the first support is separated to form a through hole at the position of the modified portion;
Further comprising:
The method according to claim 1 . Further comprising forming a second conductor layer on the second surface side of the glass substrate in which the through hole is formed,
the second conductor layer includes a portion provided on the second surface, a portion provided on a side wall of the through hole, and a portion in contact with a portion of the first conductor layer covering the through hole;
The method according to claim 7. the first conductor layer includes a copper layer and a hydrofluoric acid-resistant metal layer provided between the glass substrate and the copper layer and in contact with the second conductor layer;
The method according to claim 8. The first support is directly bonded to the glass substrate.
The method according to claim 1 . The first support is bonded to the glass substrate via an adhesive layer.
The method according to claim 1 . The first support is larger than the glass substrate when viewed in a direction intersecting the first surface and the second surface.
The method according to claim 1 . The depth of the groove is 10 μm or more and 5 mm or less.
The method according to any one of claims 1 to 12.