JP2024058301A - Chip Resistors - Google Patents

Abstract

[Problem] To provide a chip resistor that can reliably improve surge characteristics and can adjust the resistance value over a wide range by trimming. [Solution] A chip resistor 1 includes a rectangular insulating substrate 2, a pair of front electrodes 4 provided at both longitudinal ends of the insulating substrate 2, and a rectangular resistor 3 that bridges the pair of front electrodes 4, and the resistor 3 has a resistance value adjusted by forming a plurality of trimming grooves 9, 10 that extend linearly. When the direction that connects the pair of front electrodes 4 at the shortest distance is defined as the X direction and the direction perpendicular to the X direction is defined as the Y direction, two rows of a plurality of openings 12 that are wider than the groove width of the trimming grooves 9, 10 are formed in the resistor 3 along the Y direction, and the trimming grooves 9, 10 are formed so as to extend in the Y direction from one of two outer edges of the resistor 3 that extend in the X direction as a starting point toward the other outer edge, with any opening 12 being the end point. [Selected Figure] Figure 1

Description

The present invention relates to a chip resistor whose resistance value is adjusted by forming a trimming groove in the resistor element.

A chip resistor is mainly composed of a rectangular insulating substrate, a pair of front electrodes arranged facing each other with a specified distance on the surface of the insulating substrate, a pair of rear electrodes arranged facing each other with a specified distance on the rear surface of the insulating substrate, end electrodes bridging the front and rear electrodes, a resistor bridging the pair of front electrodes, and a protective coating layer covering the resistor.

In general, when manufacturing such chip resistors, a large number of electrodes, resistors, protective coating layers, etc. are formed on a large substrate at once, and then the large substrate is divided along grid-like dividing lines (e.g., dividing grooves) to obtain a large number of chip resistors. In the manufacturing process of such chip resistors, a large number of resistors are formed on one side of the large substrate using thick film or thin film technology, but since it is difficult to avoid variations in the initial resistance value of each resistor, a resistance value adjustment process is performed in which trimming grooves are formed in each resistor while the substrate is still in the large substrate and the desired resistance value is set.

Trimming grooves are slits (laser marks) formed by irradiating a resistor with laser light, and known shapes include an I-cut shape that starts at the outer edge of the resistor and extends in a straight line in a direction perpendicular to the inter-electrode direction, and an L-cut shape that turns 90 degrees from the middle of the I-cut and extends in the inter-electrode direction.

In the case of an I-cut trimming groove, the tip of the trimming line becomes a load-concentrated area where the current path is narrowed, so when a surge voltage generated by static electricity or power supply noise is received, excessive electrical stress is likely to cause problems such as fluctuations in resistance value and resistor breakage. Since it is known that one way to improve surge characteristics is to lengthen the current path flowing through the resistor, chip resistors have been proposed in the past in which multiple (e.g., two) I-cut trimming grooves are formed in the resistor to form a meandering shape (see, for example, Patent Document 1). With a chip resistor configured in this way, the multiple trimming grooves can increase the adjustment range of the resistance value, and the meandering shape of the resistor lengthens the current path, dispersing the load-concentrated area and improving the surge characteristics.

On the other hand, in the case of an L-cut trimming groove, although power concentration at the end of the trimming line can be avoided, the adjustment range of the resistance value by trimming cannot be increased, so there is a manufacturing problem in that a wide range of resistance values cannot be covered. In particular, thin-film resistors formed using thin-film techniques such as sputtering and vapor deposition cannot freely change the initial resistance value by mixing multiple resistance materials as in thick-film resistors, and the adjustment range of the resistance value required for the resistor is wide, so with an L-cut trimming groove, it becomes impossible to reliably adjust the resistance value to the target resistance value.

JP 2020-61448 A

As mentioned above, in chip resistors with multiple linear trimming grooves formed in the resistor, the overall length of the current path through the resistor can be increased to disperse the load concentration area and improve surge characteristics. However, in the case of resistors with a thin film thickness, such as thin-film resistors, the volume of the load concentration area at the tip of the trimming line is small, so simply giving the resistor a serpentine shape can cause resistance value fluctuations due to surge voltages, and there is a demand for further improvements in surge characteristics.

The present invention was made in consideration of the current state of the prior art, and its purpose is to provide a chip resistor that can reliably improve surge characteristics and allows for a wide range of resistance value adjustment by trimming.

In order to achieve the above object, the present invention provides a chip resistor comprising a rectangular parallelepiped insulating substrate, a pair of electrodes provided at both longitudinal ends of the main surface of the insulating substrate, and a rectangular resistor bridging the pair of electrodes, and the resistor has a resistance value adjusted by forming a trimming groove extending linearly. When the direction connecting the pair of electrodes at the shortest distance is defined as the X direction and the direction perpendicular to the X direction is defined as the Y direction, the resistor has a plurality of openings wider than the groove width of the trimming groove formed in at least two or more rows along the Y direction, and the trimming groove is formed to extend in the Y direction from one of the two outer edges of the resistor extending in the X direction as a starting point toward the other outer edge, and any of the openings is defined as a terminal point.

In a chip resistor configured in this manner, multiple openings are formed in at least two rows in the resistor along a direction perpendicular to the electrodes, and linear trimming grooves are formed at positions spanning the openings in each row, allowing a wide range of resistance adjustments to be made by trimming multiple rows. Furthermore, the portion located between the opening where the trimming groove ends and the outer edge of the resistor becomes a load concentration portion, and the volume of this load concentration portion is large depending on the width of the opening, which is wider than the width of the trimming groove, so that even when subjected to a surge voltage generated by static electricity, power supply noise, etc., it is possible to reliably prevent resistance value fluctuations and resistor breakage.

In the chip resistor of the above configuration, if the volume of the resistor sandwiched between the opening where the end of the trimming groove is located and the other outer edge of the resistor is set within a range of 5% to 40% of the overall volume of the resistor that serves as the current path, this is preferable because it allows for low resistance while improving surge characteristics.

In addition, in a chip resistor having the above configuration, if the width dimension of the opening facing the other outer edge of the resistor is set larger than the width dimension of the opening facing the one outer edge of the resistor, the volume of the load concentration portion can be increased.

In addition, in the chip resistor having the above configuration, the shape of the multiple openings is not particularly limited, but it is preferable that the openings have a non-rectangular shape without corners, such as a rectangle with rounded corners or an oval, in order to prevent current concentration.

In addition, in a chip resistor having the above configuration, if the multiple openings arranged in a row are arranged at a position offset toward one of the outer edges with respect to the center of the resistor in the Y direction, a trimming groove can be formed from the outer edge side with a shorter distance from the openings, making it easy to ensure a large-volume load concentration area on the outer edge side with a longer distance from the openings.

In addition, in the chip resistor having the above configuration, if a fine-tuning trimming groove having a shorter overall length than the trimming groove formed in a position straddling the multiple openings is formed near the trimming groove formed in a position straddling the multiple openings, this is preferable because it allows the resistance value to be finely adjusted with high precision.

In addition, in the chip resistor of the above configuration, if the resistor is a thin-film resistor formed by vacuum deposition or sputtering, a chip resistor with low resistance and excellent surge characteristics can be realized.

The chip resistor of the present invention can reliably improve surge characteristics and allows for a wide range of resistance value adjustments through trimming.

FIG. 2 is a plan view of a chip resistor according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 3 is an explanatory diagram showing a resistor pattern provided on the chip resistor. FIG. 5A to 5C are plan views showing a manufacturing process of the chip resistor. 5A to 5C are plan views showing a manufacturing process of the chip resistor. 5A to 5C are cross-sectional views showing a manufacturing process of the chip resistor. 5A to 5C are cross-sectional views showing a manufacturing process of the chip resistor. FIG. 13 is an explanatory diagram showing a modified example of the opening portion. FIG. 13 is an explanatory diagram showing a modified example of the opening portion. FIG. 13 is an explanatory diagram showing a modified example of the opening portion. FIG. 13 is an explanatory diagram showing a modified example of the electrode arrangement.

The following describes an embodiment of the invention with reference to the drawings.

Figure 1 is a plan view of a chip resistor according to an embodiment of the present invention, and Figure 2 is a cross-sectional view taken along line II-II in Figure 1.

As shown in Figures 1 and 2, the chip resistor 1 of this embodiment is mainly composed of a rectangular insulating substrate 2, a resistor 3 formed on the surface of the insulating substrate 2, a pair of front electrodes 4 formed on both ends of the resistor 3, a protective coating layer 5 formed to cover the resistor 3, a pair of back electrodes 6 formed on both longitudinal ends of the back surface of the insulating substrate 2, a pair of end electrodes 7 formed on both longitudinal end faces of the insulating substrate 2, and a pair of external electrodes 8 plated to cover the end electrodes 7, and three trimming grooves 9, 10, and 11 are formed in the resistor 3 for adjusting the resistance value to a desired value.
There are.

The insulating substrate 2 is a large substrate described later, which is divided along primary and secondary dividing grooves that extend vertically and horizontally in a lattice pattern into a number of pieces, and the large substrate is a _sheet -like substrate whose main components are _Al2O3 , _SiO2 , ZrO and mixtures thereof. In the following description, the longitudinal direction of the insulating substrate 2 (the direction connecting a pair of front electrodes 4 at the shortest distance) is the X-direction, and the lateral direction of the insulating substrate 2 (the direction perpendicular to the X-direction) is the Y-direction.

The resistor 3 is a thin-film resistor formed by vacuum deposition or sputtering of resistor materials whose main components are NiCr, CuNi, CrSi, TaN, etc., and is formed so as to cover almost the entire surface of the insulating substrate 2.

The front electrodes 4 are thin-film electrodes formed by vacuum deposition or sputtering of Cu, Ag, Au, Al, Ni, Cr, Pt, Pd, or an alloy containing two or more of these, and are formed on both ends of the resistor 3 in the X direction and positioned at both longitudinal ends of the insulating substrate 2.

Figure 3 is an explanatory diagram showing the trimming pattern of resistor 3. As shown in Figure 3(a), the resistor 3 sandwiched between a pair of front electrodes 4 has a rectangular outer shape, and in the following description, one of the two outer edges of resistor 3 extending in the X direction is referred to as the first outer edge 3a, and the other is referred to as the second outer edge 3b.

In this resistor 3, a plurality of openings 12 arranged along the Y direction are formed at two positions close to both front electrodes 4, and in this embodiment, three openings 12 are formed continuously at a predetermined interval per row. For convenience, the openings 12 in one row close to the front electrode 4 on the left side of the figure are called the first opening group, and the openings 12 in the other row close to the front electrode 4 on the right side of the figure are called the second opening group. Each opening 12 constituting the first opening group is formed at a position biased toward the first outer edge 3a, and the length from the second outer edge 3b to the opposing opening 12 is set to be longer than the length from the first outer edge 3a to the opposing opening 12. Also, each opening 12 constituting the second opening group is formed at a position biased toward the second outer edge 3b, and the length from the first outer edge 3a to the opposing opening 12 is set to be longer than the length from the second outer edge 3b to the opposing opening 12.

By forming three trimming grooves 9, 10, and 11 in the resistor 3 in which such an opening 12 is formed, the resistance value of the resistor 3 is adjusted to a predetermined value. As shown in FIG. 3(b), the first trimming groove 9 extends linearly in the Y direction from the first outer edge 3a, which has a narrower distance from the opening 12, to a position where the opening 12 faces the second outer edge 3b of the first opening group is terminated. The second trimming groove 10 extends linearly in the Y direction from the second outer edge 3b, which has a narrower distance from the opening 12, to a position where the opening 12 faces the first outer edge 3a of the second opening group is terminated. These two trimming grooves 9 and 10 adjust the resistance value of the resistor 3 to a value close to the target resistance value, and the resistor 3 has a two-turn meandering shape, which increases the total length of the current path.

Here, the narrowed portion of the current path between the opening 12 where the end of the first trimming groove 9 is located and the second outer edge 3b of the resistor 3 becomes the load concentration portion A (the hatched portion in the figure). Similarly, the portion sandwiched between the opening 12 where the end of the second trimming groove 10 is located and the first outer edge 3a of the resistor 3 also becomes the load concentration portion A. Since the volume of these load concentration portions A depends on the width dimension of the opening 12, which is sufficiently wider than the groove width of the trimming grooves 9 and 10, a large-volume load concentration portion A is secured in the resistor 3. The total volume of these load concentration portions A is set within the range of 5% to 40% of the volume of the portion that becomes the current path in the resistor 3.

As shown in FIG. 3(c), the third trimming groove 11 extends linearly in the Y direction from the second outer edge 3b near the second trimming groove 10 as its starting point, and is formed at a position that does not straddle each opening 12 of the second opening group. The portion where the third trimming groove 11 is formed is an area of the resistor 3 with low current distribution, and by forming this trimming groove 11 to a position that does not exceed the entire length of the second trimming groove 10, the resistance value of the resistor 3 that is adjusted stepwise by the first and second trimming grooves 9 and 10 is finely adjusted with even higher accuracy. Here, the shape of the third trimming groove 11 for fine adjustment is not necessarily limited to a linear shape (I-cut shape), and may be other shapes such as L-cut or U-cut.

The openings 12 that are the termination positions of the first and second trimming grooves 9, 10 are selected arbitrarily depending on the initial resistance value of the resistor 3, etc. For example, if the trimming grooves 9, 10 terminate at the central openings 12 of each row, two load concentration areas A will be formed at the tip side of each of the trimming grooves 9, 10, as shown in Figure 3(d).

1 and 2, the protective coating layer 5 has a two-layer structure consisting of an inner undercoat layer 13 and an outer overcoat layer 14. The undercoat layer 13 is an insulating film formed by vacuum deposition, sputtering, CVD, or the like using inorganic materials such as _SiO2 , SiN, and _{Al2O3 ,} and is formed so as to cover the resistor 3 before the trimming grooves 9, 10, and 11 are formed. The overcoat layer 14 is an insulating film formed by screen printing epoxy resin, silicone resin, polyimide resin, or the like, and is formed so as to cover the undercoat layer 13 after the trimming grooves 9, 10, and 11 have been formed.

The back electrode 6 is a thin-film electrode formed by vacuum deposition or sputtering of Cu, Ag, Au, Al, Ni, Cr, Pt, Pd, or an alloy containing two or more of these, and is formed on both longitudinal ends of the back surface of the insulating substrate 2 corresponding to the front electrode 4.

The end electrodes 7 are thin-film electrodes formed by vacuum deposition, sputtering, or other methods using NiCr, Cu, Ni, Cr, or a metal material containing a combination of these. The end electrodes 7 provide electrical continuity between the corresponding front electrodes 4 and back electrodes 6 on both the front and back sides of the insulating substrate 2.

The external electrode 8 has a two-layer structure consisting of an inner barrier layer 15 and an outer external connection layer 16. The barrier layer 15 is a Ni plating layer formed by electrolytic plating, and this barrier layer 15 covers the entire surface of the end electrode 7. The external connection layer 16 is a Sn plating layer formed by electrolytic plating, and this external connection layer 16 covers the entire surface of the barrier layer 15.

Next, a method for manufacturing the chip resistor 1 configured as described above will be described with reference to Figures 4 to 7. Figures 4 and 5 are plan views showing the manufacturing process of the chip resistor 1, and Figures 6 and 7 are cross-sectional views showing the manufacturing process of the chip resistor 1.

First, as shown in Figures 4(a) and 6(a), a large-sized substrate 2A from which multiple insulating substrates 2 are to be cut is prepared. Primary and secondary dividing grooves extending vertically and horizontally are provided in advance in a grid pattern on this large-sized substrate 2A, and each of the squares separated by the dividing grooves becomes one chip area. Although Figures 4 to 7 show a representative large-sized substrate 2A corresponding to one chip area, in reality, the steps described below are carried out simultaneously on a large-sized substrate 2A corresponding to multiple chip areas.

In the first step, as shown in Figures 4(b) and 6(b), a resistor film 3A mainly composed of NiCr or the like is formed on the surface of a large substrate 2A by vacuum deposition or sputtering.

Next, an electrode film made of Cu or the like is formed on the resistor film 3A by vacuum deposition or sputtering, and then this electrode film is patterned by photolithography to form a pair of surface electrodes 4 at both ends of the resistor film 3A, as shown in Figures 4(c) and 6(c).

Then, the resistor film 3A is patterned by photolithography to form a resistor 3 having a rectangular outer shape between a pair of front electrodes 4, as shown in Fig. 4(d) and Fig. 6(d), and a plurality of openings 12 are formed inside the resistor 3. Also, before or after this, an electrode film made of Cu or the like is formed on the back surface of the large substrate 2A by vacuum deposition or sputtering, and then the electrode film is patterned by photolithography to form a pair of back electrodes 6 at positions corresponding to the front electrodes 4 on the back surface of the large substrate 2A.

It is also possible to reverse the order of the process of forming the front electrode 4 and the process of patterning the resistor 3. In that case, after patterning the resistor film 3A to form the resistor 3, the resistor 3 is masked except for a specified position, and in this state the electrode film is sputtered or the like to form the front electrode 4.

Next, an inorganic material such as _SiO2 is formed on the front electrode 4 and the resistor 3 by a method such as CVD, and this inorganic material is patterned by photolithography to form an undercoat layer 13 that covers a part of the front electrode 4 and the entire resistor 3, as shown in Figures 4(e) and 6(e).

Next, by irradiating the undercoat layer 13 with laser light, three trimming grooves 9, 10, and 11 are formed in the resistor 3, as shown in FIG. 5(f) and FIG. 7(f), to adjust the resistance value to a target predetermined value. As described above, the first and second trimming grooves 9 and 10 are formed from the opposing outer edges of the resistor 3 to a position that reaches an arbitrary opening 12, and by forming these two trimming grooves 9 and 10, the resistance value of the resistor 3 is gradually raised to a value close to the target resistance value. The third trimming groove 11 is formed at a position on the side of the second trimming groove 10 that does not straddle the opening 12, and by forming this trimming groove 11, the resistance value of the resistor 3 raised by the first and second trimming grooves 9 and 10 is finely adjusted to the target resistance value with high precision.

Next, a resin material such as epoxy resin is screen-printed on the undercoat layer 13, and the resin material is cured by heating or irradiating with ultraviolet light to form an overcoat layer 14 that covers the undercoat layer 13, as shown in Figures 5(g) and 7(g). The undercoat layer 13 and overcoat layer 14 form a protective coat layer 5 with a two-layer structure.

Each step up to this point is a batch process for the large-sized substrate 2A for multiple pieces, but in the next step, a primary break process is performed to divide the large-sized substrate 2A into strips along the primary dividing grooves, resulting in a strip-shaped substrate 2B with multiple chip areas. Next, a metal material such as NiCr is sputtered onto the divided surfaces of the strip-shaped substrate 2B to form end electrodes 7 that bridge the corresponding front electrodes 4 and back electrodes 6, as shown in Figures 5(h) and 7(h).

Then, a secondary breaking process is performed in which the rectangular substrate 2B is divided along the secondary dividing grooves, to obtain chip units 2C of the same size as the chip resistor 1. Next, Ni plating is applied to each individual chip unit 2C by electrolytic plating to form a barrier layer 15 that covers the entire surface of the end electrode 7, as shown in Figures 5(i) and 7(i). Finally, Sn plating is applied to each chip unit 2C by electrolytic plating to form an external connection layer 16 that covers the entire surface of the barrier layer 15, as shown in Figures 5(j) and 7(j). The barrier layer 15 and external connection layer 16 form an external electrode 8 with a two-layer structure, and a chip resistor 1 as shown in Figures 1 and 2 is obtained.

As described above, according to the chip resistor 1 of this embodiment, the resistor 3 has a plurality of openings 12 formed in multiple rows (two rows in this embodiment) along the direction (Y direction) perpendicular to the electrodes, and linear trimming grooves 9, 10 are formed at positions straddling the openings 12 in each row, so that the resistance value can be adjusted over a wide range by these trimmings 9, 10. Moreover, the portion located between the openings 12 at which the ends of the trimming grooves 9, 10 are located and one of the outer edges of the resistor 3 becomes the load concentration portion A, and the volume of this load concentration portion A is larger depending on the width dimension of the openings 12, which is wider than the groove width of the trimming grooves 9, 10, so that even if a surge voltage generated by static electricity or power supply noise is received, it is possible to reliably prevent resistance value fluctuations and disconnection of the resistor 3.

The total volume of the load concentration area A is set to within the range of 5% to 40% of the volume of the current path in resistor 3, which makes it possible to achieve low resistance while improving surge characteristics.

In addition, in the chip resistor 1 according to this embodiment, the multiple openings 12 arranged in a row are arranged at a position offset toward one of the outer edges with respect to the center of the resistor 3 in the Y direction. Therefore, by forming the trimming grooves 9, 10 from the outer edge side with a shorter distance to the openings 12, it is possible to easily ensure a large-volume load concentration portion A on the outer edge side with a longer distance to the openings 12.

In addition, in the chip resistor 1 according to this embodiment, a trimming groove 11 for fine adjustment, which has a shorter overall length than the trimming groove 10, is formed near the trimming groove 10 formed at a position straddling the opening 12, but at a position that does not straddle the opening 12. Therefore, the resistance value of the resistor 3, which is gradually increased by the trimming grooves 9 and 10 formed at a position straddling the opening 12, can be continuously increased by the trimming groove 11 for fine adjustment, thereby enabling highly accurate resistance value adjustment.

In addition, in the chip resistor 1 according to this embodiment, the resistor 3 is a thin-film resistor formed by vacuum deposition or sputtering, so that a chip resistor 1 with low resistance and excellent surge characteristics can be realized.

The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention. All technical matters included in the technical ideas described in the claims are the subject of the present invention. The above-described embodiment shows a preferred example, but a person skilled in the art can realize various alternatives, modifications, variations, or improvements from the contents disclosed in this specification, and these are included in the technical scope described in the attached claims.

For example, in the above embodiment, the openings 12 in each row all have the same shape, but as in the modified example shown in FIG. 8, the width dimension of the openings 12 facing one outer edge of the resistor 3, which is the starting end of the trimming groove, may be made larger than the width dimension of the openings 12 facing the other outer edge of the resistor 3. This configuration is preferable because it makes it possible to increase the volume of the load concentration portion A formed on the terminal end of the trimming groove.

In addition, in the above embodiment, the opening 12 is rectangular with four corners, but as in the modified example shown in FIG. 9, the opening 12 may be rectangular with rounded corners, or as in the modified example shown in FIG. 10, the opening 12 may be elliptical. In this way, when the opening 12 is non-rectangular and has no corners, it is possible to prevent current from concentrating at the corners of the opening 12.

In addition, in the above embodiment, the resistor 3, the front electrode 4, and the back electrode 6 are positioned slightly inward from the end of the insulating substrate 2, so that in the primary breaking step, the large substrate 2A can be easily divided along the primary dividing groove to obtain the rectangular substrate 2B. However, as in the modified example shown in FIG. 11, the resistor 3, the front electrode 4, and the back electrode 6 may be positioned so that they reach the end of the insulating substrate 2, and in this case, it is preferable to divide the large substrate 2A by dicing to obtain the rectangular substrate 2B. Note that FIG. 11(a) is a plan view, and FIG. 11(b) is a cross-sectional view.

In addition, in the above embodiment, a chip resistor 1 is described in which two rows of openings 12 are arranged along the short side direction (Y direction) of the resistor 3, but the number of rows of openings 12 may be three or more.

In the above embodiment, a chip resistor in which the resistor 3 is a thin-film resistor formed by a sputtering method or the like has been described, but the present invention is also applicable to chip resistors in which the resistor is a thick-film resistor.

REFERENCE SIGNS LIST 1 Chip resistor 2 Insulating substrate 2A Large substrate 3 Resistor 3a First outer edge 3b Second outer edge 4 Front electrode 5 Protective coating layer 6 Back electrode 7 End electrode 8 External electrode 9, 10 Trimming groove 11 Fine adjustment trimming groove 12 Opening 13 Undercoat layer 14 Overcoat layer 15 Barrier layer 16 External connection layer A Load concentration portion

Claims (7)

A chip resistor comprising: a rectangular parallelepiped insulating substrate; a pair of electrodes provided at both longitudinal ends of a main surface of the insulating substrate; and a rectangular resistor bridging the pair of electrodes, the resistance value of which is adjusted by forming a trimming groove extending linearly in the resistor,
When the direction connecting the pair of electrodes at the shortest distance is defined as the X direction, and the direction perpendicular to the X direction is defined as the Y direction,
a plurality of openings, each of which is wider than a width of the trimming groove, are formed in the resistor so as to form at least two or more rows along the Y direction;
The trimming groove is formed so as to extend in the Y direction from one of two outer edge portions of the resistor extending in the X direction toward the other outer edge portion as a starting end position, and has any one of the openings as a terminal end position.
A chip resistor characterized in that The chip resistor according to claim 1, characterized in that the volume of the resistor sandwiched between the opening where the trimming groove ends and the other outer edge of the resistor is within a range of 5% to 40% of the overall volume of the resistor that serves as the current path. The chip resistor according to claim 1, characterized in that the width dimension of the opening facing the other outer edge of the resistor is set larger than the width dimension of the opening facing the one outer edge of the resistor. The chip resistor according to claim 1, characterized in that the multiple openings are non-rectangular and have no corners. The chip resistor according to claim 1, characterized in that the plurality of openings arranged in a row are arranged at a position offset toward one of the outer edges with respect to the center of the resistor in the Y direction. The chip resistor according to claim 1, characterized in that a trimming groove for fine adjustment, the trimming groove having a shorter overall length than the trimming groove formed in a position straddling the multiple openings, is formed in the vicinity of the trimming groove in a position that does not straddle the multiple openings. The chip resistor according to claim 1, characterized in that the resistor is a thin-film resistor formed by vacuum deposition or sputtering.

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