JP2023533599A - FPGA based industrial protocol mapping structure and method - Google Patents

Abstract

Kind Code: A1 The present invention uses RS-232 and RS-485 interfaces to realize large-scale networking of industrial control systems, and enables intercommunication between PLCs and instruments of different manufacturers, and enables FPGA The chip can be used to ensure accuracy, real-time and reliability of data transmission. The present invention relates to the field of control, specifically to an FPGA-based industrial protocol mapping structure and method, the structure includes a central processing unit CPU and an FPGA chip connected, said FPGA chip includes a mapping module, a mapping A form module, a framing module and a clock reset module are provided, the clock reset module connecting and controlling the mapping module, the mapping form module and the framing module respectively, the framing module receiving data from the serial port and Receiving frame byte data from the port completes protocol framing and outputs message frames to a mapping module, which is connected to a mapping form module. [Selection drawing] Fig. 1

Description

The present invention relates to the field of control, and more particularly to FPGA-based industrial protocol mapping structures and methods.

FPGA (Field Programmable Gate Array) is a further development based on programmable devices such as PAL, GAL and CPLD. It has emerged as a kind of semi-custom circuit in the field of application specific integrated circuits (ASIC), solving the shortcomings of custom circuits and the limited number of original programmable device gate circuits.

A communication protocol, also called a communication policy, is a contract for data transmission control over both communications. The conventions generally define issues such as data formats, synchronization methods, transmission speeds, transmission steps, error detection and correction methods, and control character definitions, and include those that both communications must comply with at the same time. Each instrument has its own unique communication protocol, commonly modbus communication protocol, RS-232 communication protocol, RS-485 communication protocol, PPI communication protocol, mewtocol communication protocol, and the like.

Current industrial protocols are mainly interconnected through serial ports and fieldbuses, with limited transmission distances, different instruments must be used in industrial scenes, and different protocols limit inter-instrument communication. Demands for the execution accuracy of control information in the production process are increasing, and the precision requirements for the accuracy and real-time performance of data transmission have reached the microsecond level.

Aiming at the problem of short transmission distance and limited transmission protocol in the existing industrial protocol transmission, the present invention provides an FPGA-based industrial protocol mapping structure and method, which is capable of large data size. It can meet the needs of scale and long-distance transmission, and ensure the accuracy, compatibility and reliability of data transmission.The specific technical solutions are as follows.

An FPGA-based industrial protocol mapping structure comprising a connected central processing unit (CPU) and an FPGA chip, the FPGA chip being provided with a mapping module, a mapping form module, a framing module and a clock reset module, wherein the clock The reset module connects and controls the mapping module, the mapping form module and the framing module respectively, the framing module receives data from the serial port and receives frame byte data from the serial port to perform protocol framing. Completed, it outputs the message frame to a mapping module, which is connected to a mapping form module.

Further, said mapping form module includes a PLC type mapping form plctypeform and a basic mapping form mapform, said basic mapping form mapform being used to indicate addresses, register types, locations in frames of instructions, said basic mapping form mapform exists in the form of RAM, has a total of 16 entries, is 16 deep and 24 wide, said PLC type mapping form plctypeform has a total of 256 entries, Used to classify PLCs, the subnet supports access of up to 256 PLCs, has a total of 4 types of mapping methods from 0 to 3, and the PLC type mapping form plctypeform is the form of RAM , with a depth of 256 and a width of 3.

Further, the mapping module includes a protocol type register, a port number register, a role register, a cmd command register, an edge edge calculation register and a data conversion register, wherein the protocol type register is used to set the protocol type, the port number The register is 4 bits and is used to set the port number of the current port port, the role register is 2 bits and is used to set the role of the current port port, and the cmd command register is 64 bits. , used to set the command register, the upper 32 bits represent writing, the lower 32 bits represent reading, the edge edge calculation register is 32 bits, used to store the edge calculation data, the The data conversion register has 2 bits and is used to set data conversion.

Moreover, the message frame is a complete message frame, and the data interface between the framing module and the mapping module is 8bits.

Further, the clock reset module includes a clock module and a reset module, the clock module uses the 50M clock of the backplane to generate a 125Mhz clock through the PLL frequency multiplier, and the whole system is a unified clock of 125Mhz. located in the field, the reset module causes the system to be reset at high level, pulls up the locked signal of the clock module when the clock module generates a stable 125Mhz clock signal, and raises the locked signal of the clock module. It is used to count, and when it counts to 3F, the system performs a high level reset.

An FPGA-based industrial protocol mapping method comprising:
When the CPU initializes, it sets a basic mapping form mapform based on the user's custom content, the type of the basic mapping form mapform includes the source protocol location, the number of bytes occupied by the source protocol, and the entries are configuration mapping instructions, A message frame containing register type, data, destination address, the depth of said basic mapping form mapform is 16 and the width is 24, extracted from the serial port after completing the initialization of said basic mapping form mapform. step S1 of retrieving the corresponding data in and marking the data type for later edge calculation, data conversion;
Next, extract the PLC SLAVE ID based on the basic mapping form mapform, then search the PLC type mapping form plctypeform based on the PLC SLAVE ID to get the current PLC type, and based on the PLC type, create the edge calculation form. a step S2 of searching and comparing with the edge_reg data set in the CPU in the form, performing packet loss if not satisfied, and transferring to the subsequent bus switching module if satisfied;
a step S3 of retrieving and transferring data corresponding to the edge calculation to the edge calculation module;
Finally, it includes a step S4 of extracting the data block from the mapform's RAM.

The present invention uses RS-232 and RS-485 interfaces, can realize large-scale networking of industrial control systems, and can realize mutual communication between PLCs and instruments of different manufacturers, and uses FPGA chips. Therefore, the accuracy, real-timeness and reliability of data transmission can be ensured.

FIG. 1 is a structural schematic diagram of the rigid frame of the present invention. FIG. 2 is a flow chart of the mapping method of the present invention. FIG. 3 is a principle diagram of the clock reset module of the present invention.

In order to make the purpose, technical solution and technical effect of the present invention clearer, the present invention will be described in more detail below with reference to the drawings.

As shown in FIG. 1, an FPGA-based industrial protocol mapping structure includes a central processing unit CPU and an FPGA chip connected. The central processing unit CPU implements data exchange and register configuration, and implements communication, logic control and data processing. The FPGA chip provides a unified external serial port for receiving, parsing and mapping serial port data, and is intended to double as a conventional industrial instrument and a PLC device.

The FPGA chip is provided with a mapping module 2 , a mapping form module 1 , a framing module 4 and a clock reset module 3 .
The mapping form module 1 includes a PLC type mapping form (plctypeform) and a basic mapping form (mapform).

The basic mapping form (mapform) is used to indicate the location in the frame of addresses, register types, instructions, etc. The form exists in the form of RAM, has a total of 16 entries, and is 16 deep. and has a width of 24.

The PLC type mapping form (plctypeform) has a total of 256 entries and is used to classify PLCs within a subnet, and a subnet supports access of up to 256 PLCs, with a total of 0-3 entries. It has 4 types of mapping schemes, the form exists in the form of RAM, is 256 deep and 3 wide.

The central processing unit CPU extracts the correlation data in the frame by setting the basic mapping form and the PLC type mapping form.

The mapping module 2 supports protocols such as modbus RTU, modbus ASCII, MEWTOCOL, hostlink and PPI.

The mapping module 2 includes a protocol type register, a port number register, a role register, a cmd instruction register, an edge edge calculation register, and a datacoversion data conversion register.

The protocol type register framing_mode is for setting the protocol type.

The port number register port_num is 4 bits and is used to set the port number of the current port port.

The role register is 2 bits and is used to set the role of the current port port. For example, 00 represents slave, 01 represents master1, 02 represents master2, and 11 represents master3.

The cmd command register cmd_reg is 64 bits and is used to set the command register, with the upper 32 bits representing write and the lower 32 bits representing read.

The edge edge calculation register edge_reg is a 32-bit edge calculation register.

The data conversion data conversion register is 2 bits and is used to set the data conversion, for example, 00 and 11 indicate that no data conversion is required, 01 indicates conversion from binary to ASCII code, 10 indicates conversion from ASCII code. Represents a conversion to binary.

The framing module 4 receives data from the serial port, and based on receiving frame byte data from the serial port controller, the framing function of protocols such as Profibus, PPI, Mewtocol (ASCII), Modbus ASCII, Hostlink+FINS, Modbus RTU, etc. complete the The one from the framing module is a complete message frame and the data interface is 8bit.

As shown in FIG. 3, the clock reset module 3 includes a clock module and a reset module to provide a stable and uniform clock source for protocol mapping, a reference source for deterministic data transmission, and a protocol mapping module. provide the power on/off sequence requirements for successful execution of the

Here, the clock module, the whole system is in the 125Mhz clock field and uses the 50M clock on the backplane to generate the 125Mhz clock by the PLL frequency multiplier.

the reset module pulls up the locked signal when the entire system performs a high-level reset and the clock module generates a stable 125Mhz clock signal, and counts using the lock signal of the clock module; When counting to 3F, the entire system performs a high level reset.

As shown in FIG. 2, an FPGA-based industrial protocol mapping method comprising the following steps S1 to S4,
In step S1, the SLAVE ID is extracted based on the mapform. Specifically, when the CPU is initialized, it first sets a basic mapping form (mapform), the type of the form is source protocol location, and the source protocol is Including the number of bytes occupied, entries include configuration mapping instructions, register types, data, destination addresses, etc. The content of the specific form can be defined by the user, the mapping form being 16 deep and 24 wide. after completing the initialization of the form, retrieve the corresponding data in the message frame extracted from the serial port, and mark the data type for later edge calculation and data conversion;
In step S2, retrieve the PLC type corresponding to the SLAVE ID based on the plctypeform, then retrieve the PLC SLAVE ID based on the basic mapping form (mapform), and then retrieve the PLC type mapping form (plctypeform) based on the PLC SLAVE ID. ) to obtain the current PLC type, search the form of edge calculation based on the PLC type, and compare with the edge_reg data set in the CPU in the form, perform packet loss if not satisfied, and satisfy transfer to the subsequent bus exchange module,
In step S3, edge calculation data is extracted based on edge_reg, specifically, the data corresponding to the edge calculation is extracted and transferred to the edge calculation module,
Finally, in step S4, data blocks are extracted from the mapform RAM.

The present invention enables hierarchical transmission according to the importance of data in the data communication process, and ensures real-time, reliability and accuracy of high-priority data.

It will be appreciated by those skilled in the art that the above description is merely a preferred illustration of the invention and is not intended to limit the invention, and that the invention has been described in detail with reference to the above examples. If so, the technical solutions described in the above examples can still be modified, or some of their technical features can be replaced by equivalents. Any modifications, equivalent substitutions, etc. made within the spirit and principle of the invention shall fall within the protection scope of the invention.

1 mapping form module 2 mapping module 3 clock reset module 4 framing module

Claims (6)

In an FPGA-based industrial protocol mapping structure comprising a central processing unit (CPU) and an FPGA chip connected,
The FPGA chip is provided with a mapping module (2), a mapping form module (1), a framing module (4) and a clock reset module (3), wherein the clock reset module (3) comprises a mapping module (2), a mapping The form module (1) and the framing module (4) are respectively connected and controlled, and the framing module (4) receives data from the serial port and receives frame byte data from the serial port to implement the protocol. An FPGA-based industrial protocol mapping structure, characterized in that it completes framing and outputs message frames to a mapping module (2), said mapping module (2) being connected to a mapping form module (1). Said mapping form module (1) comprises a PLC type mapping form plctypeform and a basic mapping form mapform, said basic mapping form mapform being used to indicate an address, a register type, a position in a frame of an instruction, said basic mapping form The mapform exists in the form of RAM, has a total of 16 entries, is 16 deep and 24 wide, said PLC type mapping form plctypeform has a total of 256 entries, The subnet supports access of up to 256 PLCs, and has a total of 4 types of mapping methods from 0 to 3. The PLC type mapping form plctypeform is the RAM 2. The FPGA-based industrial protocol mapping structure of claim 1, which exists in the form of a depth of 256 and a width of 3. The mapping module (2) includes a protocol type register, a port number register, a role register, a cmd command register, an edge edge calculation register and a data conversion register, wherein the protocol type register is used to set the protocol type, the port The number register is 4 bits and is used to set the port number of the current port port, the role register is 2 bits and is used to set the role of the current port port, and the cmd command register is 64 bits. is used to set the command register, the upper 32 bits represent writing and the lower 32 bits represent reading, the edge edge calculation register is 32 bits, and is used to store edge calculation data; The FPGA-based industrial protocol mapping structure as recited in claim 1, wherein the data conversion register is 2-bit and is used to set data conversion. The FPGA-based industrial protocol mapping structure according to claim 1, characterized in that said message frame is a complete message frame and the data interface between the framing module (4) and the mapping module (2) is 8bit. . The clock reset module (3) includes a clock module and a reset module, the clock module uses the 50M clock of the backplane to generate a 125Mhz clock through the PLL frequency multiplier, and the whole system Located in the clock field, the reset module causes the system to high-level reset, pulls up the locked signal of the clock module when the clock module generates a stable 125Mhz clock signal, and the lock signal of the clock module. The FPGA-based industrial protocol mapping structure of claim 1, wherein the counting is performed using , and the system performs a high-level reset when counting to 3F. An FPGA-based industrial protocol mapping method, comprising the following steps S1 to S4,
In step S1, when the CPU initializes, it sets a basic mapping form mapform according to the user's custom content, the type of the basic mapping form mapform includes the source protocol location, the number of bytes occupied by the source protocol, and the entry contains the configuration mapping instruction, register type, data, destination address, the depth of said basic mapping form mapform is 16 and the width is 24, and after completing the initialization of said basic mapping form mapform, from the serial port retrieving the corresponding data in the extracted message frame and marking the data type for later edge calculation, data conversion;
In the step S2, next extract the SLAVE ID of the PLC based on the basic mapping form mapform, then search the PLC type mapping form plctypeform based on the SLAVE ID of the PLC, obtain the current PLC type, Based on this, search the edge calculation form and compare it with the edge_reg data set in the CPU in the form, perform packet loss if not satisfied, transfer to the subsequent bus switching module if satisfied,
In step S3, the data corresponding to the edge calculation is taken out and transferred to the edge calculation module;
The FPGA-based industrial protocol mapping method, wherein, in said step S4, finally, extracting data blocks from RAM of mapform.

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