CN106168933A - A kind of method realizing virtual dual-port shared drive based on high-speed serial communication - Google Patents
A kind of method realizing virtual dual-port shared drive based on high-speed serial communication Download PDFInfo
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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Abstract
The invention discloses a kind of method realizing virtual dual-port shared drive based on high-speed serial communication, belong to embedding assembly technical field.The communication cpu both sides of the present invention are respectively arranged with a fpga chip and provide RAM EBI to it, are connected with high speed communication lines between two fpga chips, and FPGA internal firmware realizes each layer communication protocol and RAM access function.The invention enables and can possess again the biggest motility in hardware distribution simply efficiently such as dual port RAM alternately between CPU.
Description
Technical field
The invention belongs to embedding assembly technical field, in particular it relates to one is based on high-speed serial communication
The method realizing virtual dual-port shared drive.
Background technology
Embedded computing system is widely used in industrial control field.The automatically-monitored equipment of power system secondary side is allusion quotation
The embedded computing system application of type, comprises one or more embedded unit inside it, it is achieved specific protection control or
Data monitoring function.Such automation equipment is logically generally made up of following several parts: analog acquisition unit, signal are defeated
Enter unit, control output unit, Logical processing unit, data processing unit, communications interface unit, man-machine interaction unit etc..
Embedding assembly equipment in early days is many calculates system with single CPU or DSP for core composition embedded Control, it is achieved set
Standby required function.Along with the change of the external environment conditions such as electrical network demand, technology development, the calculated performance of equipment, extended capability etc. are each
Item index steps up so that device interior must use many set embedded subsystems can meet requirement.Between multiple CPU how
Carry out real time data and become emphasis and the difficult point of system design alternately.
Real time data between CPU the most substantially has a two ways: parallel mode, serial mode.Parallel mode refers to use
Dual port memories chip (abbreviation dual port RAM) provides two set internal memory compatible bus so that two CPU can access in same section jointly
Deposit.Serial mode refers to be connected by the high-speed bus such as Ethernet, LVDS between two CPU, performs specific communication protocol number
According to transmitting-receiving.Both modes all have some limitations.The parallel mode of dual port RAM can only be positioned at same print at two CPU
Use time in making sheet；Serial communication mode can take CPU substantial amounts of calculating resource and communicate the agreement implementation, reduces CPU
Application performance and reliability in time.It addition, also there is the high speed interactive selection of standardized multi-CPU, such as PCI, PCI-E, but this
System cost, development difficulty and production technology degree are had higher requirements by class scheme, it is impossible to be widely used in middle low complex degree and one-tenth
The industrial control system of this sensitivity.
Summary of the invention
The present invention seeks to: for problem between communication among multiple CPUs in prior art, it is provided that a kind of lead to based on high speed serialization
The method of reliable existing virtual dual-port shared drive.
Specifically, the present invention realizes by the following technical solutions: the CPU of data interaction both sides is by being led to by two
Cross the fpga chip that high speed serial communication link couples together and carry out data interaction；RAM, RAM is included inside described fpga chip
Depositing for data, the CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively, and both sides ram space is identical, ground
Location is corresponding；When side CPU writes data in the RAM of the FPGA of its side, these data are passed through high-speed serial communication by this FPGA
Link is sent to the FPGA of opposite side, opposite side CPU and has access to this data by the RAM identical address accessing the FPGA of its side.
Technique scheme is further characterized by, when side CPU enters data to the RAM write of the FPGA of its side,
After data arrive opposite side CPU, automatically pass back to the identical address of the RAM of the FPGA of data former write side, write as former in data
The CPU of side reads the data of this passback and shows that data the most reliably arrive the other side.
Technique scheme is further characterized by, and the RAM of described FPGA is divided into many numbers according to the order of address
According to mapping priority, it is in the high priority data transmission of the high address area of priority.
Technique scheme is further characterized by, and the RAM of described FPGA is provided with read-write Acceditation Area and system registry district,
For managing transmitting-receiving sequential and the fault processing of data.
The invention also discloses a kind of safety and stability control device of electric network based on the communication of virtual dual-port shared drive, bag
Include central authorities and process module and each function module, use between each module and aforesaid realize virtual both-end based on high-speed serial communication
The method of mouth shared drive communicates.
Beneficial effects of the present invention is as follows: the data interaction side that dual port memories is combined by the present invention with high-speed communication
Method.Communication cpu both sides are respectively arranged with a fpga chip and provide RAM EBI to it, with high speed communication lines phase between two fpga chips
Even, so make can possess again the biggest motility in hardware distribution, spy simply efficiently such as dual port RAM alternately between CPU
It is not applicable to solve the difficult problem that multiple subsystem complex data is mutual.
Accompanying drawing explanation
Fig. 1 is COM_RAM fundamental block diagram.
Fig. 2 is that COM_RAM commonly uses topological diagram.
Fig. 3 is COM_RAM asymmetric switching node schematic diagram.
Fig. 4 is COM_RAM workflow diagram.
Fig. 5 is COM_RAM typical case's application: stability control device physical assemblies schematic diagram.
Fig. 6 is COM_RAM typical case's application: stability control device communication topology figure.
Detailed description of the invention
Below in conjunction with embodiment and referring to the drawings the present invention is described in further detail.
Embodiment 1:
Embodiment shows one with the example of the virtual dual-port RAM of FPGA programming realization (being called for short COM_RAM).Its base
In the extensive programmable logic chip of FPGA and High-Speed Communication Technique so that be positioned at the CPU energy of high-speed serial communication both link ends
Enough efficient data interactions easily carried out as dual port RAM in plate.
The ultimate principle that COM_RAM realizes is the firmware program by designing FPGA, is automatically obtained the multilamellar of data communication
Agreement, only provides standardized RAM access interface to the CPU of data interaction both sides, simplifies its communication process burden, makes CPU energy
Enough it is absorbed in the realization of application software.
COM_RAM realizes substantially as it is shown in figure 1, COM_RAM is coupled together by high-speed serial communication link by two
Fpga chip and respective physical interface constitute, all include inside each fpga chip 2 logical blocks (LOGIC) and caching
(RAM), wherein 2 logical blocks are respectively used to realize data transmission logic (SEND LOGIC) and data acceptance logic
(RECEIVE LOGIC), RAM deposits for data.The CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively,
Constituted by COM_RAM and share the mutual of RAM formula.When side CPU writes data in the RAM of the FPGA of its side, this FPGA
These data are sent to the FPGA of opposite side by high-speed serial communication link, and opposite side CPU is by accessing the FPGA's of its side
RAM identical address has access to this data.
Mainly it is accomplished that data communication function due to COM_RAM, refers to the Rotating fields of Open System Interconnection OSI to it
It is described.Following table briefly lists COM_RAM and corresponds to OSI function comparison in each layer that communicates.Below from the merit of each layer
Can realize and characteristic is introduced respectively.
Application level function CPU interactive application data by both party realizes.COM_RAM provides connecing alternately of RAM mode to CPU
Mouthful, this interface can have the following characteristics that
1, one section of shared RAM of data interaction both sides CPU access interacts, interface class vraisemblance dual port RAM chip.
2, providing standard SRAM EBI on hardware, 8/16/32 optional, and Intel/PowerPC mode is optional.
3, the size of dual port RAM is variable according to application, and low is 256 bytes, and height can be 64k byte.
4, COM_RAM Module Reusable, make certain CPU can by continuous multi-stage RAM realize with multiple CPU parallel mutual.
The basic function of transport layer is A side CPU write to be entered the data of certain address in shared RAM be reliably mapped to B side CPU
RAM in identical address, i.e. apply the mapping of data.Here like address refers to relative address, and both sides CPU is to this section of RAM
The absolute address of definition may be different.Transport layer realizes reliable mapping by data register and the mechanism of rebounding.In view of COM_RAM
Being virtual dual-port RAM, data map successful speed and depend primarily on the bandwidth of serial communication link, under most conditions cannot
In reaching plate, the data in single peripheral access cycle of true dual port RAM map speed, and then transport layer introduces priority mechanism,
The i.e. high priority data of high priority is mapped.Details are as follows for this layer of principle:
1, COM_RAM basic use scene be point-to-point alternately, i.e. Being RAM Interface between CPU and FPGA, both sides ram space is identical, and address is corresponding, with byte is
Ultimate unit.
2, data map: CPU_A is certain address write new data in RAM, and CPU_B should be over time in identical address
Have access to this new data.
3, rebound mechanism: CPU_A to RAM address write new data after, data arrive CPU_B rear flank, can automatically return
Passing to the identical address (identical address of the RAM of the FPGA of data former write side) of CPU_A, now CPU_A could read at this
New data.After i.e. CPU write enters data, as long as retaking of a year or grade is correct, indicate that data the most reliably arrive the other side.
4, priority mechanism: RAM district is divided into several data according to the order of address and maps (i.e. transmission) priority, such as
Address 0-255 is high priority, and address 256-64k is low priority.The transmission mechanism of different priorities data, in similar CPU
The corresponding mechanism that different priorities interrupts, i.e. current priority soprano obtains prioritised transmission resource.The data of different priorities
Mechanism gives CPU motility in application.Interaction data high for requirement of real-time can be written to relatively low address area by CPU, makes
Can be read by recipient the soonest.
5, login mechanism: every side RAM is respectively designed with read-write Acceditation Area, system registry district, for managing the transmitting-receiving of data
Sequential and fault processing.Acceditation Area is for automatically to manage region, and CPU cannot access.The size of read-write Acceditation Area is actual big with RAM's
Little correspondence, the RAM write of each of which its correspondence of unit record enters/reads the transmission state of byte, reception state；System registry district marks
Note and record precedence information, fault processing state etc..
In the communication networks such as Ethernet, Internet is typically implemented and is operated by route, exchange etc., by complex topology network
In the reliable data transmission of certain source node to destination node.The design of COM_RAM is mainly directed towards Industry Control and calculates field, application
Under the most fixing Topology connection operating mode, do not possess the route of complexity, function of exchange.Although the basic module of COM_RAM is
Point-to-point virtual dual-port RAM, but by reasonable disposition, can realize the multiple topologys such as point-to-point, point-to-multipoint, multiple spot ring should
With.If in conjunction with CPU in the operation of application layer, more complicated network construction can be realized further.Topology mode is summarized as follows:
1, point-to-point: the basic topology application of COM_RAM.I.e. two CPU are exchanged visits by COM_RAM, such as Fig. 2 institute
Show.
2, point-to-points: certain CPU side, FPGA reuses multiple COM_RAM module, in hardware link, is also connected to many sides simultaneously
CPU.So local cpu passes through connected reference multistage address ram, and can realize with multi-CPU is parallel mutual, as shown in Figure 2.
3, multiple spot ring: be provided with three cpu nodes CPU_A, CPU_B and CPU_C, they possess a road COM_RAM respectively and connect
Mouthful, every road COM_RAM annular concatenation i.e. TX_A-> RX_B, TX_B-> RX_C, TX_C-on the communication link > RX_A.By above
Described data map and mechanism of rebounding, and multiple CPU can share same section of RAM, as shown in Figure 2.
4, asymmetric exchange: in multiple commercial Application, the data stream of control system possesses asymmetric feature, such as many distributions
Node gathers convergence and at most performs node to central node, management node issues broadcast data, etc..To this end, COM_RAM
Expand the switch version of the asymmetric transmitting-receiving of a kind of one-to-many: many-one realizes convergence, one-to-many realizes broadcast.Accordingly,
Physical link also must carry out the configuration of 1+N.So, under above-mentioned multidrop network, with relatively low physics and design cost, side
Multiple CPU can share same section of RAM and realize the data interaction with opposite side list CPU.As shown in Figure 3.
The basic function of link layer is reliably to be sent to opposite end from communication one end by unit data, with Frame is typically
Unit.In view of adapting to multiple physical layers communication link, and ensureing the high reliability in commercial Application, COM_RAM is at link
Layer be designed with following several feature:
1, the short frame of efficient synchronization: for ensureing the real-time of transmission upper layer data and consideration based on connection reliability,
Link layer uses frame synchronization transmission, i.e. receiving-transmitting chain to repeat transmission in units of frame.Frame head is special byte code, and frame is can
Becoming the upper layer data data of frame length, postamble is this frame CRC check code.The data frame length that priority is the highest is the shortest.Its workflow
Figure is as shown in Figure 4.
2, the byte code of balance: link layer includes that the ultimate unit of the data of frame head is the byte after encoding.According to thing
The difference of reason layer interface, byte uses 8b10b or 5b4b coding.Use the specific code in byte code as frame transmitting-receiving with preferential
The management of level.
3, physical layer interface flexibly: link layer and physical layer interface are roughly divided into two classes, and is that link layer is received with physics
Send out device or circuit direct interface, link layer carry out byte code；Two are and standardized physical chip such as ethernet PHY
Interface, link layer carries out the transmitting-receiving of byte with special sequencing contro PHY chip, and the encoding and decoding of byte are automatically performed by PHY chip.
Physical layer provides the physical medium of communications, and ensures the reliability of transmission the most as far as possible.In order to suitable
Answering multiple commercial Application environment, COM_RAM supports multiple communication specification and form of medium on a physical layer.According to using scene
Difference, institute's support pattern is listed below:
1, mutual in plate: high speed SERDES (1Gbps-2.5Gbps), LVDS (10Mpbs-800Mbps.
2, backboard is mutual: LVDS (10Mpbs-500Mbps), BLVDS/MLVDS (10Mpbs-100Mbps.
3, mutual between cabinet: 10bpsM/100Mbps/1000bpsM Ethernet cable, special optic fibre (10Mbps-
2.5Gbps)。
4, remote interaction: E1 coaxial cable (multiplex link, 2Mbps/ road), SDH optical fiber (155Mbps-2.5Gbps).
In order to tackle the feature that physical layer medium is changeable, application scenarios is complicated, the design of physical layer possesses following two
Individual feature:
(1) link is changeable, and mechanism is constant: under different application scenarios and restrictive condition, physical communication link has multiple
Situation, as maybe can realized the traffic rate of 2.5Gbps in application in plate by SERDES, and middle and long distance uses Ethernet cable
Application in may as little as 10Mbps.Design due to layering so that communication mode and the speed of physical layer only affect
The frame transmission speed of link layer, does not produce impact to upper strata realization mechanism or reliability.
(2) link multiplication, bandwidth doubles: the original intention of the present invention is just so that the communicating pair under the conditions of serial link to the greatest extent may be used
The raising data interaction efficiency of energy, so under physical condition allows, it should improve data transfer bandwidth as far as possible.Therefore, exist
In place of link layer and physical layer interface, additionally devise the mechanism of bandwidth multiplication, even if a plurality of identical communication link is provided that
The bandwidth increments corresponding with mathematics promotes (due to the increase of the communication overheads such as alignment of data, actual bandwidth is lower slightly).As based on
In the application of backboard LVDS communication, 4 byte datas of wall scroll 100Mbps link map (CPU_A writes, and CPU_B reads) time delay
Being about 1us, when 5 same link are concurrently accessed, time delay will shorten to 200ns, and this speed is fast with the response of real dual port RAM
Spend close.In LVDS class physical link, can directly support this function；In ethernet link, need to carry out direct-connected could supporting；
During support point physically, the E1/SDH link of multiplex protocol are applied, the bandwidth multiplication of distant place communication can be realized.
Embodiment 2:
Embodiment shows COM_RAM utilization in safety and stability control device of electric network.
Safety and stability control device of electric network is control equipment important in high voltage substation.Every complete equipment is generally by several machines
Case form, each cabinet has multiple plug-in unit, realize respectively analog acquisition, logical calculated, On-off signal output, man machine interface,
The functions such as correspondence with foreign country.Comprise the embedded system centered by a CPU in plug-in unit more.Between the plug-in unit of cabinet inside, cabinet
It is required to carry out real-time, interactive.Real-time, bandwidth and data flow are had nothing in common with each other by mutual data.As switching value data is real-time
Property require high, bandwidth is low, bidirectional equalization, man-machine data bandwidth is high but input and output are unbalanced, real-time is relatively low, gathers data band
Width, requirement of real-time are the highest and unidirectional up, etc..If in this system application COM_RAM technology, by various configurations mode
Combination, can efficiently solve the difficult problem that multiple subsystem complex data is mutual.
Fig. 5 lists a kind of typical safety and stability control device hardware configuration.Apparatus system is made up of multiple cabinets, point
One mainframe box and one or more is from cabinet.CPU in mainframe box need to collect respectively from the collection of cabinet, switch,
The data such as communication also calculate and logical judgment in real time, simultaneously to respectively from cabinet output control command or communication data.Respectively from
Cabinet is according to the internal module of application demand configuration.All physically communicated by optical fiber with mainframe box from cabinet.
Fig. 6 describe inside above-mentioned stability control device with COM_RAM for each module of Primary communication mode between communication logic
Structure:
1, inside mainframe box, central authorities process module by the LVDS link of case back plate and data management module, man-machine boundary
Face mould part communicates.Data management module realizes the functions such as the storage of system data, printing, background communication；Man machine interface mould
Part realizes the functions such as the liquid crystal display of system man-machine interface, input through keyboard.
2, central authorities process module by bidirectional optical fiber with respectively communicate from cabinet.Each from cabinet be configured with communication exchange
Module, it is achieved many modules and central authorities process the asymmetric data real-time exchange between module from cabinet, make two ends share same section
Data exchange space.According to the actual data transfer bandwidth needs of application, certain can configure multipair optical fiber to improve communication from cabinet
Bandwidth.
3, configuring in the cabinet of modules such as opening, output, communication bandwidth is less, can be realized by the topological mode of multiple spot ring
Multiple cases processes the connection of module with central authorities, so can meet demand, can save again communication interface resource.
4, from cabinet inside, each module is provided with and the communication port of the exchange module that communicates.Inhomogeneity according to module
, the physical channels such as LVDS, BLVDS, CAN, RS-485 in backboard resource can not used, be respectively adopted COM_RAM, MODBUS etc.
Communication protocol.In fpga chip in communication exchange module, it is designed with the IP module of DMA function, to realize COM_RAM and MOD_
The seamless exchange of the low-speed communication interfaces such as BUS, facilitates the exchanging visit of communicating pair CPU.
Although the present invention is open as above with preferred embodiment, but embodiment is not for limiting the present invention's.Not
Depart from the spirit and scope of the present invention, any equivalence change done or retouching, also belong to the protection domain of the present invention.Cause
The content that this protection scope of the present invention should be defined with claims hereof is as standard.
Claims (5)
1. the method realizing virtual dual-port shared drive based on high-speed serial communication, it is characterised in that data interaction is double
The CPU of side is by being carried out data interaction by two fpga chips coupled together by high-speed serial communication link；Described FPGA
Chip internal includes RAM, RAM depositing for data, and the CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively,
Both sides ram space is identical, and address is corresponding；When side CPU writes data in the RAM of the FPGA of its side, this FPGA is by this number
Identical by the RAM accessing the FPGA of its side according to the FPGA, opposite side CPU being sent to opposite side by high-speed serial communication link
Address has access to this data.
The method realizing virtual dual-port shared drive based on high-speed serial communication the most according to claim 1, its feature
It is, when side CPU enters data to the RAM write of the FPGA of its side, after data arrive opposite side CPU, automatically passes back to number
According to the identical address of RAM of the FPGA of former write side, the CPU of write side as former in data reads data of this passback and shows that data are
Through reliably arriving the other side.
The method realizing virtual dual-port shared drive based on high-speed serial communication the most according to claim 1 and 2, it is special
Levying and be, the RAM of described FPGA is divided into multiple data according to the order of address and maps priority, is in the address that priority is high
The high priority data transmission in district.
The method realizing virtual dual-port shared drive based on high-speed serial communication the most according to claim 1 and 2, it is special
Levying and be, the RAM of described FPGA is provided with read-write Acceditation Area and system registry district, at the transmitting-receiving sequential managing data and mistake
Reason.
5. based on virtual dual-port shared drive communication a safety and stability control device of electric network, including central authorities process module with
And each function module, it is characterised in that use between each module as described in claim 1 ~ 5 based on high-speed serial communication realization
The method of virtual dual-port shared drive communicates.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933757A (en) * | 2017-03-14 | 2017-07-07 | 郑州云海信息技术有限公司 | A kind of method of spread F PGA storage resources |
| CN107367991A (en) * | 2017-08-04 | 2017-11-21 | 湖南利能科技股份有限公司 | A kind of data acquisition device based on AMP |
| CN110750069A (en) * | 2019-12-24 | 2020-02-04 | 武汉精立电子技术有限公司 | Multi-equipment control device of AOI system |
| CN112181886A (en) * | 2020-10-16 | 2021-01-05 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Information interaction system, method and medium based on LVDS channel |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201163399Y (en) * | 2008-01-04 | 2008-12-10 | 国电南京自动化股份有限公司 | Double-CPU protection information shared system based on double-port RAM |
| CN104021098A (en) * | 2014-06-19 | 2014-09-03 | 福州闽台机械有限公司 | Multi-board collaboration architecture based on DMA transparent transmission |
| CN105068955A (en) * | 2015-07-20 | 2015-11-18 | 北京广利核系统工程有限公司 | Local bus structure and data interaction method |
-
2016
- 2016-06-30 CN CN201610516553.1A patent/CN106168933B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201163399Y (en) * | 2008-01-04 | 2008-12-10 | 国电南京自动化股份有限公司 | Double-CPU protection information shared system based on double-port RAM |
| CN104021098A (en) * | 2014-06-19 | 2014-09-03 | 福州闽台机械有限公司 | Multi-board collaboration architecture based on DMA transparent transmission |
| CN105068955A (en) * | 2015-07-20 | 2015-11-18 | 北京广利核系统工程有限公司 | Local bus structure and data interaction method |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106933757A (en) * | 2017-03-14 | 2017-07-07 | 郑州云海信息技术有限公司 | A kind of method of spread F PGA storage resources |
| CN107367991A (en) * | 2017-08-04 | 2017-11-21 | 湖南利能科技股份有限公司 | A kind of data acquisition device based on AMP |
| CN110750069A (en) * | 2019-12-24 | 2020-02-04 | 武汉精立电子技术有限公司 | Multi-equipment control device of AOI system |
| CN110750069B (en) * | 2019-12-24 | 2020-05-22 | 武汉精立电子技术有限公司 | Multi-equipment control device of AOI system |
| CN112181886A (en) * | 2020-10-16 | 2021-01-05 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Information interaction system, method and medium based on LVDS channel |
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| CN106168933B (en) | 2019-08-09 |
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