WO2022247019A1

WO2022247019A1 - Industrial protocol mapping structure and method based on fpga

Info

Publication number: WO2022247019A1
Application number: PCT/CN2021/111767
Authority: WO
Inventors: 牛广; 李顺斌; 王利强; 张兴明
Original assignee: 之江实验室
Priority date: 2021-05-27
Filing date: 2021-08-10
Publication date: 2022-12-01
Also published as: CN113031496A; JP2023533599A; CN113031496B

Abstract

The present invention relates to the field of control, and in particular to an industrial protocol mapping structure and method based on an FPGA. The structure comprises a central processing unit (CPU) and an FPGA chip, which are connected to each other. The FPGA chip is provided with a mapping module, a mapping form module, a framing module and a clock reset module, wherein the clock reset module controls and is connected to the mapping module, the mapping form module and the framing module, respectively; the framing module receives data from a serial port, completes framing of a protocol according to frame byte data that is received from the serial port, and outputs a message frame to the mapping module; and the mapping module is connected to the mapping form module. By means of the present invention, RS-232 and the RS-485 interfaces are used, such that large-scale networking for an industrial control system can be realized, and mutual communication between PLCs and instruments of different manufacturers can be realized; and an FPGA chip is used, thereby ensuring the accuracy, real-time performance and reliability of data transmission.

Description

An FPGA-based industrial protocol mapping structure and method

technical field

The invention relates to the field of control, in particular to an FPGA-based industrial protocol mapping structure and method.

Background technique

FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is a product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original editable device gates.

A communication protocol, also known as a communication protocol, refers to an agreement between the communication parties to control data transmission. The agreement includes unified regulations on issues such as data format, synchronization method, transmission speed, transmission steps, error detection and correction methods, and control character definitions, which must be followed by both parties at the same time. Each instrument has its own unique communication protocol, the common ones are modbus communication protocol, RS-232 communication protocol, RS-485 communication protocol, PPI communication protocol, mewtocol communication protocol, etc.

The current industrial protocols are mainly interconnected through serial ports and field buses, and the transmission distance is limited; in industrial scenarios, different instruments need to be used, and due to different protocols, there are limitations in the communication between instruments; the execution of control information in the production process The accuracy requirements are getting higher and higher, and the accuracy and real-time performance of data transmission can reach the accuracy requirements of microsecond level.

Contents of the invention

Aiming at the problems of short transmission distance and limitations of different transmission protocols in the existing industrial protocol transmission, the present invention proposes an FPGA-based industrial protocol mapping structure and method, which can realize large-scale and long-distance data transmission requirements , to ensure the accuracy, versatility and reliability of data transmission, the specific technical solutions are as follows:

A kind of industrial protocol mapping structure based on FPGA, comprising: connected central processing unit CPU and FPGA chip, described FPGA chip is provided with mapping module, mapping table module, framing module and clock reset module, and described clock reset module controls respectively Connect the mapping module, the mapping form module, and the framing module. The framing module receives data from the serial port, and completes the framing of the protocol according to the frame byte data received from the serial port, and outputs the message frame to the mapping module. The mapping module Links with the Mapping Forms module.

Further, the mapping form module includes: PLC type mapping form plctypeform and basic mapping form mapform, the basic mapping form mapform is used to indicate address, register type, position in the frame of the order, and the form exists in the form of RAM , a total of 16 entries, a depth of 16, and a width of 24; the PLC type mapping form plctypeform has a total of 256 entries, which are used to classify PLCs in the subnet. The subnet supports a maximum of 256 PLC accesses, a total of 4 A type mapping method, the type is 0 to 3, the form exists in the form of RAM, the depth is 256, and the width is 3.

Further, the mapping module includes: protocol type register, port number register, role register, cmd command register, edge computing register, data conversion register; the protocol type register: used to configure the protocol type; the port number Register: 4bit, used to configure the port number of the current port port; the role register: 2bit, used to configure the role of the current port port; the cmd command register: 64bit, used to configure the command register, the first 32bit represents writing, and the latter 32bit represents read; the edge computing register: 32bit, used to store edge computing data; the data conversion register: 2bit, used to configure data conversion.

Further, the message frame is a complete message frame, and the data interface between the framing module and the mapping module is 8 bits.

Further, the clock reset module includes: a clock module and a reset module; the clock module uses the 50M clock of the backplane to generate a 125Mhz clock through PLL frequency multiplication, so that the overall system is in a unified clock domain of 125Mhz; the reset module , make the system high reset, when the clock module generates a stable 125Mhz clock signal, the locked signal of the clock module is pulled high, and use the lock signal of the clock module to count, when the count reaches 3F, the system high reset.

A method for mapping industrial protocols based on FPGA, comprising the steps of:

S1. When the CPU is initialized, configure the basic mapping form mapform according to the user-defined content. The type of the form includes the location of the source protocol, the number of bytes occupied by the source protocol, and the entries include configuration mapping commands, register types, data, and purpose. address, the depth of the mapping form is 16, and the width is 24; after the form is initialized, the corresponding data in the message frame extracted from the serial port is taken out, and the data type is marked for future edge computing and data conversion. ;

S2. Extract the SLAVE ID of the PLC according to the basic mapping form mapform, and then query the PLC type mapping form plctypeform according to the SLAVE ID of the PLC to obtain the current PLC type. According to the PLC type, query the form of edge computing, and compare it with the CPU configuration in the form. Edge_reg data is compared, if it is not satisfied, the packet will be lost, and if it is satisfied, it will be passed to the next-level bus switching module;

S3. Take out the corresponding data of the edge computing and pass it to the edge computing module;

S4. Finally, the data block is extracted from the RAM of the mapform.

Advantages of the present invention:

The present invention adopts RS-232 and RS-485 interfaces to realize large-scale networking of industrial control systems, and realizes mutual communication between PLCs and instruments of different manufacturers; adopts FPGA chips to ensure the accuracy, real-time and reliability of data transmission sex.

Description of drawings

Fig. 1 is a schematic diagram of a hardware frame structure of the present invention;

Fig. 2 is a schematic flow chart of the mapping method of the present invention;

Fig. 3 is a schematic diagram of the clock reset module of the present invention;

Among them, 1 is a mapping form module, 2 is a mapping module, 3 is a clock reset module, and 4 is a frame module.

Detailed ways

In order to make the purpose, technical solution and technical effect of the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

As shown in Figure 1, an FPGA-based industrial protocol mapping structure includes: a connected central processing unit CPU and an FPGA chip. The central processing unit CPU is used to realize data interaction and configuration of registers, and realize communication, logic control and data processing. The FPGA chip is used for receiving, analyzing and mapping serial port data, provides a unified external serial port, and is compatible with traditional industrial instruments and PLC devices.

The FPGA chip is provided with a mapping module 2, a mapping form module 1, a framing module 4 and a clock reset module 3.

The mapping form module 1 includes: PLC type mapping form plctypeform and basic mapping form mapform.

The basic mapping form mapform is used to indicate the positions of addresses, register types, commands, etc. in the frame, and the form exists in the form of RAM, with a total of 16 entries, a depth of 16, and a width of 24.

The PLC type mapping form plctypeform has a total of 256 entries, which are used to classify the PLCs in the subnet. The subnet supports a maximum of 256 PLC accesses. There are 4 types of mapping methods, and the types are 0 to 3. The form uses RAM The form exists with a depth of 256 and a width of 3.

The central processing unit CPU extracts relevant data in the frame by configuring the basic mapping form and the PLC type mapping form.

The mapping module 2 supports protocols such as modbus RTU, modbus ASCII, MEWTOCOL, hostlink and PPI.

Mapping module 2 includes: protocol type register, port number register, role register, cmd command register, edge computing register, datacoversion data conversion register.

Protocol type register framing_mode: used to configure the protocol type.

Port number register port_num: 4bit, used to configure the port number of the current port.

role register: 2bit, used to configure the role of the current port, for example: 00 represents slave, 01 represents master1, 02 represents master2, and 11 represents master3.

cmd command register cmd_reg: 64bit, used to configure the command register, the first 32bit represents writing, and the last 32bit represents reading.

edge edge computing register edge_reg: 32bit, edge computing register.

datacoversion data conversion register: 2bit, used to configure data conversion, for example, 00 and 11: means no data conversion is required, 01: binary to ASCII code, 10: ASCII to binary.

Described framing module 4 receives the data from serial port, and according to receiving frame byte data from serial port controller, completes the framing functions of protocols such as Profibus, PPI, Mewtocol (ASCII), Modbus ASCII, Hostlink+FINS, Modbus RTU. The input from the framing module is a complete message frame, and the data interface is 8bit.

As shown in Figure 3, the clock reset module 3 includes: a clock module and a reset module, which are used to provide a stable and unified clock source for protocol mapping, provide a reference source for the transmission of deterministic data, and provide a reference source for the normal operation of the protocol mapping module. Running provides power-on and power-down sequence requirements.

Wherein, the clock module: the overall system is in the 125Mhz clock domain, using the 50M clock on the backplane to generate a 125Mhz clock through PLL frequency multiplication.

Reset module: The whole system is high reset. When the clock module generates a stable 125Mhz clock signal, the locked signal will be pulled high, and the lock signal of the clock module is used for counting. When the count reaches 3F, the overall system is high reset .

As shown in Figure 2, an FPGA-based industrial protocol mapping method specifically includes the following steps:

S1. Extract the SLAVE ID according to the mapform: when the CPU is initialized, it first configures the basic mapping form mapform. The type of the form includes the location of the source protocol, the number of bytes occupied by the source protocol, and the entries include configuration mapping commands, register types, data, The destination address, etc., the content of the specific form can be defined by the user, the depth of the mapping form is 16, and the width is 24; after the initialization of the form is completed, the corresponding data in the message frame extracted from the serial port is taken out, and the The data type is marked for future use in edge computing and data conversion;

S2. Query the PLC type corresponding to the SLAVE ID according to the plctypeform: then query the SLAVE ID of the PLC according to the basic mapping form mapform, and then query the PLC type mapping form plctypeform according to the SLAVE ID of the PLC to obtain the current PLC type, and query edge computing according to the PLC type and compare it with the edge_reg data configured by the CPU in the form. If it is not satisfied, the packet will be discarded, and if it is satisfied, it will be passed to the next-level bus switching module;

S3. Extract edge computing data according to edge_reg: take out the corresponding data of edge computing and pass it to the edge computing module;

S4. Finally, the data block is extracted from the RAM of the mapform.

In the process of data communication, the invention can carry out hierarchical transmission according to the importance of data, so as to ensure the real-time performance, reliability and accuracy of high-priority data.

Those of ordinary skill in the art can understand that the above description is only a preferred example of the invention, and is not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, for those skilled in the art, it can still be understood. The technical solutions described in the foregoing examples are modified, or some of the technical features are equivalently replaced. All modifications, equivalent replacements, etc. within the spirit and principles of the invention shall be included in the scope of protection of the invention.

Claims

A kind of industrial protocol mapping structure based on FPGA, comprising: central processing unit CPU and FPGA chip connected, it is characterized in that, described FPGA chip is provided with mapping module (2), mapping table module (1), framing module (4 ) and a clock reset module (3), the clock reset module (3) controls the connection mapping module (2), the mapping form module (1), and the framing module (4) respectively, and the framing module (4) receives from data of the serial port, and complete the framing of the protocol according to receiving the frame byte data from the serial port, and output the message frame to the mapping module (2), and the mapping module (2) is connected with the mapping form module (1).
A kind of FPGA-based industrial protocol mapping structure as claimed in claim 1, is characterized in that, described mapping form module (1), comprises: PLC type mapping form plctypeform and basic mapping form mapform, described basic mapping form mapform uses In order to indicate the position in the frame of address, register type, order, this form exists with the form of RAM, totally 16 entries, and depth is 16, and width is 24; The total 256 entries of described PLC type mapping table plctypeform are used for giving The PLCs in the subnet are classified. The subnet supports a maximum of 256 PLC accesses. There are 4 types of mapping methods, the type is 0-3, and the form exists in the form of RAM with a depth of 256 and a width of 3.
A kind of FPGA-based industrial protocol mapping structure as claimed in claim 1, is characterized in that, described mapping module (2), comprises: protocol type register, port number register, role register, cmd command register, edge computing register , data conversion register; the protocol type register: used to configure the protocol type; the port number register: 4bit, used to configure the port number of the current port port; the role register: 2bit, used to configure the role of the current port port ; The cmd command register: 64bit, used to configure the command register, the first 32bit represents writing, and the last 32bit represents reading; the edge computing register: 32bit, used to store edge computing data; the data conversion register: 2bit, used for configuration data conversion.
A kind of FPGA-based industrial protocol mapping structure as claimed in claim 1, is characterized in that, described message frame is complete message frame, the data interface between framing module (4) and mapping module (2) It is 8bit.
A kind of industrial protocol mapping structure based on FPGA as claimed in claim 1, is characterized in that, described clock reset module (3), comprises: clock module and reset module; Described clock module uses the 50M clock of bottom board to pass PLL times Generate a 125Mhz clock at a high frequency, so that the overall system is in a unified clock domain of 125Mhz; the reset module makes the system a high reset, when the clock module generates a stable 125Mhz clock signal, the locked signal of the clock module is pulled high, and Use the lock signal of the clock module to count, when the count reaches 3F, the system resets high.
A kind of FPGA-based industrial protocol mapping method is characterized in that, comprises the steps:

S1. When the CPU is initialized, configure the basic mapping form mapform according to the user-defined content. The type of the form includes the location of the source protocol, the number of bytes occupied by the source protocol, and the entries include configuration mapping commands, register types, data, and purpose. address, the depth of the mapping form is 16, and the width is 24; after the form is initialized, the corresponding data in the message frame extracted from the serial port is taken out, and the data type is marked for future edge computing and data conversion. ;

S2. Extract the SLAVE ID of the PLC according to the basic mapping form mapform, and then query the PLC type mapping form plctypeform according to the SLAVE ID of the PLC to obtain the current PLC type. According to the PLC type, query the form of edge computing, and compare it with the CPU configuration in the form. Edge_reg data is compared, if it is not satisfied, the packet will be lost, and if it is satisfied, it will be passed to the next-level bus switching module;

S3. Take out the corresponding data of the edge computing and pass it to the edge computing module;

S4. Finally, the data block is extracted from the RAM of the mapform.