JP2023164305A - Semiconductor light-emitting element - Google Patents

Abstract

To provide a semiconductor light-emitting element configured to improve light-emitting efficiency and heat dissipation efficiency.SOLUTION: A semiconductor light-emitting element 1 includes, in plan view: an n-side semiconductor layer 11 having a first region R1, a second region R2 on an outer periphery of the first region, and a plurality of third regions R3 surrounded by the first region; a semiconductor structure 10 having a light-emitting layer 12 on the first region and a p-side semiconductor layer 13 on the light-emitting layer; a first insulating film 20 having a plurality of first openings h1 on the third region and a plurality of second openings h2 on the p-side semiconductor layer; an n-side electrode 40 connected to the n-side semiconductor layer at the plurality of first openings on the first insulating film; an n pad electrode 60 connected to the n-side electrodes in the second region; a second insulating film 30 having a plurality of third openings h3 arranged in positions overlapping the plurality of second openings on the first insulating film; and a p pad electrode 70 electrically connected to the p-side semiconductor layer at the plurality of third openings on the second insulating film. The pad electrodes cover the first and third regions. The plurality of first openings are arranged around the third openings.SELECTED DRAWING: Figure 2

Description

The invention according to the present disclosure relates to a semiconductor light emitting device.

Patent Document 1 describes a semiconductor laminated portion in which a first semiconductor layer, an active layer, and a second semiconductor layer are laminated, an n-electrode electrically connected to the first semiconductor layer, and a semiconductor layer that is connected to the second semiconductor layer. A light emitting device is disclosed that has a p-electrode and an n-electrode that are electrically connected. In such a light emitting element, it has been proposed that the first plating electrode formed on the p-electrode be formed so as to cover the conductive portion between the first semiconductor layer and the n-electrode.

Patent No. 5985782

In the semiconductor light emitting device disclosed in Patent Document 1, further improvements in luminous efficiency and heat dissipation are required.

The present disclosure aims to provide a semiconductor light emitting device having high luminous efficiency and high heat dissipation.

In order to achieve the above object, a semiconductor light emitting device according to the present disclosure includes:
In plan view, an n-side semiconductor layer including a first region, a second region located on the outer periphery of the first region, and a plurality of third regions surrounded by the first region; a semiconductor structure having a light emitting layer disposed on the light emitting layer; and a p-side semiconductor layer disposed on the light emitting layer;
a first insulating film disposed on the semiconductor structure and having a plurality of first openings disposed on the third region and a plurality of second openings disposed on the p-side semiconductor layer; and,
an n-side electrode disposed on the first insulating film and electrically connected to the n-side semiconductor layer through the plurality of first openings;
an n-pad electrode arranged in the second region and electrically connected to the n-side electrode;
a second insulating film disposed on the first insulating film and having a plurality of third openings disposed at positions overlapping with the plurality of second openings;
a p pad electrode disposed on the second insulating film and electrically connected to the p-side semiconductor layer through the plurality of third openings;
In plan view, the p pad electrode covers the first region and the third region,
In plan view, the plurality of first openings are arranged around the third opening.

According to the semiconductor light emitting device according to the present disclosure configured as described above, it is possible to improve luminous efficiency and heat dissipation.

FIG. 1 is a plan view of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 1 is a cross-sectional view of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 3 is a plan view of a p-side electrode of a semiconductor light emitting device. FIG. 3 is a plan view of an n-side contact electrode of a semiconductor light emitting device. FIG. 2 is a plan view of an n-side wiring section of a semiconductor light emitting device. FIG. 3 is a plan view of a first insulating film of a semiconductor light emitting device. FIG. 3 is a plan view of a second insulating film of a semiconductor light emitting device. It is a top view of the semiconductor light emitting element based on modification 1A of one embodiment. It is a top view of the semiconductor light emitting element based on modification 1B of one embodiment. FIG. 7 is a plan view of a semiconductor light emitting device according to a second modification of one embodiment. FIG. 7 is a plan view of a semiconductor light emitting device according to modification example 3 of one embodiment. FIG. 7 is a plan view of a semiconductor light emitting device according to a fourth modification of one embodiment. FIG. 7 is a plan view of a semiconductor light emitting device according to a fifth modification of one embodiment. FIG. 2 is a flow diagram showing a manufacturing flow of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 2 is a plan view of a semiconductor light emitting device according to Example 1 used in a first demonstration test and a second demonstration test. FIG. 3 is a plan view of a semiconductor light emitting device according to Example 2 used in a first demonstration test and a second demonstration test. FIG. 7 is a plan view of a semiconductor light emitting device according to Example 3 used in a first demonstration test and a second demonstration test. FIG. 7 is a plan view of a semiconductor light emitting device according to Example 4 used in a first demonstration test and a second demonstration test. FIG. 7 is a plan view of a semiconductor light emitting device according to Example 5 used in a first demonstration test. FIG. 7 is a plan view of a semiconductor light emitting device according to Example 6 used in a first demonstration test. FIG. 7 is a plan view of a semiconductor light emitting device according to Example 7 used in a first demonstration test. FIG. 3 is a plan view of a semiconductor light emitting device according to a comparative example used in a first demonstration test. As a first demonstration test, it is a graph showing the relationship between the number of n-side conductive parts and the relative output of a semiconductor light emitting element according to an example and a comparative example. 7 is a graph showing the relationship between the number of n-side conductive parts and the forward voltage Vf of a semiconductor light emitting element according to an example and a comparative example as a first demonstration test. It is a graph showing the relationship between the number of n-side conductive parts and the output of the semiconductor light emitting device according to the example as a second demonstration test. As a second demonstration test, it is a graph showing the relationship between the number of n-side conductive parts and the forward voltage Vf of the semiconductor light emitting device according to the example.

As shown in FIGS. 1 and 2, a semiconductor light emitting device 1 of the present disclosure includes a semiconductor structure 10, a first insulating film 20, a second insulating film 30, an n-side electrode 40, an n-pad electrode 60, and a p-pad. An electrode 70 is provided.
The semiconductor structure 10 has an n-side semiconductor layer 11, a light emitting layer 12, and a p-side semiconductor layer 13.
The n-side semiconductor layer 11 has a first region R1, a second region R2 located at the outer periphery of the first region R1, and a plurality of third regions R3 surrounded by the first region R1.
The first insulating film 20 includes a plurality of first openings h1 arranged on the third region R3 and a plurality of second openings h2 arranged on the p-side semiconductor layer 13.
The second insulating film 30 includes a plurality of third openings h3 arranged at positions overlapping with the plurality of second openings h2.
The n-side electrode 40 is electrically connected to the n-side semiconductor layer 11 through the plurality of first openings h1. The n-side electrode 40 is electrically connected to the n-pad electrode 60. The n-side semiconductor layer 11 and the n-pad electrode 60 are electrically connected via the n-side electrode 40.
The p pad electrode 70 is arranged on the second insulating film 30 and electrically connected to the p-side semiconductor layer 13 through the plurality of third openings h3.
In plan view, the p pad electrode 70 covers the first region R1 and the third region R3, and the plurality of first openings h1 are arranged around the third opening h3.

According to the above configuration, since the p pad electrode 70 covers the first region R1 and the third region R3 in plan view, the heat generated in the semiconductor light emitting element 1 can be radiated by the p pad electrode 70. Furthermore, in plan view, the plurality of first openings h1 are arranged around the third opening h3. Therefore, when a current is passed through the semiconductor light emitting device 1, electrons supplied from the n-side electrode 40 through the first opening h1 are transferred to the third opening h3 side (p-side semiconductor layer side) disposed around the n-side electrode 40. Easy to move towards. Thereby, the light emitting efficiency of the semiconductor light emitting device 1 can be improved.

As described above, the semiconductor light emitting device of the present disclosure can improve luminous efficiency and appropriately dissipate heat generated as the semiconductor light emitting device emits light.

More specific forms will be described in detail below. FIG. 1 is a plan view of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view of a semiconductor light emitting device according to an embodiment of the present disclosure. FIG. 3 is a plan view of the p-side electrode of the semiconductor light emitting device. FIG. 4 is a plan view of the n-side contact electrode of the semiconductor light emitting device. FIG. 5 is a plan view of the n-side wiring section of the semiconductor light emitting device. FIG. 6 is a plan view of the first insulating film of the semiconductor light emitting device. FIG. 7 is a plan view of the second insulating film of the semiconductor light emitting device. First, a semiconductor light emitting device according to an embodiment of the present disclosure will be described with reference to FIGS. 1 to 7.

<<Embodiment of semiconductor light emitting device>>
The semiconductor light emitting device 1 according to the first embodiment of the present disclosure includes a semiconductor structure 10, an n-side electrode 40, an n-pad electrode 60, a first insulating film 20, a second insulating film 30, and a p-side electrode 50. and a p pad electrode 70.

1. Semiconductor Structure The semiconductor structure 10 includes an n-side semiconductor layer 11 , a light-emitting layer 12 , and a p-side semiconductor layer 13 on a substrate 14 . In plan view, the semiconductor structure 10 has, for example, a rectangular shape. An example of the semiconductor structure 10 is to use a nitride semiconductor such as In _X Al _Y Ga _1-XY N (0≦X, 0≦Y, X+Y≦1). Note that examples of the nitride semiconductor include GaN, InGaN, AlGaN, AlInGaN, and the like. The light emitting layer 12 can have, for example, a quantum well structure including a plurality of well layers and a plurality of barrier layers. For example, the semiconductor structure 10 emits ultraviolet light (for example, B wave with a peak wavelength of 280 nm or more and 315 nm or less or C wave with a peak wavelength of 100 nm or more and 280 nm or less). In particular, when emitting light having the wavelength of the above-mentioned B wave or C wave, the light emitting layer 12 preferably includes an AlGaN layer having an Al composition ratio of 40% to 60%. The light emitting layer 12 includes, for example, a well layer and a barrier layer made of an AlGaN layer having an Al composition ratio of 40% or more and 60% or less.

The n-side semiconductor layer 11 includes a first region R1 where the light-emitting layer 12 and the p-side semiconductor layer 13 are arranged, and a second region R2 and a third region R3 where the light-emitting layer 12 and the p-side semiconductor layer 13 are not arranged. (See Figures 1 and 2).

As shown in FIG. 1, in plan view, the first region R1 is located at the center of the semiconductor structure 10 and has a continuous plane. The outer shape of the first region R1 is, for example, approximately octagonal. By making the outer shape of the first region R1 substantially octagonal, compared to the case where the outer shape of the first region R1 is substantially square, the vicinity of the position where laser light is irradiated in the step of cutting the substrate 14 described later is improved. The number of light-emitting layers 12 located in this structure can be reduced. Thereby, deterioration of the light emitting layer 12 due to laser light can be reduced.

The second region R2 is located on the outer periphery of the first region R1, and includes a region where the n-pad electrode 60 is arranged. As shown in FIGS. 1 and 4, the second region R2 is arranged along the outer periphery of the semiconductor structure 10. As shown in FIGS. Further, the second region R2 surrounds the first region R1. Note that the second region R2 is not limited to this aspect. For example, the second region R2 may be arranged only at each of the four corners of the semiconductor structure 10 without surrounding the first region R1, or may be arranged at at least one corner. good. Here, as shown in FIG. 2, the light emitting layer 12 and the p-side semiconductor layer 13 are not arranged in the second region R2. Therefore, light absorption by the light emitting layer 12 and the p-side semiconductor layer 13 in the second region R2 can be reduced more than when the light emitting layer 12 and the p-side semiconductor layer 13 are arranged in the second region R2.

The third region R3 is a region for electrically connecting the n-side electrode 40 and the n-side semiconductor layer 11. The third region R3 corresponds to the exposed position of the n-side semiconductor layer 11. A plurality of third regions R3 are arranged in the semiconductor structure 10. The plurality of third regions R3 are surrounded by the first region R1. In a plan view of the semiconductor structure 10, the plurality of third regions R3 are arranged within the continuous first region. The plurality of third regions R3 are arranged in an island shape. Note that the term "island-like" as used herein refers to a state in which the islands are individually separated and discontinuous in a plan view.

2. P-Side Electrode The p-side electrode 50 is electrically connected to the p-side semiconductor layer 13 located in the first region R1. For the p-side electrode 50, it is preferable to use a metal that reflects light from the light-emitting layer 12 toward the n-side semiconductor layer 11 side. For the p-side electrode 50, it is preferable to use a metal having a reflectance of 50% or more, preferably 60% or more with respect to the peak wavelength of light from the light emitting layer 12, for example, a metal such as Rh or Ru. It is preferable to use The p-side electrode 50 may have a laminated structure in which a plurality of metal layers are laminated. The p-side electrode 50 may have, for example, a laminated structure in which an Ru layer, a Ni layer, and an Au layer are laminated in this order from the semiconductor structure 10 side. Further, the p-side electrode 50 may have, for example, a laminated structure in which a Ti layer, a Rh layer, and a Ti layer are laminated in this order from the semiconductor structure 10 side. The thickness of the p-side electrode 50 may be, for example, 300 nm or more and 1500 nm or less. The p-side electrode 50 of the p-side electrode 50 is formed on substantially the entire upper surface of the p-side semiconductor layer 13 . The outer shape of the p-side electrode 50 is approximately octagonal in plan view. The p-side electrode 50 is not arranged in the second region R2 and the third region R3.

3. N-Side Electrode As shown in FIG. 2, the n-side electrode 40 includes an n-side contact electrode 41 and an n-side wiring section 42. The n-side contact electrode 41 is in contact with the n-side semiconductor layer 11 and is electrically connected to the n-side semiconductor layer 11 . The n-side wiring section 42 is in contact with the n-side contact electrode 41 and is electrically connected to the n-side semiconductor layer 11 via the n-side contact electrode 41 . In a plan view of the semiconductor light emitting device 1, the n-side contact electrode 41 and the p-side electrode 50 are separated from each other. In a plan view of the semiconductor light emitting device 1, a portion of the n-side wiring portion 42 overlaps a portion of the p-side electrode 50.

For the n-side contact electrode 41, for example, metals such as Ti, Al, Ni, Ta, Rh, Ru, Si, and Pt, or alloys containing these metals as main components can be used. For example, the n-side contact electrode 41 can have a stacked structure in which a Ti layer, an Al alloy layer, a Ta layer, a Ru layer, and a Ti layer are stacked in this order from the n-side semiconductor layer 11 side. The thickness of the n-side contact electrode 41 may be, for example, 500 nm or more and 800 nm or less. As shown in FIG. 4, the n-side contact electrode 41 is arranged in the second region R2 and the third region R3. The n-side contact electrode 41 includes a contact portion 41p, an n-side outer periphery conductive portion 41g, and a plurality of n-side conductive portions 41d. The contact portion 41p is arranged in the second region R2 located at the corner of the semiconductor structure 10, and is in contact with the n-side semiconductor layer 11. The contact portion 41p is arranged at a position corresponding to an n-pad electrode 60, which will be described later. The n-side outer periphery conductive portion 41g is in contact with the n-side semiconductor layer 11 in a second region R2 that does not overlap the n-pad electrode 60 in plan view. The plurality of n-side conductive portions 41d are arranged in the third region R3 and are in contact with the n-side semiconductor layer 11. The plurality of n-side conductive portions 41d are arranged in an island shape when viewed from above. The plurality of n-side conductive portions 41d are in contact with the n-side semiconductor layer 11 at a first opening h1, which will be described later. In plan view, the distance between the center points of two adjacent n-side conductive portions 41d is preferably 45 μm or more and 100 μm or less, and more preferably 45 μm or more and 80 μm or less. Here, the center point of the n-side conductive portion 41d is the center point of the shape of the n-side conductive portion 41d when viewed from above. For example, in the n-side conductive portion 41d having a circular shape in plan view shown in FIG. 4, the center of the circle is the center point of the n-side conductive portion 41d. Further, the n-side outer circumferential conductive portion 41g may be arranged outside the outer edge of the p pad electrode 70, which will be described later, in plan view.

The n-side wiring part 42 can use the same metal as the above-described n-side contact electrode 41. As an example, the n-side wiring section 42 can have a stacked structure in which a Ti layer, an Al alloy layer, and a Ti layer are stacked in this order from the semiconductor structure 10 side. The thickness of the n-side wiring portion 42 may be, for example, 400 nm or more and 600 nm or less. As shown in FIGS. 4 and 5, the n-side wiring section 42 includes an n-side outer periphery conductive section 41g and a plurality of contact sections 41p arranged in the second region R2, and a plurality of contact sections 41p arranged in the third region R3. It is electrically connected to the n-side conductive portion 41d.

In plan view, the n-side wiring section 42 continuously covers the semiconductor structure 10. In other words, the n-side wiring section 42 covers the entire semiconductor structure 10. As shown in FIG. 5, the n-side wiring section 42 includes a plurality of openings. Each of the plurality of openings of the n-side wiring section 42 is arranged at a position overlapping with a second opening h2 of the first insulating film 20, which will be described later. Further, in a cross-sectional view, the n-side wiring portion 42 covers the side surface of the semiconductor structure 10 and a part of the top surface of the semiconductor structure 10. In this way, in a plan view, the n-side wiring portion 42 covers the semiconductor structure 10, so that the light directed toward the n-side wiring portion 42 from the light emitting layer 12 can be reflected toward the substrate 14 side. can.

4. First Insulating Film As shown in FIG. 2, the first insulating film 20 is disposed on the semiconductor structure 10. In cross-sectional view, the first insulating film 20 is disposed between the n-side contact electrode 41 and the p-side electrode 50, and electrically insulates the n-side contact electrode 41 and the p-side electrode 50. Further, the first insulating film 20 is disposed between the n-side wiring section 42 and the p-side electrode 50, and electrically insulates the n-side wiring section 42 and the p-side electrode 50. The first insulating film 20 has a plurality of first openings h1 for electrically connecting the n-side wiring section 42 and the n-side contact electrode 41, and electrically connecting the p-side electrode 50 and the p pad electrode 70. A plurality of second openings h2 for connection are provided. The first insulating film 20 includes a plurality of first openings h1 arranged on the third region R3 and a plurality of second openings h2 arranged on the first region R1.

As shown in FIG. 1, in the semiconductor light emitting device 1 according to the first embodiment of the present disclosure, the plurality of first openings h1 are arranged around the second opening h2. For example, four first openings h1 are arranged for one second opening h2. In the direction parallel to the diagonal line of the substrate 14, the first opening h1 is arranged, for example, between two adjacent second openings h2. In plan view, the first opening h1 and the second opening h2 are arranged in a staggered manner. Note that in this specification, "staggered" refers to a state in which the plurality of first openings h1 and the plurality of second openings h2 are arranged alternately. Note that in the direction parallel to one side of the substrate 14, the first opening h1 may be arranged between two adjacent second openings h2. The plurality of second openings h2 may be arranged around the first opening h1. In plan view, it is preferable that the plurality of first openings h1 and the plurality of second openings h2 are arranged at approximately equal intervals. Thereby, the uniformity of the distribution of emission intensity can be improved.

As shown in FIGS. 2 and 6, the first insulating film 20 includes a plurality of openings A1 for electrically connecting the n-side contact electrode 41 and the n-side wiring section 42. As shown in FIGS. The first insulating film 20 can be made of SiO ₂ or SiN. The thickness of the first insulating film 20 is, for example, 500 nm or more, and preferably 500 nm or more and 1000 nm or less. The thickness of the first insulating film 20 may be partially different. For example, the thickness of the first insulating film 20 disposed on the p-side electrode 50 may be different from the thickness of the first insulating film 20 disposed on the n-side contact electrode 41.

5. Second Insulating Film As shown in FIG. 2, the second insulating film 30 is disposed on the semiconductor structure 10. The second insulating film 30 is disposed between the n-side wiring section 42 and the p-pad electrode 70, and electrically insulates the n-side wiring section 42 and the p-pad electrode 70. Further, the second insulating film 30 is arranged between the n-pad electrode 60 and the p-pad electrode 70, and electrically insulates the n-pad electrode 60 and the p-pad electrode 70. The second insulating film 30 includes third openings h3 arranged corresponding to respective positions overlapping with the plurality of second openings h2 of the first insulating film 20.

In a plan view, the plurality of first openings h1 are arranged around the third opening h3, so that the portion where the n-side wiring section 42 and the n-side contact electrode 41 are electrically connected, and the p The side electrode 50 and the portion where the p pad electrode 70 is electrically connected can be arranged closer to each other. Therefore, it is possible to shorten the current path between the n-side semiconductor layer 11 and the p-side semiconductor layer 13 and increase the area where the current easily concentrates and has high luminous intensity, so that the semiconductor structure 10 can be used more efficiently. It can be made to emit light. In the semiconductor structure 10, when the n-side semiconductor layer 11 is exposed more, the area of the light emitting layer 12 becomes smaller. For example, the area where the n-side semiconductor layer 11 is exposed becomes larger in plan view by increasing the number of the plurality of third areas R3. By reducing the distance between the first opening h1 and the third opening h3, the light emitting efficiency of the semiconductor structure 10 can be maintained even when the area of the light emitting layer 12 is reduced. Further, the semiconductor structure 10 having the light-emitting layer 12 that emits ultraviolet light may use a semiconductor layer containing Al, and current tends to be difficult to diffuse in the planar direction of the semiconductor structure 10. Therefore, the present disclosure is more effective when using the semiconductor structure 10 having the light emitting layer 12 that emits ultraviolet light.

It is preferable that the number of second openings h2 and the number of third openings h3 are the same. The number of second openings h2 may be different from the number of third openings h3. In the semiconductor structure 10, when the second insulating film 30 has the third opening h3, the first insulating film 20 has a second opening h2 corresponding to the third opening h3. The p-side electrode 50 and the p pad electrode 70 are electrically connected through the third opening h3. In a plan view, when the third opening h3 and the second opening h2 have a circular shape, the diameter of the third opening h3 may be made larger than the diameter of the second opening h2. According to this configuration, when electrically connecting the p-pad electrode 70 and the p-side electrode 50, the p-pad electrode 70 is appropriately connected to the opening where the second opening h2 and the third opening h3 are continuous. can be placed.

As shown in FIGS. 2 and 7, the second insulating film 30 includes a plurality of openings A2 for electrically connecting the n-pad electrode 60 and the n-side wiring section 42. As shown in FIGS. The second insulating film 30 can be made of SiO ₂ or SiN. The thickness of the second insulating film 30 is, for example, 500 nm or more, and preferably 500 nm or more and 1000 nm or less. The thickness of the second insulating film 30 may be partially different. For example, the thickness of the second insulating film 30 disposed on the first insulating film 20 may be different from the thickness of the second insulating film 30 disposed on the n-side wiring section 42.

6. p pad electrode 70
As shown in FIG. 2, the p pad electrode 70 is electrically connected to the p-side electrode 50 through the third opening h3 of the second insulating film 30 and the second opening h2 of the first insulating film 20. The p pad electrode 70 can be made of the same metal as the n-side contact electrode 41 described above. The p pad electrode 70 can have, for example, a laminated structure in which a Ti layer, a Pt layer, and an Au layer are laminated in this order from the semiconductor structure 10 side. The thickness of the p pad electrode 70 is, for example, 800 nm or more and 1000 nm or less.

The p pad electrode 70 covers the first region R1 and the third region R3 in plan view. The p pad electrode 70 covers at least the light emitting layer 12 disposed on the first region R1. Therefore, heat caused by light emission of the semiconductor structure 10 can be radiated by the p pad electrode 70 covering the light emitting layer 12.

The area of the p pad electrode 70 is preferably larger than the area of the light emitting layer 12 in plan view from the viewpoint of radiating heat generated in the light emitting layer 12. Thereby, the heat generated in the light emitting layer 12 can be efficiently dissipated via the p pad electrode 70.

The outer edge of the p pad electrode 70 is preferably aligned with the outer edge of the p-side electrode 50 or located outside the outer edge of the p-side electrode 50 in cross-sectional view. Thereby, heat generated in the light emitting layer 12 can be efficiently radiated via the p-side electrode 50 and the p-pad electrode 70.

It is preferable that the p pad electrode 70 has a substantially octagonal shape in plan view. Thereby, it is possible to appropriately electrically connect to the p-side electrode 50 arranged in the first region R1. Further, in plan view, the shape of the p-side electrode 50 is preferably a substantially octagonal shape corresponding to the shape of the p pad electrode 70.

The semiconductor light emitting device 1 may further include a bonding member 80. The bonding member 80 is arranged on the n-pad electrode 60 and the p-pad electrode 70. As shown in FIG. 2, the joining member 80 may be arranged on the first region R1. If the bonding member 80 is placed on the p-pad electrode 70 located above the first opening h1, a load is applied to the second insulating film 30 during bonding, which may cause cracks or the like in the second insulating film 30. There is a possibility that the pad electrode 70 and the n-side electrode 40 will be short-circuited. In order to avoid such a short circuit, the bonding member 80 is preferably placed on the p-pad electrode 70 located above the third opening h3.

7. n pad electrode 60
In plan view, the n-pad electrode 60 is disposed outside the outer edge of the p-pad electrode 70 and is electrically connected to the n-side electrode 40. The n pad electrode 60 is arranged in the second region R2 and is electrically connected to the n-side semiconductor layer 11 via the contact portion 41p, the n-side wiring portion 42, and the n-side conduction portion 41d. From the viewpoint of simplifying the manufacturing process, it is preferable to use the same metal as the p-pad electrode 70 for the n-pad electrode 60. Note that the n-pad electrode 60 and the p-pad electrode 70 may be made of different metals.

Further, according to the embodiment of FIG. 1, a plurality of n-pad electrodes 60 are arranged outside the outer edge of the p-pad electrode 70 in plan view. Since a plurality of n pad electrodes 60 are arranged, the current density to the n-side wiring section 42 can be dispersed. Therefore, the bias in the emission intensity distribution of the semiconductor light emitting device 1 can be reduced. The n-pad electrode 60 is arranged in a second region R2 located at a corner of the semiconductor structure 10 in the second region R2. By arranging the n-pad electrode 60 at the corner of the semiconductor structure 10, reduction in the area of the light emitting layer 12 can be reduced.

The semiconductor light emitting device according to the first embodiment of the present disclosure described above includes a plurality of first openings h1 around a third opening h3 in plan view. In a plan view, a portion where the n-side semiconductor layer 11 is electrically connected to the n-side contact electrode 41 and the n-side wiring portion 42 via the first opening h1, and the p-side semiconductor layer 13 are connected to each other through the first opening h1. , and a portion electrically connected to the p-side electrode 50 via the third opening h3. Thereby, the current path between the n-side semiconductor layer 11 and the p-side semiconductor layer 13 can be shortened, and the semiconductor light-emitting device 1 can have a region of high emission intensity around the third opening h3. . Thereby, the semiconductor light emitting device 1 can have high luminous efficiency. The semiconductor light emitting device according to the first embodiment of the present disclosure includes a p pad electrode 70 that covers the first region R1 and the third region R3. The p pad electrode 70 covers the light emitting layer 12 arranged in the first region R1. As a result, the semiconductor light emitting device 1 can have a high heat dissipation property in which the heat generated by the light emission of the light emitting layer 12 can be efficiently dissipated by the p pad electrode 70.

<<Modifications of openings in first insulating film 20 and/or second insulating film 30>>
Next, modified examples of the semiconductor light emitting device according to the first embodiment of the present disclosure will be described below with reference to FIGS. 8 to 11. The modified example of the present disclosure is different from the semiconductor light emitting device according to the first embodiment described above in the position and/or shape of the opening in the first insulating film 20 and/or the second insulating film 30. The other configurations are basically the same as the semiconductor light emitting device according to the first embodiment of the present disclosure described above. This different configuration will be explained below.

-Modification 1A and Modification 1B-
In the semiconductor light emitting device 1 according to Modification Example 1A and Modification Example 1B, as shown in FIGS. 8A and 8B, the second insulating film 30 has a plurality of fourth openings h4 in addition to the plurality of third openings h3. This is different from the semiconductor light emitting device according to the first embodiment described above. The fourth opening h4, like the third opening h3, is arranged at a position overlapping the second opening h2 of the first insulating film 20. In the modification 1A shown in FIG. 8A, the fourth opening h4 includes the third opening h3 located closest to the n-pad electrode 60 among the plurality of third openings h3 in plan view, and the n-pad electrode It is located between 60 and 60. In modification 1A, a total of eight fourth openings h4 are arranged in plan view. Note that the number of fourth openings h4 is not particularly limited. In addition, in modification 1B shown in FIG. 8B, the fourth opening h4 includes the first opening h1 located closest to the n-pad electrode 60 among the plurality of first openings h1, and the n-pad It is located between the electrode 60 and the electrode 60 . In FIG. 8B, a total of 12 fourth openings h4 are arranged in plan view. Three fourth openings h4 are arranged between the n-pad electrode 60 and the first opening h1 located closest to the n-pad electrode 60 among the plurality of first openings h1. The number of fourth openings h4 is not particularly limited. According to Modification 1A and Modification 1B, the p-pad electrode 70 and the p-side semiconductor layer 13 are electrically connected between the first opening h1 located closest to the n-pad electrode 60 and the n-pad electrode 60. A fourth opening h4 connected to is arranged. Therefore, the current path from the p-side semiconductor layer 13 to the n-side semiconductor layer 11 can be shortened, and the region where the current is concentrated and the emission intensity is high can be increased. In addition, in FIGS. 8A and 8B, the fourth opening h4 is a third opening located closest to each n-pad electrode 60 among all the n-pad electrodes 60 and the plurality of first openings h1. h3 or the first opening h1, but is not particularly limited to this form. If the fourth opening h4 is arranged between at least one n-pad electrode 60 and the third opening h3 or first opening h1 located closest to that one n-pad electrode 60, good. In plan view, the size of the fourth opening h4 is smaller than the size of the third opening h3 and the size of the second opening h2. The size of the fourth opening h4 may be the same as the size of the third opening h3 and/or the second opening h2, or may be larger. Note that the fourth opening h4 shown in FIG. 8A and the fourth opening h4 shown in FIG. 8B may be arranged in combination.

-Modification 2-
As shown in FIG. 9, the semiconductor light emitting device 1 according to the second modification has the above-mentioned features in that the second insulating film 30 has a plurality of fifth openings h5 in addition to the plurality of third openings h3. This is different from the semiconductor light emitting device according to the first embodiment. The fifth opening h5, like the third opening h3, is arranged at a position overlapping the second opening h2 of the first insulating film 20. The fifth opening h5 is located between the first opening h1, which is located closest to the n-side outer circumferential conducting part 41g among the plurality of first openings h1, and the n-side outer circumferential conducting part 41g, in a plan view. positioned. Thereby, the p pad electrode 70 and the p-side semiconductor layer 13 are electrically connected between the first opening h1 located closest to the n-side outer periphery conduction part 41g and the n-side outer periphery conduction part 41g. A fifth opening h5 will be arranged. Therefore, the current path from the p-side semiconductor layer 13 to the n-side semiconductor layer 11 can be shortened, and the region where the current is concentrated and the emission intensity is high can be increased. As shown in FIG. 9, in plan view, the size of the fifth opening h5 is smaller than the size of the third opening h3 or the size of the second opening h2. Note that the size of the fifth opening h5 may be the same as or larger than the size of the third opening h3 or the second opening h2. In FIG. 9, in plan view, the fifth opening h5 is connected to the first opening h1 located closest to the n-side outer circumferential conducting part 41g among the plurality of first openings h1, and the n-side outer circumferential conducting part 41g. There are three placed between them. The number of fifth openings h5 is not particularly limited. In addition, in FIG. 9, the fifth opening h5 is the first opening located closest to all the n-side outer circumferential conductive parts 41g and each of the n-side outer circumferential conductive parts 41g among the plurality of first openings h1. Although it is arranged between the part h1 and the part h1, it is not particularly limited to this form. The fifth opening h5 may be disposed between at least one n-side outer periphery conduction part 41g and the first opening h1 located near the one n-side outer periphery conduction part 41g.

-Modification 3-
As shown in FIG. 10, in the semiconductor light emitting device 1 according to Modification Example 3, the first insulating film 20 has a plurality of first openings h1 and also has a larger area than one first opening h1 in plan view. This is different from the semiconductor light emitting device according to the second modification example described above in that it has a sixth opening h6. The sixth opening h6 has an elliptical shape in plan view. Thereby, the contact area between the n-side semiconductor layer 11 and the n-side electrode 40 can be increased, so that an increase in forward voltage can be reduced. In plan view, the fifth opening h5 is arranged between the sixth opening h6 and the n-side outer circumferential conduction part 41g. Thereby, the current path from the p-side semiconductor layer 13 to the n-side semiconductor layer 11 can be shortened, and the region with high emission intensity can be increased.

Furthermore, in the semiconductor light emitting device 1 according to the third modification, the area of the fifth opening h5 is larger than the area of one third opening h3 in plan view, and the fifth opening h5 has an elliptical shape in plan view. It is the shape. Thereby, the contact area between the p-side semiconductor layer 13 and the p-side electrode 50 can be increased, so that an increase in forward voltage can be reduced. In plan view, elliptical fifth openings h5 and sixth openings h6 are arranged alternately. In FIG. 10, two fifth openings h5 that are elliptical in plan view and two sixth openings h6 that are elliptical in plan view are alternately arranged. The fifth opening h5 has an elliptical shape that is elongated in the direction in which the plurality of third openings h3 are arranged. The sixth opening h6 has an elliptical shape that is elongated in the direction in which the plurality of first openings h1 are arranged.

-Modification 4-
As shown in FIG. 11, the semiconductor light emitting device 1 according to the fourth modification has (1) the shape of the plurality of first openings h1, and (2) the shape of the plurality of first openings h1 and the plurality of third openings h3. The positional relationship is different from the semiconductor light emitting device 1 according to the first embodiment described above.

The shape of the first opening h1 is, for example, a parallelogram in plan view. When the shape of the first opening h1 is a parallelogram, it is preferable that the first opening h1 be arranged so that the distance between the corner of the parallelogram and the third opening h3 is short in plan view. With such a shape and arrangement, the first openings h1 can be arranged with high density so as to fill the gaps between the adjacent third openings h3. Note that the shape of the first opening h1 in plan view may be rectangular.

At least one side forming the outer shape of the first opening h1 is arranged to be parallel to at least one side forming the outer shape of the adjacent first opening h1. Thereby, the first openings h1 can be arranged at high density so as to fill the gaps between the adjacent third openings h3. In plan view, the area of the outer shape of the first opening h1 is larger than the area of the outer shape of the third opening h3. Thereby, the area of the n-side electrode 40 can be increased, and the number of locations where the distance between the n-side semiconductor layer 11 and the p-side semiconductor layer 13 is small can be increased.

As shown in FIG. 11, in a line parallel to one side of the substrate 14, the plurality of first openings h1 and the plurality of third openings h3 are arranged alternately.

In plan view, six first openings h1 are arranged around one third opening h3. As a result, the electrons supplied from the n-side electrode 40 through the first opening h1 can be moved radially toward the second opening h2 arranged around the second opening h2, thereby further improving the luminous efficiency. be able to. In addition, from the viewpoint of reducing the bias in the current density distribution around the third opening h3, six first openings h1 are arranged at the center of the third opening h3 and around one third opening h3. It is preferable that the distances between the centers of the two are equal.

Note that in addition to the plurality of third openings h3 of the second insulating film 30 and the plurality of second openings h2 of the first insulating film 20, the second insulating film 30 has the fifth openings h5 described in Modification 2. may have.

<<Modifications of configuration regarding pad electrodes>>
A further modification of the semiconductor light emitting device according to the first embodiment of the present disclosure will be described below with reference to FIG. 12. The modified example of the present disclosure is different from the semiconductor light emitting device according to the above-described first embodiment in the configuration regarding the n-pad electrode 60 and the p-pad electrode 70. The other configurations are basically the same as the semiconductor light emitting device according to the first embodiment of the present disclosure described above. This different configuration will be explained below.

-Modification 5-
As shown in FIG. 12, the semiconductor light emitting device 1 according to the fifth modification has an n-pad electrode 60 arranged at one corner out of four corners of the semiconductor light emitting device 1 in plan view. Moreover, the p-pad electrode 70 is arranged so as to cover the corners of the semiconductor light emitting device 1 except for the corner where the n-pad electrode 60 is arranged in plan view. Note that, as can be understood from FIG. 12, the area of the p pad electrode 70 is larger than the area of the n pad electrode 60 in plan view.

Further, the second region R2 where the n-pad electrode 60 is arranged is located at a corner of the semiconductor light emitting device 1. The first region R1 is located in an area excluding the second region R2 and the third region R3. Even in the semiconductor light emitting device 1 according to modification 5, the second region R2 is located at the outer periphery (or outside) of the first region R1. The p pad electrode 70 covers the light emitting layer 12 disposed in the first region R1. As a result, the semiconductor light emitting device 1 can have a high heat dissipation property in which the heat generated by the light emission of the light emitting layer 12 can be efficiently dissipated by the p pad electrode 70.

Further, in the semiconductor light emitting device 1 according to the fifth modification shown in FIG. 12, the n pad electrode 60 is arranged at the corner of the semiconductor structure 10, but the n pad electrode 60 is located at the outer edge of the semiconductor light emitting device 1 in plan view. It may be placed in the center of the sides that make up the . In this case, the outer shape of the p-pad electrode 70 may be a C-shape (or a U-shape) that surrounds the n-pad electrode 60 in a plan view.

Next, a method for manufacturing a semiconductor light emitting device according to the present disclosure will be described with reference to the manufacturing flow of FIG. 13 and the like.

1. Semiconductor Structure Preparation Step The semiconductor structure preparation step is a step of preparing the semiconductor structure 10. For example, the semiconductor structure 10 is prepared by forming the n-side semiconductor layer 11, the light emitting layer 12, and the p-side semiconductor layer 13 in this order on the substrate 14. The semiconductor structure 10 is formed by, for example, a known method such as MOCVD. Thereafter, in the semiconductor structure 10, a part of the n-side semiconductor layer 11 is removed from the light-emitting layer 12 and the p-side semiconductor layer 13 in the third region R3 described in the above-mentioned "semiconductor light-emitting device of the first embodiment". expose. As a method for exposing the n-side semiconductor layer 11, for example, a known etching technique can be employed.

2. N-side contact electrode forming step The n-side contact electrode forming step is a step of forming the n-side contact electrode 41 at a position where the n-side semiconductor layer 11 is exposed. For forming the n-side contact electrode 41, a known electrode forming technique can be employed. Examples of methods for forming the n-side contact electrode 41 include sputtering, vapor deposition, and the like. In the n-side contact electrode forming step, the n-side contact electrode 41 having a contact portion 41p, an n-side outer circumferential conducting portion 41g, and an n-side conducting portion 41d is formed. In the n-side contact electrode forming step, an insulating film may be formed on the outermost surface of the n-side contact electrode 41. The insulating film formed on the outermost surface of the n-side contact electrode 41 is removed in a step of forming a first opening h1 and a second opening h2 in the first insulating film 20 in a first insulating film forming step described later. can do.

3. P-side electrode forming step The p-side electrode forming step is a step of forming the p-side electrode 50 on the p-side semiconductor layer 13 of the semiconductor structure 10. For forming the p-side electrode 50, a known electrode forming technique can be employed. Examples of methods for forming the p-side electrode 50 include sputtering, vapor deposition, and the like. In the p-side electrode forming step, the p-side electrode 50 can be formed on the p-side semiconductor layer 13 in the first region R1. As shown in FIG. 3, the p-side electrode 50 has a plurality of circular openings in plan view. In the opening of the p-side electrode 50, the contact portion 41p of the n-side contact electrode 41 is exposed.

4. First Insulating Film Forming Step In the first insulating film forming step, the first insulating film 20 having the first opening h1 and the second opening h2 is formed on the above-mentioned n-side contact electrode 41 and p-side electrode 50. It is a process. The first insulating film 20 can be formed using a known insulating film forming technique. Examples of methods for forming the first insulating film 20 include sputtering, vapor deposition, and chemical vapor deposition.

The first insulating film forming step includes a step of forming the first insulating film 20 on the n-side contact electrode 41 and the p-side electrode 50, and a step of electrically connecting the first insulating film 20 with the n-side wiring part 42. forming a first opening h1, an opening A1, and a second opening h2 for electrical connection with the p pad electrode 70. The first opening h1 and the second opening h2 can be formed by forming a resist mask on the first insulating film 20 and then removing a part of the first insulating film 20 through the resist mask. . For example, a resist mask may be formed on the first insulating film 20 at positions corresponding to the first opening h1 and the second opening h2. A known etching technique can be used to remove the first insulating film 20. Examples of methods for removing the first insulating film 20 include wet etching and dry etching.

5. N-side wiring part forming process The n-side wiring part forming process is a process of forming the n-side wiring part 42 on the first insulating film 20 described above. For forming the n-side wiring section 42, it is possible to employ a known electrode forming technique. Examples of methods for forming the n-side wiring portion 42 include sputtering, vapor deposition, and the like. As shown in FIG. 5, the n-side wiring section 42 has a plurality of circular openings in plan view. The p-side electrode 50 is exposed in the opening of the n-side wiring section 42 . In the n-side wiring part forming step, an insulating film may be formed on the outermost surface of the n-side wiring part 42. The insulating film formed on the outermost surface of the n-side wiring section 42 can be removed in the step of forming the third opening h3 in the second insulating film 30 in the second insulating film forming step described later.

6. Second Insulating Film Forming Step The second insulating film forming step is a step of forming the second insulating film 30 having the third opening h3 on the n-side wiring section 42 described above. The third opening h3 may be formed at a position overlapping the second opening h2 in plan view. The second insulating film 30 can be formed using a known insulating film forming technique. Examples include sputtering, vapor deposition, and chemical vapor deposition. Further, the second insulating film 30 may be made of the same material as the first insulating film, or may be made of a different material.

The second insulating film forming step includes a step of forming the second insulating film 30 on the n-side wiring part 42, and a third opening h3 in the second insulating film 30 for electrically connecting to the p pad electrode 70. A step of forming a. The third opening h3 can be formed by forming a resist mask on the second insulating film 30 and then removing a portion of the second insulating film 30 through the resist mask. For example, a resist mask may be formed on the second insulating film 30 at a position corresponding to the second opening h2. A known etching technique can be used to remove the second insulating film 30. Examples of methods for removing the second insulating film 30 include wet etching and dry etching.

Note that, before performing the second insulating film forming step, a step of exposing the substrate 14 from the semiconductor structure 10 at the outer edge of the semiconductor light emitting device 1 may be included. The outer edge of the semiconductor light emitting device 1 is located outside the opening A1 in plan view. By performing the step of exposing the substrate 14 from the semiconductor structure 10, a portion of the side surface of the n-side semiconductor layer 11, a portion of the side surface of the first insulating film 20, and a portion of the side surface of the n-side wiring portion 42 are removed. and is exposed. In the second insulating film forming step, the second insulating film 30 may be formed on the exposed substrate 14. As shown in FIG. 2, a portion of the exposed side surface of the n-side semiconductor layer 11, a portion of the side surface of the first insulating film 20, and a portion of the side surface of the n-side wiring portion 42 are covered with a second insulating film. It can be covered by 30.

7. n-pad electrode and p-pad electrode forming step The n-pad electrode and p-pad electrode forming step includes forming an n-pad electrode 60 electrically connected to the n-side wiring section 42 and a p-pad electrode electrically connected to the p-side electrode 50. This is a step of forming a pad electrode 70. For forming the n-pad electrode 60 and the p-pad electrode 70, a known electrode formation technique can be employed. Examples of methods for forming the n-pad electrode 60 and the p-pad electrode 70 include sputtering, vapor deposition, and the like. N-pad electrode 60 and p-pad electrode 70 made of the same metal material can be formed at the same time. Note that the n-pad electrode 60 and the p-pad electrode 70 may be formed in separate steps using different metal materials.

A step of cutting the substrate 14 may be included after the step of forming the n-pad electrode and the p-pad electrode. The step of cutting the substrate 14 is a step of dividing the plurality of semiconductor light emitting devices 1 formed on the substrate 14 into a plurality of semiconductor light emitting devices 1 each including the substrate 14 . Examples of methods for cutting the substrate 14 include laser light irradiation, dicing with a blade, and the like.

According to the method for manufacturing a semiconductor light emitting device of the present disclosure, as explained in <<Semiconductor light emitting device of first embodiment>> above, it is possible to manufacture a semiconductor light emitting device with improved luminous efficiency and heat dissipation.

<<Description of the first demonstration test>>
A first demonstration test was conducted on the semiconductor light emitting device of the present disclosure. Specifically, semiconductor light emitting devices of Comparative Examples and Examples shown below were manufactured.

<Example>
First, common basic structures of the semiconductor light emitting devices of Examples 1 to 7 will be explained.

(Common structure of semiconductor light emitting devices of Examples 1 to 7)
Semiconductor light emitting devices 1A to 1G of Examples 1 to 7 shown in FIGS. 14A to 14G have basically the same basic structure as the first embodiment shown in FIGS. 1 to 7 described above. The semiconductor light emitting devices 1A to 1G of Examples 1 to 7 have a semiconductor structure 10, an n-side electrode 40, an n pad electrode 60, a first insulating film 20, a second insulating film 30, on a substrate 14, It includes a p-side electrode 50 and a p-pad electrode 70. Structures common to the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 will be described in detail below. As the substrate 14, a sapphire substrate was used. The substrate 14 is a square with one side measuring 1 mm in plan view. As the semiconductor structure 10, a nitride semiconductor was used in which an n-type semiconductor layer including an AlGaN layer with an Al composition ratio of 60% and a p-type semiconductor layer including an AlGaN layer with an Al composition ratio of 20% were stacked. . As the n-side contact electrode 41 of the n-side electrode 40, a 25 nm thick Ti layer, a 100 nm thick Al alloy layer, a 500 nm thick Ta layer, a 120 nm thick Ru layer, and a 120 nm thick Ti layer are laminated in this order. A laminated structure was used. As the n-side wiring section 42, a laminated structure was used in which a Ti layer with a thickness of 1.5 nm, an Rh layer with a thickness of 500 nm, and a Ti layer with a thickness of 10 nm were laminated in this order. As the first insulating film 20, a SiO ₂ layer with a thickness of 800 nm was used. As the p-side electrode 50, a laminated structure was used in which a Rh layer with a thickness of 100 nm, a Ni layer with a thickness of 6 nm, and an Au layer with a thickness of 7 nm were laminated in this order. As the second insulating film 30, a SiO ₂ layer with a thickness of 800 nm was used. As the n pad electrode 60 and the p pad electrode 70, a laminated structure in which a 200 nm thick Ti layer, a 200 nm thick Pt layer, and a 500 nm thick Au layer were laminated in this order was used.

In the semiconductor light emitting devices 1A to 1G of Examples 1 to 7, the first region R1 had an octagonal shape in plan view. The outer area of the first region R1 is 670,957 μm ² . Further, the outer shape of the p pad electrode 70 was made into an octagonal shape in plan view. The n-pad electrode 60 was placed at each of the four corners of the substrate 14 located outside the outer edge of the p-pad electrode 70. The semiconductor light emitting devices 1A to 1G of Examples 1 to 7 have a contact portion 41p of a common size and an n-side outer circumferential conduction portion 41g. In the semiconductor light emitting devices 1A to 1G of Examples 1 to 7, the combined area of the contact portion 41p and the n-side outer peripheral conduction portion 41g is 210,024 μm ² . In the semiconductor light emitting devices 1A to 1G of Examples 1 to 7, the outer shape of the n-side conductive portion 41d was circular in plan view. The diameter of one n-side conductive portion 41d is 20 μm and the area is 314 μm ² .

Next, the differences between the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 will be described in detail. The semiconductor light emitting devices 1A to 1G of Examples 1 to 7 each have a different total area of the n-side contact electrode 41 and a different total area of the light emitting layer 12. As the total area of the n-side contact electrode 41 increases, the total area of the light emitting layer 12 decreases. The semiconductor light emitting devices 1A to 1G of Examples 1 to 7 each have a different total area of the n-side conductive portion 41d.

(Semiconductor light emitting device 1A of Example 1: see FIG. 14A)
In the semiconductor light emitting device 1A of Example 1, the number of n-side conductive portions 41d was 156. The number of first openings h1 for arranging the n-side conductive portions 41d was 156.

In the semiconductor light emitting device 1A of Example 1, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was 145. The diameter of the third opening h3 of the semiconductor light emitting device 1A is 12 μm.

In the semiconductor light emitting device 1A of Example 1, the area of the n-side contact electrode 41 was 259,008 μm ² . Note that the "area of the n-side contact electrode" in this specification is the sum of the areas of the contact portion 41p, the n-side outer circumferential conducting portion 41g, and the n-side conducting portion 41d in plan view, as shown in FIG. It is the area.

In the semiconductor light emitting device 1A of Example 1, the area of the light emitting layer 12 was 529,465 μm ² . Note that the "area of the light emitting layer" in this specification is the area of the light emitting layer 12 in plan view, as shown in FIGS. 2 and 14A.

(Semiconductor light emitting device 1B of Example 2: see FIG. 14B)
In the semiconductor light emitting device 1B of Example 2, the number of n-side conductive portions 41d was 120. The number of first openings h1 for arranging the n-side conductive portions 41d was 120.

In the semiconductor light emitting device 1B of Example 2, the number of second openings h2 (or third openings h3) for establishing conduction of the p-side electrode 50 was 109. In plan view, the diameter of the third opening h3 of the semiconductor light emitting device 1B is 12 μm.

In the semiconductor light emitting device 1B of Example 2, the area of the n-side contact electrode 41 was 247,704 μm ² . Further, in the semiconductor light emitting device 1B of Example 2, the area of the light emitting layer 12 was 562,117 μm ² .

(Semiconductor light emitting device 1C of Example 3: see FIG. 14C)
In the semiconductor light emitting device 1C of Example 3, the number of n-side conductive parts 41d was 76. The number of first openings h1 for arranging the n-side conductive portions 41d was 76.

In the semiconductor light emitting device 1C of Example 3, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was 69. In plan view, the diameter of the third opening h3 of the semiconductor light emitting device 1C is 32 μm.

In the semiconductor light emitting device 1C of Example 3, the area of the n-side contact electrode 41 was 233,888 μm ² . Further, in the semiconductor light emitting device 1C of Example 3, the area of the light emitting layer 12 was 602,025 μm ² .

(Semiconductor light emitting device 1D of Example 4: see FIG. 14D)
In the semiconductor light emitting device 1D of Example 4, the number of n-side conductive portions 41d was 69. The number of first openings h1 for arranging the n-side conductive portions 41d was 69.

In the semiconductor light emitting device 1D of Example 4, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was set to 60. In plan view, the diameter of the third opening h3 of the semiconductor light emitting device 1D is 32 μm.

In the semiconductor light emitting device 1D of Example 4, the area of the n-side contact electrode 41 was 231,690 μm ² . Further, in the semiconductor light emitting device 1D of Example 4, the area of the light emitting layer 12 was 608,374 μm ² .

(Semiconductor light emitting device 1E of Example 5: see FIG. 14E)
In the semiconductor light emitting device 1E of Example 5, the number of n-side conductive portions 41d was 52. The number of first openings h1 for arranging the n-side conductive portion 41d was set to 52.

In the semiconductor light emitting device 1E of Example 5, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was set to 45. In plan view, the diameter of the third opening h3 of the semiconductor light emitting device 1E is 32 μm.

In the semiconductor light emitting device 1E of Example 5, the area of the n-side contact electrode 41 was 226,352 μm ² . Further, in the semiconductor light emitting device 1E of Example 5, the area of the light emitting layer 12 was 623,793 μm ² .

(Semiconductor light emitting device 1F of Example 6: see FIG. 14F)
In the semiconductor light emitting device 1F of Example 6, the number of n-side conductive parts 41d was 37. The number of first openings h1 for arranging the n-side conductive portion 41d was set to 37.

In the semiconductor light emitting device 1F of Example 6, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was set to 32. In plan view, the diameter of the third opening h3 of the semiconductor light emitting device 1F is 32 μm.

In the semiconductor light emitting device 1F of Example 6, the area of the n-side contact electrode 41 was 221,642 μm ² . Further, in the semiconductor light emitting device 1F of Example 6, the area of the light emitting layer 12 was 637,398 μm ² .

(Semiconductor light emitting device 1G of Example 7: see FIG. 14G)
In the semiconductor light emitting device 1G of Example 7, the number of n-side conductive parts 41d was set to 24. The number of first openings h1 for arranging the n-side conductive portions 41d was set to 24.

In the semiconductor light emitting device 1G of Example 7, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was set to 21. In plan view, the diameter of the third opening h3 of the semiconductor light emitting device 1G is 32 μm.

In the semiconductor light emitting device 1G of Example 7, the area of the n-side contact electrode 41 was 217,560 μm ² . Further, in the semiconductor light emitting device 1G of Example 7, the area of the light emitting layer 12 was 649,189 μm ² .

<Comparative example>
Next, the structure of a semiconductor light emitting device of a comparative example will be explained.

(Structure of semiconductor light emitting device of comparative example: see FIG. 14H)
The semiconductor light emitting element of the comparative example shown in FIG. , a first insulating film 120, a second insulating film 130, a p-side electrode 500, and a p-pad electrode 700. As the substrate 114, a sapphire substrate was used. The substrate 114 is a square with one side measuring 1 mm in plan view. The semiconductor structure 110 has an n-side semiconductor layer, a light emitting layer, and a p-side semiconductor layer. The n-side semiconductor layer has a first region R1', a second region located at the outer periphery of the first region R1', and a plurality of third regions R3' surrounded by the first region R1'. There is. The first insulating film includes a plurality of first openings h1' arranged on the third region R3' and a plurality of second openings h2' arranged on the p-side semiconductor layer. The second insulating film includes a plurality of third openings h3' arranged at positions overlapping with the plurality of second openings h2'. The n-side electrode 400 is electrically connected to the n-side semiconductor layer through a plurality of first openings h1'. N-side electrode 400 is electrically connected to n-pad electrode 600. The n-side semiconductor layer and the n-pad electrode 600 are electrically connected via the n-side electrode 400. The p pad electrode 700 is placed on the second insulating film and electrically connected to the p-side semiconductor layer through a plurality of third openings h3'. In plan view, the p pad electrode 700 covers the first region R1' and the third region R3', and the plurality of first openings h1' are arranged around the third opening h3'. The semiconductor light emitting device 100 of the comparative example differs from the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 in that the first opening h1' is also arranged under the n pad electrode 600. The semiconductor light emitting device 100 of the comparative example differs from the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 in that a light emitting layer is disposed under the n pad electrode 600. The semiconductor light emitting device 100 of the comparative example uses the same material and thickness as the semiconductor light emitting devices 1A to 1G of Examples 1 to 7.

In the semiconductor light emitting device 100 of the comparative example, the outer shape of the first region R1' was made into a quadrangular shape in plan view. The outer area of the first region R1' is 809,657 μm ² . Further, in the semiconductor light emitting device 100 of the comparative example, the p pad electrode 700 had a rectangular outer shape in plan view. In the semiconductor light emitting device 100 of the comparative example, the n-pad electrodes 600 were arranged at positions adjacent to two opposing sides in a plan view among the sides of the substrate. The outer shape of the n-pad electrode 600 was made into a rectangular shape in plan view.

In the semiconductor light emitting device 100 of the comparative example, the number of n-side conductive portions 410d was 81. The area of one n-side conductive portion 410d is 20 μm ² . The number of first openings h1' for arranging the n-side conductive portion 410d was 81.

In the semiconductor light emitting device 100 of the comparative example, the number of second openings h2' and third openings h3' for establishing conduction of the p-side electrode 500 was set to 48. The diameter of the third opening h3' of the semiconductor light emitting device 100 of the comparative example is 32 μm.

In the semiconductor light emitting device 100 of the comparative example, the area of the n-side contact electrode was 91,426 μm ² . Further, in the semiconductor light emitting device 100 of the comparative example, the area of the light emitting layer was 736,190 μm ² .

Table 1 shows the number of n-side conductive parts, the area of the n-side contact electrode, and the area of the light emitting layer for Examples 1 to 7 and Comparative Example.

As shown in Table 1, the area of the n-side contact electrode increases as the number of n-side conductive parts increases. Furthermore, the area of the light emitting layer decreases as the number of n-side conductive parts increases. The area of the n-side contact electrode 41 of the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 is larger than the area of the n-side contact electrode of the semiconductor light emitting device 100 of the comparative example. Further, the area of the light emitting layer 12 of the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 is smaller than the area of the light emitting layer of the semiconductor light emitting device 100 of the comparative example.

In the semiconductor light emitting device 100 of the comparative example, a light emitting layer is arranged under the n pad electrode 600. Therefore, the area of the n-side contact electrode of the semiconductor light-emitting device 100 of the comparative example is smaller than the area of the n-side contact electrode 41 of the semiconductor light-emitting devices 1A to 1G of Examples 1 to 7. Further, the number 410d of n-side conductive parts in the semiconductor light emitting device 100 of the comparative example is larger than that of Examples 3 to 7, but the area of the light emitting layer of the semiconductor light emitting device 100 of the comparative example is It is larger than the area of the light emitting layer 12 of the light emitting elements 1A to 1G.

Next, for Examples 1 to 7 and Comparative Example, the relative output, which is an index of brightness, and the forward voltage Vf were measured when a forward current of 350 mA was passed through the semiconductor light emitting device. Relative output is a value measured by passing a current between the p-side semiconductor layer and n-side semiconductor layer of a semiconductor light-emitting device in a wafer state to emit light, and receiving the emitted light with a photodiode. . A large relative output value means brightness, and a small value means darkness. Note that the values of forward voltage Vf (V) in Table 2 are values obtained by rounding off the measured values of forward voltage Vf (V) to the third decimal place. Table 2 shows the relationship among the number of n-side conductive parts, relative output [a.u.], and forward voltage Vf (V) for Examples 1 to 7 and Comparative Example. Further, FIG. 15 shows a graph showing the relationship between the number of n-side conductive parts and the relative output. In FIG. 15, the vertical axis is the relative output, and the horizontal axis is the number of n-side conducting parts. Further, FIG. 16 shows a graph showing the relationship between the number of n-side conductive parts and the forward voltage Vf. In FIG. 16, the vertical axis represents the forward voltage Vf, and the horizontal axis represents the number of n-side conductive parts. In FIGS. 15 and 16, the results of Examples 1 to 7 are shown by black circles, and the results of Comparative Examples are shown by open circles.

According to the graph in FIG. 15 and the results in Table 2, higher relative outputs were obtained in the semiconductor light emitting devices 1A to 1G of Examples 1 to 7 than in the semiconductor light emitting device 100 of the comparative example. Furthermore, in Examples 1 to 7, the greater the number of n-side conducting portions 41d, the higher the relative output was obtained. It was confirmed that even when the number of n-side conductive parts 41d increases and the area of the light emitting layer 12 decreases, a high relative output can be obtained. By arranging a large number of n-side conductive portions 41d in the same first region R1, a portion where the n-side wiring portion 42 and the n-side contact electrode 41 are electrically connected and a portion where the p-side electrode 50 It is presumed that this is because the distance between the p-pad electrode 70 and the part to which it is electrically connected has become smaller.

According to the graph in FIG. 16 and the results in Table 2, in Examples 1 to 7, the larger the number of n-side conductive parts 41d, the lower the forward voltage Vf was obtained. In Examples 1 to 5, a forward voltage Vf equal to or lower than that of the semiconductor light emitting device 100 of the comparative example was obtained.

From the above results, the distance between the part where the n-side wiring part 42 and the n-side contact electrode 41 are electrically connected and the part where the p-side electrode 50 and the p-pad electrode 70 are electrically connected It was confirmed that a semiconductor light emitting device having a high relative output and a low forward voltage Vf can be obtained by reducing the Vf.

<<Description of the second demonstration test>>
A second demonstration test was conducted on the semiconductor light emitting device of the present disclosure. In the second demonstration test, semiconductor light emitting devices of Examples 1 to 4 and Examples 8 to 9 shown below were manufactured.

Note that Examples 1 to 4 and Examples 8 to 9, which are the targets of the second verification test, differ in the thickness of the semiconductor structure 10 and the electrodes, which are the targets of the first verification test. Note that the semiconductor light emitting devices of Examples 1 to 4 and Examples 8 to 9, which are the targets of the second verification test, had substantially the same structure as the first verification test, except for the configuration described below. This will be explained in detail below.

The semiconductor structure 10 is a p-type semiconductor including an n-type semiconductor layer including an AlGaN layer with an Al composition ratio of 60%, an AlGaN layer with an Al composition ratio of 40%, and a GaN layer disposed on the AlGaN layer. A nitride semiconductor with laminated layers was used. As the n-side wiring part 42 of the n-side electrode 40, a stacked structure in which a 1.6 nm thick Ti layer, a 500 nm thick Ru layer, and a 10 nm thick Ti layer were stacked in this order was used. As the p-side electrode 50, a laminated structure was used in which a Ru layer with a thickness of 340 nm, a Ni layer with a thickness of 9 nm, and an Au layer with a thickness of 7 nm were laminated in this order.

The number of n-side conductive parts, the area of the n-side contact electrode (μm ² ), and the area of the light-emitting layer (μm ² ) of the semiconductor light-emitting devices of Examples 1 to 4, which are the targets of the second demonstration test, are as described above. This is the same as the semiconductor light emitting device of Examples 1 to 4 described in the first demonstration test.

Furthermore, Examples 8 and 9 differ from Examples 1 to 4 mainly in the number of n-side conductive portions 41d and the number of third openings h3. For example, in the eighth embodiment, the distance between the n-side conductive part 41d and the third opening h3 of the first embodiment shown in FIG. A large number of 84 openings h3 are arranged. Similarly, in Example 9, the distance between the n-side conductive part 41d and the third opening h3 of Example 1 shown in FIG. 27 more openings h3 are arranged. Therefore, in Examples 8 and 9, the total area of the n-side contact electrode 41 is increased and the total area of the light emitting layer 12 is decreased compared to Examples 1 to 7.

In Example 8, the number of n-side conductive parts 41d was 216, and the number of first openings h1 for arranging the n-side conductive parts 41d was 216. Further, in Example 8, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was set to 229. The diameter of the third opening h3 in Example 8 is 6 μm. In Example 9, the number of n-side conductive parts 41d was 185, and the number of first openings h1 for arranging the n-side conductive parts 41d was 185. Further, in Example 9, the number of second openings h2 and third openings h3 for establishing conduction of the p-side electrode 50 was 172. The diameter of the third opening h3 in Example 9 is 6 μm. Examples 8 and 9 have the area of the n-side contact electrode and the area of the light emitting layer shown in Table 3 below.

Next, for Examples 1 to 4 and 8 to 9, the output (mW) and forward voltage Vf when a forward current of 350 mA was passed through the semiconductor light emitting devices were measured. Table 4 shows the relationship between the number of n-side conductive parts, the output (mW), and the forward voltage Vf (V) for Examples 1 to 4 and 8 to 9. Furthermore, a graph showing the relationship between the number of n-side conductive parts and the output (vertical axis: output (mW), horizontal axis: number of n-side conductive parts) is shown in FIG. ) (vertical axis: forward voltage (V), horizontal axis: number of n-side conducting parts) is shown in FIG.

According to the graph in FIG. 17 and the results in Table 4, the semiconductor light emitting devices of Examples 1 to 4 and 8 to 9 achieved high output. Further, in Examples 1 to 4 and 8 to 9, the greater the number of n-side conductive portions 41d, the higher the output was obtained. Similar to the results of the first demonstration test, it was confirmed in the second demonstration test that high output can be obtained even when the number of n-side conductive parts 41d increases and the area of the light emitting layer 12 becomes small. It was done. This is achieved by arranging a large number of n-side conductive parts 41d in the first region R1 having the same area, so that the n-side wiring part 42 and the n-side contact electrode 41 are electrically connected to each other. It is presumed that the cause is that the distance between the p-side electrode 50 and the part where the p-pad electrode 70 is electrically connected has become smaller.

According to the graph in FIG. 18 and the results in Table 4, in Examples 1 to 4 and 8 to 9, the larger the number of n-side conductive parts 41d, the lower the forward voltage Vf was obtained. From the results of the second demonstration test, it was found that the part where the n-side wiring part 42 and the n-side contact electrode 41 are electrically connected, and the part where the p-side electrode 50 and the p-pad electrode 70 are electrically connected. It was confirmed that a semiconductor light emitting device having high output and low forward voltage Vf can be obtained by reducing the distance between the two.

Note that the embodiments disclosed herein are illustrative in all respects, and are not the basis for a limited interpretation. Therefore, the technical scope of the present disclosure should not be interpreted solely by the embodiments described above, but should be defined based on the claims. Further, the technical scope of the present disclosure includes all changes within the meaning and scope equivalent to the claims.

The present disclosure includes the following embodiments.
[Section 1]
In plan view, an n-side semiconductor layer including a first region, a second region located on the outer periphery of the first region, and a plurality of third regions surrounded by the first region; a semiconductor structure having a light emitting layer disposed on the light emitting layer; and a p-side semiconductor layer disposed on the light emitting layer;
a first insulating film disposed on the semiconductor structure and having a plurality of first openings disposed on the third region and a plurality of second openings disposed on the p-side semiconductor layer; and,
an n-side electrode disposed on the first insulating film and electrically connected to the n-side semiconductor layer through the plurality of first openings;
an n-pad electrode arranged in the second region and electrically connected to the n-side electrode;
a second insulating film disposed on the first insulating film and having a plurality of third openings disposed at positions overlapping with the plurality of second openings;
a p pad electrode disposed on the second insulating film and electrically connected to the p-side semiconductor layer through the plurality of third openings;
In plan view, the p pad electrode covers the first region and the third region,
In a plan view, the plurality of first openings are arranged around the third opening.
[Section 2]
Item 2. The semiconductor light emitting device according to Item 1, wherein the first opening and the third opening are arranged in a staggered manner in a plan view.
[Section 3]
Item 2. The semiconductor light emitting device according to Item 1, wherein the light emitting layer includes an AlGaN layer having an Al composition ratio of 40% or more and 60% or less.
[Section 4]
4. The semiconductor light emitting device according to any one of Items 1 to 3, wherein a plurality of the n-pad electrodes are arranged outside an outer edge of the p-pad electrode in plan view.
[Section 5]
In plan view, the semiconductor structure has a rectangular shape,
5. The semiconductor light emitting device according to any one of Items 1 to 4, wherein the n-pad electrode is disposed in the second region located at a corner of the semiconductor structure in the second region.
[Section 6]
6. The semiconductor light emitting device according to any one of Items 1 to 5, wherein the p pad electrode has an octagonal shape in plan view.
[Section 7]
7. The semiconductor light emitting device according to any one of Items 1 to 6, wherein the area of the p pad electrode is larger than the area of the light emitting layer in plan view.
[Section 8]
8. The semiconductor light emitting device according to any one of Items 1 to 7, wherein a bonding member is disposed on the p pad electrode located above the third opening.
[Section 9]
The n-side electrode includes a plurality of n-side conductive parts and an n-side wiring part,
The n-side conductive portion contacts the n-side semiconductor layer at the first opening,
9. The semiconductor light emitting device according to any one of Items 1 to 8, wherein the n-side wiring portion electrically connects the n-side conductive portion and the n pad electrode.
[Section 10]
The second insulating film includes a fourth opening located between the first opening located closest to the n-pad electrode among the plurality of first openings and the n-pad electrode in plan view. The semiconductor light emitting device according to any one of Items 1 to 9, which has the following.
[Section 11]
The n-side electrode has an n-side outer periphery conductive portion that contacts the n-side semiconductor layer in the second region that does not overlap with the n-pad electrode in plan view;
The n-side outer periphery conductive portion is disposed outside the outer edge of the p pad electrode in plan view,
The second insulating film is located between the first opening, which is located closest to the n-side outer periphery conductive part among the plurality of first openings, and the n-side outer periphery conductive part, in plan view. The semiconductor light emitting device according to any one of Items 1 to 10, having a fifth opening.
[Section 12]
The first insulating film has a sixth opening larger in area than one of the first openings in plan view,
The sixth opening has an elliptical shape in plan view,
12. The semiconductor light emitting device according to item 11, wherein the fifth opening is disposed between the sixth opening and the n-side outer circumferential conduction part in plan view.
[Section 13]
In plan view, the area of the fifth opening is larger than the area of one of the third openings,
13. The semiconductor light emitting device according to item 11 or 12, wherein the fifth opening has an elliptical shape in plan view.

1 Semiconductor light emitting device 10 Semiconductor structure 11 N-side semiconductor layer 12 Light-emitting layer 13 P-side semiconductor layer 14 Substrate 20 First insulating film 30 Second insulating film 40 N-side electrode 41 N-side contact electrode 41p Contact portion 41g N-side outer periphery conduction Part 41d N-side conduction section 42 N-side wiring section 50 P-side electrode 60 N-pad electrode 70 P-pad electrode 80 Bonding member R1 First region R2 Second region R3 Third region h1 First opening h2 Second opening h3 3 openings

Claims (13)

In plan view, an n-side semiconductor layer including a first region, a second region located on the outer periphery of the first region, and a plurality of third regions surrounded by the first region; a semiconductor structure having a light emitting layer disposed on the light emitting layer; and a p-side semiconductor layer disposed on the light emitting layer;
a first insulating film disposed on the semiconductor structure and having a plurality of first openings disposed on the third region and a plurality of second openings disposed on the p-side semiconductor layer; and,
an n-side electrode disposed on the first insulating film and electrically connected to the n-side semiconductor layer through the plurality of first openings;
an n-pad electrode arranged in the second region and electrically connected to the n-side electrode;
a second insulating film disposed on the first insulating film and having a plurality of third openings disposed at positions overlapping with the plurality of second openings;
a p pad electrode disposed on the second insulating film and electrically connected to the p-side semiconductor layer through the plurality of third openings;
In plan view, the p pad electrode covers the first region and the third region,
In a plan view, the plurality of first openings are arranged around the third opening. The semiconductor light emitting device according to claim 1, wherein the first opening and the third opening are arranged in a staggered manner in a plan view. 2. The semiconductor light emitting device according to claim 1, wherein the light emitting layer includes an AlGaN layer having an Al composition ratio of 40% or more and 60% or less. 4. The semiconductor light emitting device according to claim 1, wherein a plurality of the n-pad electrodes are arranged outside an outer edge of the p-pad electrode in plan view. In plan view, the semiconductor structure has a rectangular shape,
4. The semiconductor light emitting device according to claim 1, wherein the n-pad electrode is arranged in the second region located at a corner of the semiconductor structure among the second regions. 4. The semiconductor light emitting device according to claim 1, wherein the p pad electrode has an octagonal shape in plan view. 4. The semiconductor light emitting device according to claim 1, wherein the area of the p pad electrode is larger than the area of the light emitting layer in plan view. 4. The semiconductor light emitting device according to claim 1, wherein a bonding member is disposed on the p pad electrode located above the third opening. The n-side electrode includes a plurality of n-side conductive parts and an n-side wiring part,
The n-side conductive portion contacts the n-side semiconductor layer at the first opening,
4. The semiconductor light emitting device according to claim 1, wherein the n-side wiring section electrically connects the n-side conductive section and the n-pad electrode. The second insulating film includes a fourth opening located between the first opening located closest to the n-pad electrode among the plurality of first openings and the n-pad electrode in plan view. The semiconductor light emitting device according to any one of claims 1 to 3, having the following. The n-side electrode has an n-side outer periphery conductive portion that contacts the n-side semiconductor layer in the second region that does not overlap with the n-pad electrode in plan view;
The n-side outer periphery conductive portion is disposed outside the outer edge of the p pad electrode in plan view,
The second insulating film is located between the first opening, which is located closest to the n-side outer periphery conductive part among the plurality of first openings, and the n-side outer periphery conductive part, in plan view. The semiconductor light emitting device according to claim 1, having a fifth opening. The first insulating film has a sixth opening larger in area than one of the first openings in plan view,
The sixth opening has an elliptical shape in plan view,
12. The semiconductor light emitting device according to claim 11, wherein, in plan view, the fifth opening is disposed between the sixth opening and the n-side outer periphery conductive part. In plan view, the area of the fifth opening is larger than the area of one of the third openings,
The semiconductor light emitting device according to claim 11 or 12, wherein the fifth opening has an elliptical shape in plan view.