JP2023128441A - switching circuit - Google Patents

Abstract

To protect an element provided at a post stage of a switching circuit.SOLUTION: A switching circuit according to an embodiment includes an output MOS transistor, a capacitive element, and a ground circuit. The output MOS transistor is driven based on a drive signal outputted from a gate driver. The capacitive element is connected to the output MOS transistor in parallel. The ground circuit grounds a gate of the output MOS transistor and the capacitive element.SELECTED DRAWING: Figure 1

Description

The present invention relates to technology using output MOS transistors.

2. Description of the Related Art Conventionally, a switching circuit is known that operates using PWM (Pulse Width Modulation) pulses so that the output voltage becomes a desired voltage (for example, see Patent Document 1).

Japanese Patent Application Publication No. 2009-124844

A switching circuit that drives an output MOS transistor to generate an output voltage is provided with a protection circuit that suppresses the generation of an unintended output voltage due to, for example, a steep voltage rise at startup.

However, due to the response delay of the protection circuit and the input voltage application speed, the output voltage increases, and overvoltage is applied to the switching circuit elements (microcomputers, modules, etc.), which may cause the elements to deteriorate.

The present invention has been made in view of the above, and an object of the present invention is to provide a switching circuit that protects elements provided at a subsequent stage.

A switching circuit according to one aspect of the embodiment includes an output MOS transistor, a capacitive element, and a ground circuit. The output MOS transistor is driven based on a drive signal output from the gate driver. The capacitive element is connected in parallel to the output MOS transistor. The grounding circuit grounds the gate of the output MOS transistor and the capacitive element.

According to one aspect of the embodiment, an element provided at a subsequent stage of the switching circuit can be protected.

FIG. 1 is a schematic diagram illustrating a switching circuit according to an embodiment. FIG. 2 is a schematic diagram illustrating a switching circuit according to a comparative example. FIG. 3 is a time chart showing changes in output voltage, etc. in a switching circuit according to a comparative example. FIG. 4 is a time chart showing changes in output voltage, etc. in the switching circuit according to the embodiment.

Hereinafter, switching circuits according to embodiments will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to this embodiment.

A switching circuit 1 according to an embodiment will be described with reference to FIG. 1. FIG. 1 is a schematic diagram illustrating a switching circuit 1 according to an embodiment.

The switching circuit 1 is incorporated into, for example, an engine control ECU (Electronic Control Unit) of a vehicle. The switching circuit 1 is included in a power supply circuit of an engine control ECU. The switching circuit 1 is, for example, a step-down DC/DC converter. The switching circuit 1 converts an input voltage VIN input from a battery (not shown), which is a DC power source, into a desired output voltage VDD. The switching circuit 1 converts the input voltage VIN so as to supply a constant output voltage VDD to an element provided after the switching circuit 1. Elements provided after the switching circuit 1 include a microcomputer and a module. In the following, elements provided at the subsequent stage of the switching circuit 1 will be explained using a microcomputer as an example.

The switching circuit 1 includes an error amplifier 2, a PWM generator 3, a Hi-side driver 4, an output MOS transistor 5, a capacitive element 6, and a grounding circuit 7.

The error amplifier 2 outputs a signal corresponding to the difference between the output voltage VDD output to the microcomputer and a predetermined reference voltage.

The PWM generator 3 generates a PWM signal whose duty changes according to the signal output from the error amplifier 2.

Hi-side driver 4 is a gate driver. The Hi-side driver 4 generates a drive signal that turns on or off the output MOS transistor 5 according to the PWM signal generated by the PWM generator 3. The drive signal generated by the Hi-side driver 4 is input to the gate of the output MOS transistor 5.

Output MOS transistor 5 is a switching element. The output MOS transistor is an N-type MOS transistor. The output MOS transistor 5 operates ON/OFF based on the drive signal generated and output by the Hi-side driver 4, and converts the input voltage VIN so that a constant output voltage VDD is supplied to the microcomputer. do. The output MOS transistor 5 is configured to output an output voltage VDD of, for example, 5V during normal operation. The output MOS transistor 5 turns on when the drive signal is an ON signal greater than or equal to a first predetermined value, and turns off when the drive signal is an OFF signal less than the first predetermined value. The first predetermined value is a preset value.

The drain of output MOS transistor 5 is connected to the input terminal. The source of output MOS transistor 5 is connected to the output terminal. The gate of the output MOS transistor 5 is connected to the Hi-side driver 4. Output MOS transistor 5 has a parasitic capacitance C1 between its source and gate.

Capacitive element 6 is connected in parallel to output MOS transistor 5. The capacitive element 6 is, for example, an N-type MOS transistor like the output MOS transistor 5. Hereinafter, the capacitive element 6 may be referred to as "MOS6". The drain of MOS6 is connected to the input terminal. The source of the MOS 6 is grounded via a resistor 8. The resistor 8 is provided so that, for example, a current that turns on the transistor 7a of the grounding circuit 7 flows through the base of the transistor 7a when the input voltage VIN sharply increases. The resistance value of the resistor 8 is, for example, equal to the impedance at the gate node of the output MOS transistor 5. The gate of MOS6 is connected to the source of MOS6. That is, MOS6 is short-circuited between its gate and source. Like the output MOS transistor 5, the MOS 6 has a parasitic capacitance C2 between its source and gate. For example, the parasitic capacitance C2 of the MOS 6 is equal to the parasitic capacitance C1 of the output MOS transistor 5. Note that "equal" includes completely equal cases and substantially equal cases. The parasitic capacitance C2 includes, for example, a capacitance that produces a similar effect to the parasitic capacitance C1 in the output MOS transistor 5.

Grounding circuit 7 includes a transistor 7a. Transistor 7a is an NPN type transistor. The collector of transistor 7a is connected to the gate of output MOS transistor 5. The base of transistor 7a is connected to MOS6. The base of transistor 7a is connected between capacitive element 6 and resistor 8. The base of transistor 7a is connected to the source of MOS6 and the gate of MOS6. The emitter of transistor 7a is grounded.

For example, in a switching circuit that is a step-down DC/DC converter, a steep rise in the input voltage VIN may occur at startup when voltage application is started from a state where the input voltage VIN is not input. In this case, since the output MOS transistor has a parasitic capacitance between the source and the gate, the gate potential VG increases in response to a steep rise in the input voltage VIN. As a result, the output MOS transistor is turned on, and an unintended high voltage is output to the microcomputer provided at the subsequent stage of the switching circuit, causing an overvoltage to be applied to the microcomputer, which may deteriorate the microcomputer.

On the other hand, the switching circuit 100 according to the comparative example includes a monitor circuit 101, as shown in FIG. FIG. 2 is a schematic diagram illustrating a switching circuit 100 according to a comparative example.

The monitor circuit 101 uses the monitor unit 102 to detect the output voltage VDD to the microcomputer provided at the subsequent stage of the switching circuit 100. Then, when the output voltage VDD is equal to or higher than the second predetermined value, the monitor unit 102 turns on the transistor 103 connected to the gate of the output MOS transistor 5. The second predetermined value is a preset value. The second predetermined value is a value set to suppress overvoltage from being applied to the microcomputer. The second predetermined value is smaller than the output voltage VDD during steady operation. For example, the second predetermined value is 2V. By turning on the transistor 103, the gate potential VG of the output MOS transistor 5 decreases, the output MOS transistor 5 turns off, and the rise in the output voltage VDD is suppressed.

In order to prevent the monitor circuit 101 from operating during the steady operation of the output MOS transistor 5, that is, when there is no steep rise in the input voltage VIN, the monitor circuit 101 is connected to an external An enable signal is input from. This turns off the transistor 103. In the monitor circuit 101, the transistor 103 is turned off by inputting a "Hi" enable signal.

However, in the switching circuit 100 according to the comparative example, when the input voltage VIN rises sharply, the output voltage VDD may rise abnormally due to a response delay in the monitor circuit 101 and the speed at which the input voltage VIN rises. be.

Here, changes in voltage in the switching circuit 100 according to the comparative example will be explained with reference to the time chart of FIG. 3. FIG. 3 is a time chart showing changes in the output voltage VDD, etc. in the switching circuit 100 according to the comparative example. In FIG. 3, the input voltage VIN, the gate potential VG of the output MOS transistor 5, the output voltage VDD, and the state of the transistor 103 are shown.

From a state where the input voltage VIN is zero, application of the input voltage VIN is started at time t0, and the input voltage VIN increases. Since the output MOS transistor 5 has a parasitic capacitance C1 between the source and the gate, the gate potential VG of the output MOS transistor 5 increases when the input voltage VIN is applied.

At time t1, when the gate potential VG of the output MOS transistor 5 becomes equal to or higher than the first predetermined value, the output MOS transistor 5 is turned on. By turning on the output MOS transistor 5, the output voltage VDD increases.

At time t2, when the output voltage VDD detected by the monitor section 102 of the monitor circuit 101 becomes equal to or higher than the second predetermined value, the transistor 103 of the monitor circuit 101 is turned on. As a result, the gate potential VG of the output MOS transistor 5 decreases.

At time t3, when the gate potential VG of the output MOS transistor 5 becomes less than the first predetermined value, the output MOS transistor 5 is turned off. This causes the output voltage VDD to decrease.

At time t4, when the output voltage VDD becomes less than the second predetermined value, the transistor 103 of the monitor circuit 101 is turned off.

In the switching circuit 100 according to the comparative example, the gate potential VG of the output MOS transistor 5 is equal to or higher than the first predetermined value from time t1 to t3, and the output MOS transistor 5 is turned on, so that the output voltage VDD increases. .

When the input voltage VIN rises steeply, the rate of rise of the gate potential VG of the output MOS transistor 5 increases. Further, the rate of increase in the gate potential VG of the output MOS transistor 5 is determined by the characteristics of the RC high-pass filter configured by the parasitic capacitance C1 in the output MOS transistor 5 and the impedance at the node of the gate of the output MOS transistor 5. Therefore, for example, when the variation in the RC component is large, the rate at which the gate potential VG of the output MOS transistor 5 rises becomes large. When the input voltage VIN becomes an unexpectedly large voltage between times t1 and t3, the output voltage VDD also becomes large and an overvoltage is applied to the microcomputer.

Furthermore, the switching circuit 100 according to the comparative example lowers the gate potential VG of the output MOS transistor 5 by turning on the transistor 103. In the switching circuit 100 according to the comparative example, when the sink current of the transistor 103 is low, the rate of decline of the output MOS transistor 5 becomes small after time t2.

In the switching circuit 100 according to the comparative example, the increase in the output voltage VDD cannot be suppressed until the gate potential VG of the output MOS transistor 5 becomes less than the first predetermined value. As described above, the switching circuit 100 according to the comparative example is difficult to suppress the increase in the output voltage VDD caused by external factors such as variations in the elements constituting the switching circuit 100 and the application speed of the input voltage VIN. There is.

Next, changes in voltage in the switching circuit 1 according to the embodiment will be explained with reference to the time chart of FIG. 4. FIG. 4 is a time chart showing changes in the output voltage VDD, etc. in the switching circuit 1 according to the embodiment. FIG. 4 shows the input voltage VIN, the gate potential VG of the output MOS transistor 5, the source potential VS of the MOS 6, the output voltage VDD, and the state of the transistor 7a.

From a state where the input voltage VIN is zero, application of the input voltage VIN is started at time T0, and the input voltage VIN increases. Since the output MOS transistor 5 has a parasitic capacitance C1 between the source and the gate, the gate potential VG of the output MOS transistor 5 increases with the start of application of the input voltage VIN. Furthermore, since the MOS 6 has a parasitic capacitance C2 between the source and the gate, the source potential VS (gate potential) of the MOS 6 increases with the start of application of the input voltage VIN.

At time T1, transistor 7a is turned on. Note that the time T1 corresponds to the response delay time of the transistor 7a. When the transistor 7a is turned on, the gate of the output MOS transistor 5 is grounded, and the gate potential VG of the output MOS transistor 5 is lowered.

The gate potential VG of the output MOS transistor 5 rises for a time corresponding to the response delay of the transistor 7a, but since the response delay of the transistor 7a is short, the gate potential VG of the output MOS transistor 5 is not higher than the first predetermined value at which the output MOS transistor 5 is turned on. No. Therefore, the output MOS transistor 5 is prevented from being turned on due to a steep rise in the input voltage VIN. Therefore, the output voltage VDD is maintained at zero even when the input voltage VIN steeply increases.

At time T2, the gate potential VG of the output MOS transistor 5 becomes zero. Further, at time T3, when the input voltage VIN becomes constant, the voltage at the source of the MOS 6 decreases, and the transistor 7a is turned off.

In the switching circuit 1 according to the embodiment, when the input voltage VIN rises sharply, the source potential VS of the MOS 6 increases as the input voltage VIN rises, and the transistor 7a turns on. Before the gate potential VG of the output MOS transistor 5 rises to a first predetermined value that turns the output MOS transistor 5 ON, the transistor 7a is turned ON. Therefore, in response to a steep rise in the input voltage VIN, the gate potential VG of the output MOS transistor 5 does not exceed the first predetermined value, and the output MOS transistor 5 is prevented from being turned on. Therefore, the output voltage VDD is prevented from rising to an unexpected value.

The switching circuit 1 quickly detects a steep rise in the input voltage VIN because the transistor 7a is turned on in response to the source potential VS of the MOS 6 which rises in accordance with the steep rise in the input voltage VIN. Then, the switching circuit 1 turns on the transistor 7a and quickly lowers the gate potential VG of the output MOS transistor 5.

The switching circuit 1 includes an output MOS transistor 5, a capacitive element 6, and a grounding circuit 7. The output MOS transistor 5 is driven based on a drive signal output from the Hi-side driver 4. Capacitive element 6 is connected in parallel to output MOS transistor 5. Grounding circuit 7 grounds the gate of output MOS transistor 5 and capacitive element 6.

Thereby, the switching circuit 1 can lower the gate potential VG of the output MOS transistor 5, for example, without monitoring the rise in the output voltage VDD. Therefore, when the input voltage VIN to the output MOS transistor 5 rises sharply, the switching circuit 1 lowers the gate potential VG of the output MOS transistor 5 before the output MOS transistor 5 is turned on. Then, the switching circuit 1 can prevent the output voltage VDD from increasing. The switching circuit 1 can prevent an overvoltage from being applied to the microcomputer provided at the subsequent stage of the switching circuit 1 due to a sudden rise in the input voltage VIN. That is, the switching circuit 1 can protect the microcomputer provided at the subsequent stage of the switching circuit 1.

The capacitive element 6 is a MOS6. Thereby, the switching circuit 1 can operate the grounding circuit 7 by, for example, the MOS 6 having a parasitic capacitance C2 corresponding to the parasitic capacitance C1 in the output MOS transistor 5 when the input voltage VIN rises sharply. The switching circuit 1 can quickly activate the grounding circuit 7 to quickly lower the gate potential VG of the output MOS transistor 5 in response to a steep rise in the input voltage VIN. Therefore, the switching circuit 1 can prevent the output MOS transistor 5 from turning on when the input voltage VIN increases sharply, and can prevent the output voltage VDD from increasing.

The gate and source of MOS6 are connected. As a result, when the switching circuit 1 is in steady operation, that is, when the input voltage VIN is kept at a constant voltage, the grounding circuit 7 is kept OFF. Therefore, the switching circuit 1 can keep the grounding circuit 7 OFF during steady operation without inputting an enable signal from the outside to turn the grounding circuit 7 OFF.

Grounding circuit 7 includes a transistor 7a. The collector of transistor 7a is connected to the gate of output MOS transistor 5. The base of transistor 7a is connected to MOS6. The emitter of transistor 7a is grounded.

As a result, when the input voltage VIN rises sharply, the switching circuit 1 can quickly turn on the transistor 7a in response to the rise in the input voltage VIN, thereby suppressing the rise in the gate potential VG of the output MOS transistor 5. It can be prevented. The switching circuit 1 can prevent the output voltage VDD from increasing by lowering the gate potential VG of the output MOS transistor 5 before the output MOS transistor 5 is turned on. The switching circuit 1 can prevent an overvoltage from being applied to the microcomputer provided at the subsequent stage of the switching circuit 1 due to a sudden rise in the input voltage VIN.

The parasitic capacitance C2 of the MOS 6 is equal to the parasitic capacitance C1 between the drain of the output MOS transistor 5 and the gate of the output MOS transistor 5.

Thereby, when the input voltage VIN rises sharply, the switching circuit 1 can turn on the transistor 7a in accordance with the source potential VS of the MOS 6, which rises in accordance with the rise in the gate potential VG of the output MOS transistor 5. can. Therefore, the switching circuit 1 can quickly operate the transistor 7a and quickly lower the gate potential VG of the output MOS transistor 5 in response to a steep rise in the input voltage VIN. Therefore, the switching circuit 1 can prevent the output MOS transistor 5 from turning on when the input voltage VIN increases sharply, and can prevent the output voltage VDD from increasing.

Note that in the switching circuit 1, the types of the MOS 6 and the transistor 7a may be set based on the amplification factor of the transistor 7a, the impedance at the gate node of the output MOS transistor 5, and the like. The MOS 6 and the transistor 7a only need to be able to lower the gate potential VG of the output MOS transistor 5 before the output MOS transistor 5 is turned on when the input voltage VIN rises steeply. That is, the MOS 6 and the transistor 7a only need to be able to keep the output MOS transistor 5 OFF when the input voltage VIN sharply increases.

In the switching circuit 1 according to the modification, the capacitive element 6 may be a capacitor. The capacitance of the capacitor is, for example, equal to the parasitic capacitance C1 of the output MOS transistor 5. Thereby, when the input voltage VIN rises sharply, the transistor 7a can be turned on in accordance with the gate potential VG of the output MOS transistor 5. The switching circuit 1 can quickly turn on the transistor 7a and quickly lower the gate potential VG of the output MOS transistor 5 in response to a steep rise in the input voltage VIN. Therefore, the switching circuit 1 can prevent the output MOS transistor 5 from turning on when the input voltage VIN increases sharply, and can prevent the output voltage VDD from increasing.

The capacitor only needs to be able to turn on the transistor 7a and lower the gate potential VG of the output MOS transistor 5 so that the output MOS transistor 5 does not turn on when the input voltage VIN sharply increases. The capacitance of the capacitor may be smaller than the parasitic capacitance C1 of the output MOS transistor 5.

In the switching circuit 1 according to the modification, the grounding circuit 7 may be a current mirror circuit. In the current mirror circuit, the value obtained by multiplying the parasitic capacitance C2 of the MOS 6 by the mirror ratio is smaller than the parasitic capacitance C1 of the output MOS transistor 5. Thereby, when the input voltage VIN sharply increases, the switching circuit 1 can turn on the transistor 7a, suppress the increase in the gate potential VG of the output MOS transistor 5, and prevent the output voltage VDD from increasing. .

The switching circuit 1 described above is not limited to a step-down DC/DC converter. The switching circuit 1 may be applied to an IPD (Intelligent Power Device) such as an overcurrent protection circuit.

Further advantages and modifications can be easily deduced by those skilled in the art. Therefore, the broader aspects of the invention are not limited to the specific details and representative embodiments shown and described above. Accordingly, various changes may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.

1 Switching circuit 4 Hi-side driver (gate driver)
5 Output MOS transistor 6 Capacitive element 7 Ground circuit 7a Transistor C1 Parasitic capacitance C2 Parasitic capacitance

Claims (8)

an output MOS transistor driven based on a drive signal output from the gate driver;
a capacitive element connected in parallel to the output MOS transistor;
A switching circuit comprising: a gate of the output MOS transistor; and a grounding circuit that grounds the capacitive element. The switching circuit according to claim 1, wherein the capacitive element is a MOS transistor. 3. The switching circuit according to claim 2, wherein the MOS transistor has a gate and a source connected. The switching circuit according to claim 1, wherein the capacitive element is a capacitor. the grounding circuit includes a transistor;
a collector of the transistor is connected to a gate of the output MOS transistor;
a base of the transistor is connected to the capacitive element;
The switching circuit according to any one of claims 1 to 4, wherein the emitter of the transistor is grounded. 6. The switching circuit according to claim 1, wherein the capacitance of the capacitive element is equal to the parasitic capacitance between the drain of the output MOS transistor and the gate of the output MOS transistor. The switching circuit according to claim 1, wherein the ground circuit is a current mirror circuit. A value obtained by multiplying the capacitance of the capacitive element by the mirror ratio of the current mirror circuit is smaller than a parasitic capacitance formed between the drain of the output MOS transistor and the gate of the output MOS transistor. The switching circuit according to claim 7.

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