JP2013255002A - Undervoltage lockout circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an undervoltage lockout circuit that reduces current consumption and reduces chip area.SOLUTION: The UVLO circuit comprises: a startup circuit 3 that has a voltage dividing resistance circuit 2 including first and second resistances R1, R2 for generating a divided voltage Vx, and diodes D1, D2, D3 connected in series between the voltage dividing resistance circuit 2 and a ground so as to allow a forward current to flow from an input power supply 1 to the ground, and that outputs a starting current Is; a reference voltage generation circuit 4 started by the starting current Is to generate a reference voltage Vref; a MOS transistor M1 turned on in response to the reference voltage Vref to short-circuit both ends of the diodes D1, D2, D3 and thus ground a third resistance R3; and a comparator 5 for outputting a UVLO signal if the divided voltage Vx is lower than the reference voltage Vref.

Description

  The present invention relates to an undervoltage lockout circuit for preventing malfunction of an internal circuit when an input voltage is low.

  2. Description of the Related Art Conventionally, in a switching power supply circuit such as a DC-DC converter, the switching power supply circuit is kept in a standby state until the voltage of the input power supply reaches a predetermined voltage when the power is turned on by an under voltage lockout circuit. Thus, the switching power supply circuit is prevented from malfunctioning and the consumption current is reduced. In the following description, the low voltage lockout circuit is abbreviated as a UVLO circuit.

  FIG. 3 is a circuit diagram of a conventional UVLO circuit. The UVLO circuit includes a resistance voltage dividing circuit 2 connected to an input power supply 1 (DC power supply), a startup circuit 3, a band gap type reference voltage generation circuit 4, and a comparator 5.

  The resistance voltage dividing circuit 2 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series between the input power source 1 and the ground, and the first resistor R1 and the second resistor R3. A divided voltage Vx is output from a connection point with the resistor R2. The resistance voltage dividing circuit 2 further includes an N-channel MOS transistor M2 connected to both ends of the third resistor R3 for adjusting the divided voltage Vx.

  The MOS transistor M2 conducts in response to an undervoltage lockout signal (hereinafter abbreviated as UVLO signal) from the comparator 5, and grounds one end of the second resistor R2. The third resistor R3 and the MOS transistor M2 are connected in parallel between the second resistor R2 and the ground. The resistance value of this parallel circuit is that the MOS transistor M2 is turned off when the MOS transistor M2 is conductive. It is lower than the case.

  The start-up circuit 3 is a circuit that outputs a start-up current Is to the reference voltage generation circuit 4 when the power is turned on, and has a current limiting resistor R4 having one end connected to the input power supply 1 and a forward direction from the input power supply 1 to the ground. The three diodes D1, D2, D3 connected in series between the other end of the current limiting resistor R4 and the ground, and the reference voltage generating circuit 4 so that a current flows, and the reference voltage generating circuit 4, the starting current Is (forward current) ) Is output. The resistance value of the current limiting resistor R4 is several MΩ.

  The comparator 5 compares the divided voltage Vx output from the resistance voltage dividing circuit 2 with the reference voltage Vref output from the reference voltage generating circuit 4, and when the divided voltage Vx is lower than the reference voltage Vref, the UVLO signal ( H level signal). The comparator 5 operates using the input power supply 1 as a power supply. The divided voltage Vx is input to the negative input terminal (−), and the reference voltage Vref is input to the positive input terminal (+).

  The switching power supply circuit 6 is, for example, a chopper type DC-DC converter including a switching element and a choke coil, and a circuit that steps down or boosts a voltage Vcc (DC voltage) from the input power supply 1 by a switching operation of the switching element. It is. The switching element of the switching power supply circuit 6 is turned off in response to the UVLO signal, and the switching power supply circuit stops operating.

  The operation of such a UVLO circuit will be described. First, when the power is turned on, the voltage Vcc of the input power supply 1 rises from 0V. When the voltage Vcc becomes higher than 3 × VF (about 1.8 V), forward current flows to the diodes D1, D2, and D3 through the current limiting resistor R4. VF is a forward bias voltage of the diodes D1, D2, and D3, and is about 0.6V.

  Then, the starting current Is is supplied to the reference voltage generation circuit 4 through the output diode D4. As a result, the reference voltage generation circuit 4 is activated, and the reference voltage generation circuit 4 outputs the reference voltage Vref (about 1.2 V). At this time, the resistance values of the first resistor R1 and the second resistor R2 are set so that the divided voltage Vx is lower than the reference voltage Vref. Therefore, the output of the comparator 5 is at the H level, and the UVLO signal is being output.

  The MOS transistor M2 is turned on in response to the UVLO signal from the comparator 5. As a result, one end of the second resistor R2 is grounded through the MOS transistor M2. In this case, the divided voltage Vx is expressed by the following equation.

Vx = Vcc × R2 / (R1 + R2) (1)
Here, R1 is the resistance value of the first resistor R1, R2 is the resistance value of the second resistor R2, and the on-resistance of the MOS transistor M2 is negligibly small with respect to the resistance value of the resistor R3.

  When the voltage Vcc further rises and the divided voltage Vx becomes higher than the reference voltage Vref, the output of the comparator 5 changes from H level to L level. Thereby, the operation stop state of the switching power supply circuit 6 is released. When the value of the voltage Vcc at this change is Vcc1, Vcc1 is expressed by the following equation.

Vcc1 = Vref × (R1 + R2) / R2 (2)
The MOS transistor M2 is turned off when the output of the comparator 5 becomes L level. As a result, the divided voltage Vx changes to a value represented by the following equation.

Vx = Vcc × (R2 + R3) / (R1 + R2 + R3) (3)
After that, when the voltage Vcc is lowered due to power reduction of the input power supply 1 and the divided voltage Vx becomes lower than the reference voltage Vref, the output of the comparator 5 changes from L level to H level. When the value of the voltage Vcc at this change is Vcc2, Vcc2 is expressed by the following equation.

Vcc2 = Vref × (R1 + R2 + 3) / (R2 + R3) (2)
From simple calculations, Vcc2 <Vcc1. That is, the comparator 5 has a hysteresis characteristic as shown in FIG.

  Thus, when the voltage Vcc rises and exceeds Vcc1, the output of the comparator 5 changes from the H level to the L level, and the operation stop state of the switching power supply circuit 6 is released. Thereafter, when the voltage Vcc decreases and becomes lower than Vcc2, the UVLO signal is output from the comparator 5, and the switching power supply circuit 6 stops its operation in response to this. The UVLO circuit is described in Patent Document 1.

JP 2009-94888 A

  In the conventional UVLO circuit, the resistance voltage dividing circuit 2 and the startup circuit 3 are separated. For this reason, the resistance voltage dividing circuit 2 has a problem that current always flows from the input power supply 1 to the ground through the first to third resistors R1 to R3, and current consumption is large. Further, the first to third resistors R1 to R3 of the resistance voltage dividing circuit 2 and the current limiting resistor R4 of the start-up circuit 3 are provided separately, and these resistors have high resistance values, so that the chip area is large. There was also the problem of getting bigger.

  Accordingly, an object of the present invention is to provide a UVLO circuit with a small current consumption and a small chip area.

  The undervoltage lockout circuit of the present invention is connected to an input power supply, and includes a voltage dividing resistor circuit including first and second resistors for generating a divided voltage, and a forward current flows from the input power supply to the ground. A plurality of diodes connected in series between the voltage-dividing resistor circuit and the ground, and a start-up circuit that outputs a start-up current when the input power is turned on, and a reference that is started by the start-up current and generates a reference voltage A voltage generating circuit; a first switching element that conducts according to the reference voltage; and grounds the voltage dividing resistor circuit by short-circuiting both ends of the plurality of diodes; and the divided voltage and the reference voltage. And a comparator that outputs an undervoltage lockout signal when the divided voltage is lower than the reference voltage.

  According to the low voltage lockout circuit of the present invention, since the voltage dividing resistor of the resistance voltage dividing circuit and the current limiting resistor of the start-up circuit are shared, the current consumption can be reduced and the chip area can be reduced.

It is a circuit diagram of a UVLO circuit in an embodiment of the present invention. It is a circuit diagram of a band gap type reference voltage generating circuit. It is a circuit diagram of the UVLO circuit of a prior art example. It is an operating characteristic figure of the UVLO circuit of a prior art example.

  FIG. 1 is a circuit diagram of a UVLO circuit in an embodiment of the present invention. The UVLO circuit includes a start-up circuit 3 including a resistance voltage dividing circuit 2 connected to an input power supply 1 (DC power supply), an N-channel MOS transistor M1 for grounding the resistance voltage dividing circuit 2 (“first” of the present invention Switching element ”), a band gap type reference voltage generation circuit 4, and a comparator 5.

  This UVLO circuit shares the voltage dividing resistors (first to third resistors R1 to R3) of the resistance voltage dividing circuit 2 and the current limiting resistor (R4 of the conventional example) of the startup circuit 3.

  The resistance voltage dividing circuit 2 includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series to the input power supply 1. The resistance voltage dividing circuit 2 further includes an N-channel MOS transistor M2 (the “second switching element” of the present invention) connected to both ends of the third resistor R3 and for adjusting the divided voltage Vx. . A divided voltage Vx is output from a connection point between the first resistor R1 and the second resistor R2. The MOS transistor M2 becomes conductive in response to the UVLO signal from the comparator 5, and short-circuits both ends of the second resistor R3.

  The start-up circuit 3 includes three diodes D1, D2, D3 connected in series between the resistance voltage dividing circuit 2 and the ground, and a reference voltage generation so that a forward current flows from the resistance voltage dividing circuit 2 to the ground. An output diode D4 that outputs a starting current Is (forward current) to the circuit 4; The anode of the output diode D4 is connected to the connection point between the third resistor R3 and the anode of the diode D1.

  In the MOS transistor M1, the source and drain are connected to both ends of the series diodes D1, D2, and D3, respectively, and the reference voltage Vref from the reference voltage generation circuit 4 is applied to the gate. The MOS transistor M1 conducts according to the reference voltage Vref (about 1.2 V), and shorts both ends of the series diodes D1, D2, and D3 to ground the third resistor R3 of the voltage dividing resistor circuit 2.

  As shown in FIG. 2, the reference voltage generation circuit 4 includes P-channel type MOS transistors M3, M4, and M5, NPN-type bipolar transistors T1, T2, and T3, and resistors R5 and R6.

  The voltage Vcc from the input power supply 1 is applied to the sources of the MOS transistors M3, M4, and M5. The bipolar transistor T1 is connected between the drain of the MOS transistor M3 and the ground, and the base and the collector are commonly connected. The bipolar transistor T2 is connected between the drain of the MOS transistor M4 and the ground via a resistor R5. The bipolar transistors T1, T2 form a current mirror. The bipolar transistor T3 is connected between the drain of the MOS transistor M5 and the ground via a resistor R6. The MOS transistors M3 and M4 form a current mirror, and the MOS transistors M4 and M5 form a current mirror.

  The reference voltage Vref is output from the connection point between the drain of the MOS transistor SM5 and the resistor R6. The cathode of the output diode D4 is connected to a connection point (collector of T1) between the MOS transistor M3 and the bipolar transistor T1.

  Next, the operation of the UVLO circuit will be described. First, when the power is turned on, the voltage Vcc of the input power supply 1 rises from 0V. When the voltage Vcc is lower than 3 × VF, no current flows through the first to third resistors R1 to R3 and the diodes D1, D2, and D3, so that power consumption is reduced accordingly.

  When the voltage Vcc becomes higher than 3 × VF (about 1.8 V), forward current flows through the diodes D1, D2, and D3 through the first to third resistors R1 to R3. VF is a forward bias voltage of the diodes D1, D2, and D3, and is about 0.6V. In this case, since the series resistance value of the first to third resistors R1 to R3 is a high resistance value of several MΩ, the potential of the anode of the diode D1 is clamped to 3 × VF.

  When a forward current flows through the diodes D1, D2, and D3 through the first to third resistors R1 to R3, the starting current Is flows through the output diode D4 to the bipolar transistor T1 of the reference voltage generation circuit 4. As a result, the reference voltage generation circuit 4 is activated, and the reference voltage generation circuit 4 outputs the reference voltage Vref (about 1.2 V). In response to the reference voltage Vref, the MOS transistor M1 becomes conductive. The threshold value of the MOS transistor M1 is set lower than the reference voltage Vref.

  When the MOS transistor M1 is turned on, the third resistor R3 of the voltage dividing resistor circuit 2 is grounded. Therefore, the first to third resistors R1 to R3 of the voltage dividing resistor circuit 2 are connected between the voltage Vcc and the ground. Therefore, the operation is performed under the same bias condition as that of the conventional example.

  Therefore, the subsequent operation is the same as the operation of the conventional example. That is, as shown in FIG. 4, when the voltage Vcc rises and exceeds Vcc1, the output of the comparator 5 changes from the H level to the L level, and the operation stop state of the switching power supply circuit 6 is released. After that, when the voltage Vcc decreases and becomes lower than Vcc2, a UVLO signal (H level signal) is output from the comparator 5, and the switching power supply circuit 6 stops its operation accordingly.

  Thus, according to the UVLO circuit of the present embodiment, the voltage dividing resistors (first to third resistors R1 to R3) of the resistor voltage dividing circuit 2 and the current limiting resistor (R4 of the conventional example) of the startup circuit 3 are provided. Since they are shared, the current consumption can be reduced and the chip area can be reduced.

  In the present embodiment, the third resistor R3 and the MOS transistor M2 are provided in order to give the comparator 5 hysteresis characteristics. However, when hysteresis characteristics are not required, the third resistor R3 and MOS transistor are provided. M2 can be deleted.

DESCRIPTION OF SYMBOLS 1 Input power supply 2 Resistance voltage dividing circuit 3 Startup circuit 4 Reference voltage generation circuit 5 Comparator 6 Switching power supply circuit

Claims (3)

A voltage dividing resistor circuit including first and second resistors that are connected to an input power source and generates a divided voltage, and between the voltage dividing resistor circuit and the ground so that a forward current flows from the input power source to the ground. A start-up circuit comprising a plurality of diodes connected in series and outputting a start-up current when the input power is turned on;
A reference voltage generation circuit that is activated by the activation current and generates a reference voltage;
A first switching element that conducts according to the reference voltage and grounds the voltage dividing resistor circuit by short-circuiting both ends of the plurality of diodes;
And a comparator that compares the divided voltage with the reference voltage and outputs a low voltage lockout signal when the divided voltage is lower than the reference voltage.   The voltage dividing resistor circuit is electrically connected to a third resistor connected in series to the second resistor in response to the undervoltage lockout signal, and a second switching circuit that short-circuits both ends of the third resistor. The undervoltage lockout circuit according to claim 1, further comprising an element.   3. The low voltage lockout circuit according to claim 1, wherein the reference voltage generation circuit is a band gap type reference voltage generation circuit.

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