JP2023123109A - package - Google Patents

Abstract

To provide a package capable of suppressing occurrence of crack from a via hole caused by a stress which is generated during manufacture or use of the package.SOLUTION: A ceramic frame part 120 is disposed on a ceramic substrate part 110, in which a substrate wiring part 200 is provided, and encloses a cavity CV. A metallized layer 600 is provided on the ceramic frame part 120. A via electrode 510 connects the metallized layer 600 and the substrate wiring part 200 and is disposed in a via hole VH. The via hole VH includes a frame penetration part VH1, a wiring penetration part VH2 and a protruding part VH3. The frame penetration part VH1 penetrates the ceramic frame part 120 and is filled with the via electrode 510. The wiring penetration part VH2 extends from the frame penetration part VH1, penetrates the substrate wiring part 200 and is filled with the via electrode 510. The protruding part VH3 protrudes from the wiring penetration part into the ceramic substrate part 110.SELECTED DRAWING: Figure 11

Description

TECHNICAL FIELD The present invention relates to a package, and more particularly to a package provided with a cavity for hermetically sealing an electronic component by attaching a lid.

A package for a crystal oscillator is known as a ceramic component manufactured using a ceramic green sheet. A typical crystal oscillator has a crystal blank, a package having a cavity in which the crystal blank is housed, and a lid for sealing the cavity. The package has a substrate forming the bottom surface of the cavity, a frame surrounding the cavity, and a metallized layer provided on the frame. A lid is bonded to the metallized layer using a bonding material (typically a brazing material).

During the use of packaged modules, such as crystal oscillators as described above, the potential of the metallization layer often needs to be properly controlled for purposes such as noise prevention, typically ground potential It is said that For this purpose, the metallization layer is electrically shorted, for example, to an electrode pad for ground potential. An electrical path for this purpose is typically secured through a via electrode penetrating the frame. Specifically, the wiring portion electrically connected to the electrode pad for ground potential and the metallized layer are connected to each other by via electrodes embedded in the frame portion.

However, with the progress of miniaturization of packages, the material width of the frame (the dimension between the inner wall surface and the outer wall surface of the frame) is becoming smaller. is becoming more difficult. Specifically, it has become difficult to form fine via holes for arranging fine via electrodes in a green sheet that becomes a frame portion when fired.

When a pin-shaped mold is used as a typical method for forming a via hole, if the pin shape is made finer to make the via hole finer, the mechanical strength of the pin tends to be insufficient. Therefore, in mold processing, as via holes become finer, it becomes more difficult to ensure processing efficiency in mass production.

Therefore, for example, according to the technique disclosed in Japanese Patent Laying-Open No. 2007-27592 (Patent Document 1), a castellation electrode having a substantially crescent shape is provided on the inner wall surface of the frame instead of the via electrode. It is However, when the castellation electrodes are provided on the side wall of the cavity instead of the via electrodes as in the technique of the above-mentioned publication, the brazing material is introduced into the cavity to the castellation electrodes in the step of joining the lid using the brazing material. Easy to flow along. Contact between the flowed braze material and the crystal blank can adversely affect the performance of the crystal unit. Adverse effects on mechanical properties due to the inflow of the brazing material are of particular concern when the element mounted in the package is a crystal blank, but it can occur not only in crystal blanks but also in the case of other piezoelectric elements. . Furthermore, not only piezoelectric elements but also other electronic components may be adversely affected by electrical characteristics such as unintended short circuits.

On the other hand, Japanese Patent Application Laid-Open No. 2009-234074 (Patent Document 2) discloses a method of forming minute through holes as via holes in a ceramic green sheet by laser processing technology. Specifically, a through-hole having a diameter of 30 μm to 50 μm is formed in a ceramic green sheet having a thickness of 250 μm or less using an ultraviolet laser. By using such laser processing in place of the metal mold processing described above, it is possible to ensure the processing efficiency of via holes in mass production of small packages.

JP 2007-27592 A JP 2009-234074 A

By using laser processing as described above, through holes (via holes) can be formed with sufficient processing efficiency. However, according to the studies of the present inventors, as described above, the smaller the material width of the frame along with the progress of miniaturization of the package, the more the stress generated during the manufacture or use of the package will cause the via hole to become more difficult. There is a great concern that cracks will occur from the

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and an object of the present invention is to suppress the occurrence of cracks in via holes due to stress generated during package manufacture or use. to provide a package that can

A package according to one aspect is provided with a cavity for hermetically sealing an electronic component by attaching a lid. The package includes a ceramic substrate portion, a substrate wiring portion, a ceramic frame portion, a metallized layer, and via electrodes. The substrate wiring portion is provided on the ceramic substrate portion. The ceramic frame portion has a first surface and a second surface opposite to the first surface and disposed on the ceramic substrate portion provided with the substrate wiring portion, and surrounds the cavity. The metallized layer is provided on the first surface of the ceramic frame. The via electrode connects the metallized layer and the substrate wiring portion to each other, and is arranged in the via hole. The via hole has a frame penetrating portion, a wire penetrating portion, and a projecting portion. The frame penetrating portion penetrates the ceramic frame portion and is filled with the via electrode. The wiring through portion extends from the frame through portion and penetrates the substrate wiring portion, and is filled with the via electrode. The protruding portion protrudes into the ceramic substrate portion from the wiring through portion.

According to the above aspect, the via hole has the projecting portion projecting into the ceramic substrate portion. Accordingly, the via electrode arranged in the via hole does not have a bottom surface on the substrate wiring portion, and thus does not have a corner portion on the substrate wiring portion. Therefore, there is a difference in sintering shrinkage between the via electrode and the ceramic substrate during the firing process for manufacturing the package, and a difference in sintering shrinkage between the via electrode and the ceramic substrate during use of the package. A phenomenon in which stress is concentrated on the corner due to at least one of the difference in coefficient of thermal expansion is avoided. Therefore, it is possible to prevent cracks from occurring due to stress concentration.

The protrusion of the via hole may be tapered. In this case, the stress in the vicinity of the protrusion can be suppressed.

The projecting portion of the via hole may be a blind hole provided in the ceramic substrate portion. Thereby, the depth of the via hole can be suppressed. Therefore, it is possible to suppress deterioration of the mechanical strength of the ceramic substrate due to the via holes.

The ceramic frame may have a minimum width of 200 μm or less. Cracks are particularly likely to occur when the ceramic frame has such fine dimensions. According to the above aspect, the occurrence of such cracks can be prevented.

The via electrode has a diameter of 50 μm or less. Such fine via electrodes allow the width of the ceramic frame to be fine. Cracks are particularly likely to occur when the ceramic frame has such fine dimensions. According to the above aspect, the occurrence of such cracks can be prevented.

The package may further include electrode pads on which the crystal blank as the electronic component is to be mounted. Packages in which crystal blanks are mounted often have fine design dimensions. In that case, cracks are particularly likely to occur. According to the above aspect, the occurrence of such cracks can be prevented.

The protrusion of the via hole may be at least partially filled with the via electrode. As a result, the wiring penetrating portion, which is a portion of the via hole located shallower than the projecting portion, is more reliably filled with the via electrode. Therefore, the via electrode can be electrically connected to the substrate wiring portion more reliably.

The protrusion of the via hole may be partially filled with the via electrode such that the protrusion has a void. This void allows stress to be more relaxed.

The via electrode may have a bottom surface in contact with the projecting portion of the via hole, and the bottom surface of the via electrode may be a convex curved surface. In this case, the bottom surface of the via electrode does not have an angular portion. This avoids stress concentration on such angular portions. Therefore, the occurrence of cracks due to the stress concentration can be avoided.

Objects, features, aspects and advantages of the present invention will become more apparent with the following detailed description and accompanying drawings.

FIG. 2 is a plan view schematically showing the configuration of the crystal resonator in Embodiment 1; 2 is a schematic cross-sectional view along line II-II of FIG. 1; FIG. FIG. 2 is a plan view schematically showing one step of a method for manufacturing the crystal oscillator of FIG. 1; Figure 4 is a schematic cross-sectional view along line IV-IV of Figure 3; 2 is a plan view schematically showing the configuration of the package in Embodiment 1; FIG. Figure 6 is a schematic cross-sectional view along line VI-VI of Figure 5; FIG. 6 is a plan view omitting illustration of the metallized layer, the ceramic frame portion, and the via electrode in FIG. 5 ; 8 is a plan view schematically showing the substrate portion and substrate via electrodes in FIG. 7, with package electrode pads indicated by dashed lines; FIG. FIG. 6 is a plan view omitting illustration of a metallized layer on the ceramic frame in FIG. 5 ; FIG. 6 is a schematic partial cross-sectional view along line XX of FIG. 5; FIG. 11 is a partially enlarged view of FIG. 10; FIG. 2 is a flow diagram schematically showing a method of manufacturing a package according to Embodiment 1; FIG. 4 is a plan view schematically showing one step of the method of manufacturing the package in Embodiment 1; FIG. 14 is a plan view schematically showing the substrate portion and substrate via electrodes in FIG. 13 , with package electrode pads indicated by broken lines; Figure 15 is a schematic partial cross-sectional view along line XV-XV of Figures 13 and 14; FIG. 4 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package in Embodiment 1; FIG. 4 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package in Embodiment 1; FIG. 4 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package in Embodiment 1; FIG. 4 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package in Embodiment 1; FIG. 4 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package in Embodiment 1; FIG. 4 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package in Embodiment 1; FIG. 4 is a partial cross-sectional view showing the structure of a package in a first comparative example; FIG. 23 is a partially enlarged view of FIG. 22; FIG. 10 is a partial cross-sectional view showing one step of a method of manufacturing a package in the first comparative example; FIG. 10 is a partial cross-sectional view showing one step of a method of manufacturing a package in the first comparative example; FIG. 10 is a partial cross-sectional view showing one step of a method of manufacturing a package in the first comparative example; FIG. 10 is a partial cross-sectional view showing one step of a method of manufacturing a package in the first comparative example; FIG. 10 is a partial cross-sectional view showing one step of a method of manufacturing a package in the first comparative example; FIG. 11 is a partial cross-sectional view showing one step of a method of manufacturing a package in a second comparative example; 21 is a micrograph showing an example of the process shown in FIG. 20; 12 is a partial cross-sectional view schematically showing the configuration of the package in Embodiment 2 from a view corresponding to FIG. 11; FIG.

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below based on the drawings.

<Embodiment 1>
FIG. 1 is a plan view schematically showing the configuration of a crystal oscillator 900 as a module according to the first embodiment. FIG. 2 is a schematic cross-sectional view along line II-II of FIG. FIG. 3 is a plan view schematically showing the configuration immediately after the crystal blank 890 (electronic component) is mounted in the manufacturing method of the crystal oscillator 900 (FIG. 1). FIG. 4 is a schematic cross-sectional view along line IV-IV of FIG.

A crystal oscillator 900 has a package 701 , a crystal blank 890 , a brazing material 960 and a lid body 980 . The package 701 is provided with a cavity CV for hermetically sealing a crystal blank 890 (electronic component) by attaching a lid 980 . A crystal blank 890 is housed in the cavity CV and mounted on the device electrode pads 211 and 212 of the package 701 . The lid 980 is joined to the metallized layer 600 of the package 701 with a brazing material 960, thereby sealing the cavity CV. Brazing material 960 is typically preferably made of an alloy containing gold, for example, an alloy containing gold and tin, in other words, an Au—Sn alloy. Lid 980 is made of metal, for example, an alloy containing iron and nickel. In this specification, an alloy is regarded as one type of metal.

Metallized layer 600 is made of, for example, metal containing at least one of molybdenum and tungsten. The surface of the metallized layer 600 (the surface facing the brazing material 960) may be provided with a plating layer, typically a gold plating layer. Also, a nickel plating layer may be provided as a base for the gold plating layer. The metallized layer 600 provided directly on the frame upper surface SF1 of the ceramic frame portion 120 of the package 701 and the lid body 980 may be joined only by the brazing material 960 .

FIG. 5 is a plan view schematically showing the configuration of package 701. As shown in FIG. FIG. 6 is a schematic cross-sectional view along line VI-VI of FIG. Package 701 includes ceramic portion 100, device electrode pads 211, device electrode pads 212, and package electrode pads 301-304.

The ceramic part 100 is made of ceramic, preferably containing oxide as a main component, more preferably containing alumina as a main component, for example substantially made of alumina. The ceramic portion 100 includes a ceramic substrate portion 110 and a ceramic frame portion 120 surrounding the cavity CV on the ceramic substrate portion 110 . The material of the ceramic substrate portion 110 and the material of the ceramic frame portion 120 may be the same. The ceramic frame portion 120 is laminated on the ceramic substrate portion 110 in the thickness direction (vertical direction in FIG. 6). Thereby, the ceramic frame portion 120 is arranged on the ceramic substrate portion 110 and surrounds the cavity CV. The ceramic frame portion 120 has a frame upper surface SF1 (first surface) and a frame lower surface SF2 (second surface opposite to the first surface in the thickness direction). The ceramic frame portion 120 also has an inner wall surface that connects the upper frame surface SF1 and the lower frame surface SF2, and the inner wall surface is the side wall of the cavity CV. The ceramic substrate portion 110 has a substrate upper surface SF3 (third surface). The substrate top surface SF3 has a support surface portion SF3S that supports the frame bottom surface SF2 of the ceramic frame portion 120, and a cavity surface portion SF3C that faces the cavity CV. Cavity surface portion SF3C forms the bottom surface of cavity CV.

The package 701 also has a metallization layer 600 on the frame top surface SF1 of the ceramic frame 120 to which the lid 980 (FIGS. 1 and 2) will be bonded. The package 701 also includes a structure for electrical wiring provided in the ceramic part 100, as described below.

Device electrode pads 211 and device electrode pads 212 (FIG. 5) are arranged on the ceramic portion 100 (FIG. 6) facing the cavity CV. Specifically, the element electrode pad 211 and the element electrode pad 212 are arranged on the cavity surface portion SF3C of the substrate top surface SF3 of the ceramic substrate portion 110 (FIG. 6). A crystal blank 890 (FIGS. 3 and 4) as an electronic component is mounted on the element electrode pads 211 and 212. FIG. Package electrode pads 301-304 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) outside the cavity CV. Specifically, the package electrode pads 301 to 304 are arranged on the lower surface (surface opposite to the substrate upper surface SF3) of the ceramic substrate portion 110 (FIG. 6).

The relay electrode 220 (FIG. 5) is provided on the substrate upper surface SF3 of the ceramic substrate portion 110 (FIG. 6). The relay electrode 220 is arranged at least partially on the support surface portion SF3S (FIG. 6). Thus, the relay electrode 220 (FIG. 5) is at least partially covered by the ceramic frame 120. As shown in FIG. The relay electrode 220 may further have a portion that is not covered by the ceramic frame 120 and is located on the bottom surface of the cavity CV. In other words, the relay electrode 220 may be only partially covered with the ceramic frame 120 .

FIG. 7 is a plan view in which illustration of the metallized layer 600, the ceramic frame 120 and the via electrodes 510 (see FIG. 9) in FIG. 5 is omitted. FIG. 8 is a plan view schematically showing the ceramic substrate portion 110 and the substrate via electrodes 411 to 414 in FIG. 7, with the package electrode pads 301 to 304 indicated by broken lines.

Wiring layers 401 to 403 are embedded in the vicinity of the upper surface of the ceramic substrate portion 110 of the ceramic portion 100 . The wiring layer 401 is in contact with the element electrode pad 211 , the wiring layer 402 is in contact with the element electrode pad 212 , and the wiring layer 403 is in contact with the relay electrode 220 . The wiring layers 401 to 403 may be covered with an insulating film 110i (see FIG. 10) as part of the ceramic substrate portion 110 to the extent that these contacts are not hindered. The gap is insulated by the insulating film 110i. The wiring layer 403 and the relay electrode 220 constitute the substrate wiring section 200 . The substrate wiring portion 200 is part of the package 701 and is provided on the ceramic substrate portion 110 . The thickness of the substrate wiring portion 200 is, for example, 5 μm or more and 20 μm or less.

The package 701 has substrate via electrodes 411 - 414 embedded in the ceramic substrate portion 110 . A substrate via electrode 411 connects the wiring layer 402 and the package electrode pad 301 to each other. A substrate via electrode 412 connects the wiring layer 403 and the package electrode pad 302 to each other. A substrate via electrode 413 connects the wiring layer 401 and the package electrode pad 303 to each other. A substrate via electrode 414 connects the wiring layer 403 and the package electrode pad 304 to each other.

From the above configuration, the element electrode pad 211 is electrically connected to the package electrode pad 303, the element electrode pad 212 is electrically connected to the package electrode pad 301, and the relay electrode 220 is connected to the package electrode pad 302 and It is electrically connected to the package electrode pad 304 .

FIG. 9 is a plan view in which illustration of the metallization layer 600 in FIG. 5 is omitted. FIG. 10 is a schematic partial cross-sectional view along line XX of each of FIGS. 5 and 7-9. 11 is a partially enlarged view of FIG. 10. FIG.

Referring to FIG. 9, the minimum width of ceramic frame 120, that is, the minimum width between inner wall surface EI (surface facing cavity CV) and outer wall surface EO (surface opposite to inner wall surface EI) of ceramic frame 120 The dimensions may be 200 μm or less, typically 20 μm or more and 110 μm or less.

As described above, the wiring layer 403 and the relay electrode 220 constitute the substrate wiring portion 200 on the substrate upper surface SF3 of the ceramic substrate portion 110. As shown in FIG. Moreover, as described above, the ceramic substrate portion 110 has the insulating film 110i (FIG. 10) as a part thereof. A frame lower surface SF2 (FIG. 10) of the ceramic frame portion 120 is arranged on the ceramic substrate portion 110 on which the substrate wiring portion 200 is provided.

As a modification, the insulating film 110i may be omitted depending on the design of the package. Also, the substrate wiring portion 200 may be configured by only one of the wiring layer 403 and the relay electrode 220 . For example, the substrate wiring section 200 may have the wiring layer 403 while the relay electrode 220 is omitted. ) may be shifted to the end position of the relay electrode 220 on the support surface portion SF3S (the right end position of the relay electrode 220 in FIG. 10), and the relay electrode 220 may be omitted. Also, the edge of the insulating film 110i facing the cavity CV may be deformed to reach the ceramic frame 120, in which case the substrate wiring portion 200 may be separated from the cavity CV by the insulating film 110i. Further, the substrate wiring portion 200 typically extends over the support surface portion SF3S and the cavity surface portion SF3C as shown in FIG. 10, but as a modification, it is arranged only on the support surface portion SF3S. It's okay. In the present embodiment, the substrate wiring portion 200 has an end away from the outer edge of the frame lower surface SF2 of the ceramic frame portion 120 (the right end of the frame lower surface SF2 in FIG. 10). may have reached

The package 701 has via electrodes 510 . The via electrode 510 has an end surface SFA on the frame top surface SF1 and a bottom surface SFB on the opposite side of the end surface SFA. The shape of the end surface SFA of the via electrode 510 may be substantially circular, and the approximate circle of the shape may have a diameter of 10 μm or more and 50 μm or less. The thickness of the via electrode 510 (dimension in the vertical direction in FIG. 10) is, for example, 50 μm or more and 250 μm or less.

As shown in FIG. 10, the via electrode 510 penetrates the ceramic frame portion 120 between the frame top surface SF1 and the frame bottom surface SF2 and reaches the substrate wiring portion 200. More specifically, the substrate wiring It reaches the relay electrode 220 of the portion 200 . Thus, the via electrode 510 connects the metallized layer 600 and the substrate wiring portion 200 to each other. The via electrode 510 electrically short-circuits the metallized layer 600 to the substrate wiring portion 200 . As described above, the relay electrode 220 is in contact with the wiring layer 403, and the substrate via electrode 412 and the substrate via electrode 414 are connected to the wiring layer 403 (FIG. 7). Thus, substrate via electrode 412 and substrate via electrode 414 are electrically connected to via electrode 510 . Furthermore, the end surface SFA of the via electrode 510 is in contact with the metallization layer 600 . Thus, referring to FIG. 8, metallization layer 600 is electrically connected to package electrode pads 302 and package electrode pads 304 through substrate via electrodes 412 and substrate via electrodes 414, respectively. Therefore, by setting the potentials of the package electrode pads 302 and 304 to the reference potential, the potential of the metallized layer 600 can also be set to the reference potential. The reference potential is typically ground potential.

The via electrode 510 is arranged in the via hole VH (FIG. 11) so as to penetrate the ceramic frame portion 120 and reach the substrate wiring portion 200 as described above. The thickness (longitudinal dimension in FIG. 11) of the via hole VH is, for example, 50 μm or more and 250 μm or less.

The via hole VH, as shown in FIG. 11, has a frame through portion VH1, a wire through portion VH2, and a projecting portion VH3. The frame through portion VH1 penetrates the ceramic frame portion 120 and is filled with the via electrode 510 . The wiring through portion VH2 extends from the frame through portion VH1 and penetrates the substrate wiring portion 200, and is filled with the via electrode 510. As shown in FIG. The protruding portion VH3 protrudes into the ceramic substrate portion 110 from the wiring through portion VH2. In the present embodiment, the projecting portion VH3 of the via hole VH is tapered in the projecting direction of the projecting portion VH3 (downward in FIG. 11). The projecting portion VH3 is a blind hole provided in the ceramic substrate portion 110. As shown in FIG. Also, the protrusion VH3 is at least partially filled with the via electrode 510, and substantially the entire protrusion VH3 is filled in the configuration shown in FIG. In this configuration, the via electrode 510 has a bottom surface SFB in contact with the protrusion VH3, and the bottom surface SFB is a convex curved surface.

FIG. 12 is a flow diagram schematically showing the method of manufacturing the package 701 according to the first embodiment. FIG. 13 is a plan view schematically showing one process of manufacturing the package 701 according to Embodiment 1, and FIG. 15 is a schematic partial cross-sectional view along line XV--XV of FIGS. 13 and 14. FIG. 16 to 21 are partial cross-sectional views schematically showing one step of the method of manufacturing the package according to the first embodiment.

13 to 15, in step ST100 (FIG. 12), ceramic substrate portion 110 provided with substrate wiring portion 200 is formed as substrate green body GS. In this specification, the term "green body" means a structure that becomes a ceramic body by firing. The green bodies are typically powder compacts. In order to facilitate powder compaction and handling, the green body may contain, in addition to the main component, a glass component and an organic component as additives. Organic components may include, for example, polyvinyl butyral or acrylic. Although the method for forming the green body is arbitrary, a green sheet as a green body is formed by, for example, a doctor blade method. Additional green bodies may be added onto this greensheet, typically by printing on the greensheet or lamination of other greensheets. The printing is typically done by screen printing. The main component of the green body that becomes the ceramic part 100 by firing may be alumina powder, for example. The main component of the green body that becomes the substrate wiring portion 200 and the via electrode 510 by firing is, for example, tungsten (W) powder, molybdenum (Mo) powder, mixed powder of W powder and Mo powder, or W- Mo alloy powder may be used.

Specifically, first, a green sheet to be the ceramic substrate portion 110 is formed. Via holes are formed in this green sheet by punching, and electrode paste is printed in the via holes, thereby forming green bodies that will become the substrate via electrodes 411 to 414 . Powder of at least one of tungsten and molybdenum, for example, is dispersed in the electrode paste. Subsequently, an electrode paste is printed on this green sheet to form a green body that will become the wiring layers 401 to 403 . Subsequently, a ceramic paste is printed on this green sheet to form a green body that will become the insulating film 110i. Subsequently, an electrode paste is printed on this green sheet to form a green body that will become the element electrode pads 211 and 212 and the relay electrode 220 . After the green bodies to be the substrate via electrodes 411 to 414 are formed as described above, the electrode paste is printed on the green sheets at an arbitrary timing, thereby forming the package electrode pads 301 to 304. A green body is formed.

16 and 17, in step ST200 (FIG. 12), ceramic frame portion 120 is formed as frame-shaped green sheet GF having a frame shape surrounding cavity CV. Specifically, first, as shown in FIG. 16, a green sheet to be the ceramic frame 120 is formed. Cavities CV are then formed by punching, as shown in FIG. The order of steps ST100 and ST200 (FIG. 12) is arbitrary.

Referring to FIG. 18, in step ST300 (FIG. 12), frame-shaped green sheets GF (see FIG. 17) are stacked on substrate green body GS (see FIG. 15).

Referring to FIG. 19 in addition to FIG. 18, in step ST400 (FIG. 12), via hole VH is formed by laser processing. A laser processing system, which is a system for performing laser processing, includes a table that supports a work to be irradiated with laser light, a laser device that irradiates a desired laser light onto the work, and the table and laser device. and a controller for controlling.

The laser system includes a laser oscillator, collimator lens, mask, bent mirror, scan head, table, and camera. The laser oscillator, for example a CO ₂ laser oscillator, generates laser light. The generated laser light is collimated by a collimator lens. The collimated light passes through a mask to form a beam width-tuned laser beam. The direction of travel of the laser beam may be adjusted by a bent mirror as needed. A scan head provided with a laser beam focuses the laser beam to a desired position on a workpiece supported by a table. To control this position, the scan head may have a galvanometer scanner to allow the position where the laser beam is emitted to be adjustable to any position in two dimensions parallel to the table. The scan head may also have a collection lens between the galvo scanner and the workpiece to focus the laser beam.

The control unit may be configured by a general computer having electric circuits. A typical computer includes a central processing unit (i.e. CPU), read only memory (i.e. ROM), random access memory (i.e. RAM), storage, input It has a display unit, a display unit, a communication unit, and a bus line interconnecting them.

In this embodiment, step ST400 includes steps ST411, ST412, and ST421. At step ST411 (FIG. 12), the position of the cavity CV of the frame-shaped green sheet GF is recognized. Specifically, the laser processing system uses its camera to recognize the position of the cavity CV of the frame-shaped green sheet GF. This recognition may be performed using conventional image recognition techniques. In step ST412 (FIG. 12), the position to be laser-processed is determined with reference to the position recognized in step ST411 (FIG. 12). For example, the controller of the laser processing system determines a predetermined relative position from the recognized position as the position to be laser processed. In step ST421 (FIG. 12), a via hole VH (FIG. 19) is formed as shown in FIG. 19 by irradiating laser light. For example, a step of irradiating two pulses of laser light with a wavelength of 9.3 μm or more and 10.7 μm or less from a CO ₂ laser oscillator with an average output of 10 W or more and 250 W or less for an irradiation time of 6 μs is repeated five times.

The via hole VH is formed to penetrate the substrate wiring portion 200 and enter the ceramic substrate portion 110 as shown in FIG. The via hole VH may have a substantially circular shape in a cross section along the upper surface of the substrate wiring portion 200 (the surface facing the frame upper surface SF1), and the approximate circle of the shape is, for example, 10 μm or more and 40 μm or less. have a diameter.

20, in step ST500 (FIG. 12), via electrodes 510 (see FIG. 10) are formed as electrode green bodies G510 in via holes VH (FIG. 19) of frame-shaped green sheet GF. . The electrode green body G510 is a green body that becomes the via electrode 510 (see FIG. 10) by firing. The electrode green bodies G510 may be formed by filling electrode paste into the via holes VH by screen printing.

Referring to FIG. 21, a metallized layer (see FIG. 10) is formed as a metallized green body G600. The metallized green body G600 is a green body that becomes the metallized layer 600 (see FIG. 10) by firing. The metallized green body G600 is formed by applying an electrode paste, and the application is performed, for example, by screen printing.

In step ST600 (FIG. 12), the substrate green body GS, the frame-shaped green sheet GF, the electrode green body G510, and the metallized green body G600 are fired. In addition, if necessary, plating treatment may be performed after firing. A package 701 (FIG. 10) is thus obtained.

In the description with reference to FIGS. 13 to 21, the method of manufacturing one package has been described for the sake of simplification. On the other hand, for efficient mass production, it is impossible to obtain a plurality of packages by dividing the sintered body after forming a sintered body having a configuration in which a plurality of packages are connected to each other in the in-plane direction. , is a well-known technique, which may be applied to the present embodiment. In that case, the outer wall surface SF4 of the package 701 may be formed by a division step after firing.

FIG. 22 is a partial cross-sectional view showing the configuration of a package 711 in the first comparative example, and FIG. 23 is a partially enlarged view of FIG. The via hole VH0 (FIG. 23) of the package 711 has a portion corresponding to the frame penetrating portion VH1 of the via hole VH (FIG. 11). It does not have a portion corresponding to the portion VH3.

24 to 28 are partial cross-sectional views showing one process of manufacturing the package 711 in the first comparative example. First, a frame-shaped green sheet GFc is formed by the steps from FIG. 24 to FIG. Specifically, referring to FIG. 24, via hole VH0 is formed before cavity CV (first embodiment: FIG. 17) is formed. Referring to FIG. 25, via electrode 510 (see FIG. 22) is formed as electrode green body G510 in via hole VH0. Referring to FIG. 26, a metallized layer (see FIG. 22) is formed as a metallized green body G600. Referring to FIG. 27, cavity CV is then formed. At this time, unnecessary portions of the metallized green body G600 are removed. As described above, the frame-shaped green sheet GFc is formed. Referring to FIG. 28, frame-shaped green sheet GFc (FIG. 27) is laminated on substrate green body GS (see FIG. 15). A package 711 (FIG. 22) is obtained by firing this laminate.

In the first comparative example, the first drawback is that when the via hole VH0 is formed (FIG. 24), the cavity CV (FIG. 27) is not yet formed, so the position of the cavity CV (FIG. 27) is cannot be used as a basis. As a result, it is difficult to sufficiently secure the positional accuracy of the via hole VH0 with respect to each of the cavity CV and the board wiring portion 200 . A second disadvantage is that stress tends to concentrate on the corner CN (FIG. 23) of the via electrode 510 due to the difference in sintering shrinkage between the via electrode 510 and the ceramic substrate portion 110 in the firing process. . Cracks may occur due to this stress concentration.

FIG. 29 is a partial cross-sectional view schematically showing one step of the method of manufacturing the package in the second comparative example. In this comparative example, after the same steps as in the first embodiment are performed up to the step shown in FIG. A via hole VH0 having the shape described in the first comparative example 1 is formed. In this case, the first drawback mentioned above can be resolved, but the second drawback cannot be resolved. Furthermore, as a third drawback, in order to accurately stop the bottom surface SH (FIG. 29) of the via hole VH0 on the substrate wiring portion 200 without penetrating the substrate wiring portion 200 in laser processing, the precision of the laser processing is required. control is required. As a result, manufacturing efficiency is likely to be sacrificed.

FIG. 30 is a micrograph showing a state in which the via hole VH (see FIG. 19) is filled with the electrode green bodies G510 (see FIG. 20) in the example of the manufacturing method of the package 701 according to the first embodiment. In this way, the inventors conducted experiments on the manufacturing method according to the first embodiment. It was confirmed that the manufacturing method was practical.

According to the present embodiment, via hole VH ( FIG. 11 ) has projecting portion VH3 projecting into ceramic substrate portion 110 . As a result, the via electrode 510 arranged in the via hole VH does not have the bottom surface SFB on the substrate wiring portion 200 (see FIG. 11), and therefore has the corner portion CN (FIG. 23) on the substrate wiring portion 200. do not. Therefore, the difference in sintering shrinkage between the via electrodes 510 and the ceramic substrate portion 110 in the firing process for manufacturing the package 701, and the difference between the via electrodes 510 and the ceramic substrate portion 110 during use of the package 701. It is possible to avoid the phenomenon that the stress is concentrated on the corner portion CN due to at least one of the difference in thermal expansion coefficient. Therefore, it is possible to prevent cracks from occurring due to stress concentration.

Furthermore, since the via hole VH (FIG. 11) has the projecting portion VH3 projecting into the ceramic substrate portion 110 as described above, the process of forming the via hole VH (FIG. 11) before the firing process in the manufacture of the package 701 As 19), it is permissible to form the via hole VH so as to penetrate the ceramic frame portion 120 and the substrate wiring portion 200 and protrude into the ceramic substrate portion 110 . Therefore, the via hole VH can be formed with reference to the position of the cavity CV, which is the area surrounded by the ceramic frame 120 . Therefore, the positional accuracy of the via holes VH in the package 701 can be improved.

Specifically, when the via hole VH is formed, the position of the cavity CV is recognized in step ST411 (FIG. 12), and the position thus recognized is used as a reference in step ST412 (FIG. 12). , the position where the laser processing is to be applied is defined. Thereby, the accuracy of the relative position between the cavity CV and the via hole VH can be improved. In addition, since the structure recognized for securing the relative position is the cavity CV, which is a structure having relatively large dimensions, the recognition (typically image recognition) can be easily performed. The accuracy of the relative position between the via hole VH and the substrate wiring portion 200 (see FIG. 7) depends on the cavity CV in the lamination process of the substrate green body GS (FIG. 15) and the frame-shaped green sheet GF (FIG. 17). By ensuring the accuracy of these relative positions by referring to the position and the position of the substrate wiring section 200 (or the position corresponding thereto), the accuracy is usually sufficiently ensured. However, when the accuracy of the relative position between the via hole VH and the substrate wiring portion 200 is particularly required, in addition to recognizing the position of the cavity CV (step ST411), the position of the substrate wiring portion 200 (or the position corresponding thereto) are also recognized, the via hole VH may be laser-processed using both of these positions as references.

Furthermore, when the via hole VH (FIG. 11) has the protruding portion VH3 protruding into the ceramic substrate portion 110 as described above, the bottom surface of the via hole VH can be penetrated through the substrate wiring portion 200 by laser processing. Therefore, there is no need to accurately stop on the substrate wiring portion 200 . This makes it easier to control the laser processing. Therefore, the efficiency of laser processing can be improved.

Protruding portion VH3 of via hole VH may be tapered. In this case, firstly, the stress in the vicinity of the projecting portion VH3 can be suppressed. Second, it is easy to apply laser processing as a method of forming via holes VH.

The projecting portion VH3 of the via hole VH may be a blind hole provided in the ceramic substrate portion 110 . As a result, first, the depth of the via hole VH can be suppressed. Therefore, it is possible to suppress the deterioration of the mechanical strength of the ceramic substrate portion 110 due to the via hole VH.

Ceramic frame 120 may have a minimum width of 200 μm or less. When the ceramic frame 120 has such fine dimensions, firstly, cracks are particularly likely to occur. According to the present embodiment, such cracks can be prevented from occurring. Second, there is a particularly strong need to improve the relative positional accuracy between the ceramic frame 120 and the via hole VH. According to this embodiment, the need can be satisfied.

Via electrode 510 has a diameter of 50 μm or less. Since the via electrodes 510 are thus fine, the width of the ceramic frame 120 is allowed to be fine. When the ceramic frame 120 has such fine dimensions, firstly, cracks are particularly likely to occur. According to the present embodiment, such cracks can be prevented from occurring. Second, there is a particularly strong need to improve the relative positional accuracy between the ceramic frame 120 and the via hole VH. According to this embodiment, the need can be satisfied.

The package 701 may further comprise a metallization layer 600 on the ceramic frame 120 to which the lid 980 will be bonded. The metallized layer 600 is electrically short-circuited to the substrate wiring portion 200 by via electrodes 510 . In this case, the potential of the metallized layer 600 can be controlled to the potential of the substrate wiring section 200 .

The package 701 may further comprise device electrode pads 211, 212 on which a crystal blank 890 as an electronic component 890 will be mounted. The package 701 in which the crystal blank 890 is mounted often has fine design dimensions. In that case, firstly, cracks are particularly likely to occur. According to the present embodiment, such cracks can be prevented from occurring. Second, there is a particularly strong need to improve the positional accuracy of the via holes VH in the package 701 . According to this embodiment, the need can be satisfied.

Projection VH3 of via hole VH may be at least partially filled with via electrode 510 . As a result, the wiring penetrating portion VH2, which is a portion of the via hole VH located shallower than the protruding portion VH3, is filled with the via electrode 510 more reliably. Therefore, the via electrode 510 can be electrically connected to the substrate wiring portion 200 more reliably.

Via electrode 510 may have a bottom surface SFB in contact with projecting portion VH3 of via hole VH, and bottom surface SFB of via electrode 510 may be a convex curved surface. In this case, bottom surface SFB of via electrode 510 does not have an angular portion. This avoids stress concentration on such angular portions. Therefore, the occurrence of cracks due to the stress concentration can be avoided.

<Embodiment 2>
FIG. 31 is a partial cross-sectional view schematically showing the configuration of the package 702 according to the second embodiment from a view corresponding to FIG. 11. As shown in FIG. In the present embodiment, projecting portion VH3 of via hole VH is partially filled with via electrode 510 so that projecting portion VH3 has gap GP. The air gap GP does not reach the wire penetration portion VH2. In other words, the gap GP in the via hole VH is located below the substrate wiring portion 200 in the drawing. Bottom surface SFB of via electrode 510 is separated from ceramic substrate portion 110 via gap GP. The void GP is obtained by incompletely filling the electrode paste for forming the electrode green body G510 (see FIG. 20) into the via hole VH. Since the second embodiment is substantially the same as the first embodiment described above except for these features, the description thereof will not be repeated.

According to the present embodiment, projecting portion VH3 of via hole VH is partially filled with via electrode 510 such that projecting portion VH3 has gap GP. This gap GP can further relax the stress described in the first embodiment.

The first and second embodiments of the present invention and their modifications have been described above. These embodiments and modifications may be freely combined with each other as long as they do not contradict each other.

110: Ceramic substrate portion 110i: Insulating film 120: Ceramic frame portion 200: Substrate wiring portion 211, 212: Element electrode pad 220: Relay electrode 510: Via electrode 600: Metallized layer 701, 702: Package 890: Crystal blank (electronic component )
900: crystal oscillator 980: lid CN: corner CV: cavity GP: void VH: via hole VH1: frame penetration VH2: wiring penetration VH3: protrusion

Claims (9)

A package provided with a cavity for hermetically sealing an electronic component by attaching a lid body,
a ceramic substrate;
a substrate wiring portion provided on the ceramic substrate portion;
a ceramic frame having a first surface and a second surface opposite to the first surface and disposed on the ceramic substrate portion provided with the substrate wiring portion, and surrounding the cavity;
a metallized layer provided on the first surface of the ceramic frame;
a via electrode that connects the metallized layer and the substrate wiring portion to each other and is arranged in a via hole;
with
The via hole is
a frame penetrating portion penetrating the ceramic frame portion and filled with the via electrode;
a wiring penetration portion extending from the frame penetration portion, penetrating the substrate wiring portion, and filled with the via electrode;
a protruding portion protruding from the wiring penetrating portion into the ceramic substrate portion;
have,
package. 2. The package of claim 1, wherein said protrusion of said via hole is tapered. 3. The package of claim 1 or 2, wherein the protrusion of the via hole is a blind hole provided in the ceramic substrate portion. 4. A package according to any preceding claim, wherein the ceramic frame has a minimum width of 200[mu]m or less. 5. The package according to any one of claims 1 to 4, wherein said via electrodes have a diameter of 50 [mu]m or less. The package according to any one of claims 1 to 5, further comprising electrode pads on which the crystal blank as the electronic component is to be mounted. 7. The package of any one of claims 1-6, wherein the protrusion of the via hole is at least partially filled by the via electrode. 8. The package of any one of claims 1 to 7, wherein the protrusion of the via hole is partially filled with the via electrode such that the protrusion has a void. 8. The package according to any one of claims 1 to 7, wherein said via electrode has a bottom surface in contact with said projecting portion of said via hole, and said bottom surface of said via electrode is a convex curved surface.

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