TW202425241A - Package - Google Patents

Abstract

The invention provides a packaging body. The first via electrode (511) extends along a first central axis (AX1), and has a first end surface (SFA) located on a first surface (SF1) of the frame portion (120) and away from the chamber (CV), and a first bottom surface (SFJ) located within the frame portion (120). The second via electrode (512) extends along a second central axis (AX2), and has a second end surface (SFK) electrically connected to the first bottom surface (SFJ) of the first via electrode (511) within the frame section (120), and a second bottom surface (SFB) in contact with the substrate electrode layer (200) at a second surface (SF2) of the frame section (120). In a plan view, a second bottom surface (SFB) of the second via electrode (512) has a minimum dimension (LI) from an inner edge (EI) of a second surface (SF2) of the frame section (120) and a minimum dimension (LO) from an outer edge (EO) of the second surface (SF2) of the frame section (120), and satisfies LO > LI. The first central axis (AX1) is farther from the inner edge (EI) of the frame section (120) than the second central axis (AX2).

Description

Package

The present invention relates to a package, and more particularly to a package having a frame portion formed of ceramic.

As a ceramic component manufactured using a ceramic blank, a package for a crystal oscillator is known. A general crystal oscillator has a crystal blank, a package having a cavity for accommodating the crystal blank, and a cover for sealing the cavity. The package has a substrate portion that serves as the bottom surface of the cavity, a frame portion that surrounds the cavity, and a metallized layer provided on the frame portion. The cover is bonded to the metallized layer using solder. In this way, the airtightness of the cavity is ensured.

The metallization layer on the frame of the package is usually electrically short-circuited with the electrode pad for ground potential. This electrical path can generally be ensured by an interlayer electrode penetrating the frame. However, as the miniaturization of the package progresses, the material width of the frame (the dimension between the inner and outer edges of the frame) also becomes smaller, and the formation of the corresponding fine interlayer electrode becomes difficult. Specifically, it becomes difficult to form fine interlayer holes for fine interlayer electrodes in the green sheet that is formed into the frame by calcination. As a general method for forming a via hole, a mold having a pin shape is used. However, if the pin shape is miniaturized in order to miniaturize the via hole, the mechanical strength of the pin is likely to be insufficient. Therefore, according to the technology disclosed in Japanese Patent Application Laid-Open No. 2007-27592, a battlement-shaped electrode having a crescent shape is provided on the inner wall surface of the frame instead of the via electrode.

When the interlayer electrode is replaced with a crenellated electrode on the side wall of the cavity as in the technique of the above-mentioned publication, the electrode having high wettability to solder is longitudinally cut along the thickness direction of the inner wall of the cavity compared to the frame formed by ceramic. Therefore, in the joining step using solder, the solder easily flows into the cavity along the crenellated electrode. Once the flowing solder contacts the crystal blank, it may cause adverse effects on the mechanical properties of the crystal oscillator. Such adverse effects on mechanical properties are particularly concerned when the component mounted on the package body is a crystal blank, but they may also occur in the case of other piezoelectric components. Furthermore, as long as the components mounted in the package are electrical components, there is a concern about adverse effects on electrical characteristics such as unexpected short circuits. Therefore, it is important to avoid the inflow of solder, and from this point of view, interlayer electrodes are more suitable than battlement-shaped electrodes. Since such a demand also exists for small packages, a technology is desired that can form fine interlayer holes for interlayer electrodes corresponding to the small material width of the frame.

Japanese Patent Publication No. 2009-234074 discloses a method of forming fine through holes, which serve as vias, in a ceramic green sheet by means of laser processing technology. Specifically, through holes with a diameter of 30 μm to 50 μm are formed in a ceramic green sheet with a thickness of less than 250 μm using an ultraviolet laser. In the case of forming through holes with a smaller diameter relative to the thickness by laser processing in this way, it is pointed out that there is a tendency for "the through holes to have a pushed-out shape." In the above-mentioned publication, the pushed-out shape of the through holes is considered to be a problem in that it is difficult to fill the through holes with a conductive glue. Therefore, in the technology of the above-mentioned publication, the laser light irradiation conditions that can make the push-out rate above 60% are examined. Here, the push-out rate is defined by the ratio of the push-out diameter. A push-out rate of 100% means that the through hole has no push-out shape. In addition, a smaller push-out rate means a steeper push-out shape. [Known technical literature] [Patent literature]

Patent document 1: Japanese Patent Publication No. 2007-27592 Patent document 2: Japanese Patent Publication No. 2009-234074

[Problems to be solved by the present invention]

According to the review of the inventors of this case, if the above-mentioned laser processing technology is applied simply for the purpose of setting the interlayer electrode in the frame of the package, it is difficult to fully ensure the airtightness of the cavity. As the miniaturization of the package progresses, the material width of the frame becomes smaller, making this problem more serious. Therefore, from the perspective of ensuring airtightness, the above-mentioned battlement-shaped electrode is more suitable. On the other hand, as mentioned above, if a battlement-shaped electrode is provided, there is a situation where the inflow of solder into the cavity becomes a problem. From the above content, it can be seen that in the known technology, it is difficult to ensure sufficient airtightness of the cavity and prevent the inflow of solder into the cavity.

The present invention is proposed to solve the above-mentioned problem, and its purpose is to provide a package that can ensure sufficient airtightness of the cavity and prevent solder from flowing into the cavity. [Technical means for solving the problem]

Aspect 1 is a package body, which is provided with a cavity; it includes a frame portion formed of ceramic, the frame portion has a first surface, and a second surface opposite to the first surface in the thickness direction; the second surface has an inner edge surrounding the cavity, and an outer edge surrounding the inner edge; the package body further includes a substrate portion formed of ceramic; the substrate portion has a third surface, the third surface is provided with a portion supporting the second surface of the frame portion, and a portion facing the cavity; the package body further includes: a substrate electrode layer, which is provided on the third surface of the substrate portion; a first dielectric electrode, which extends along a first central axis along the thickness direction, has a first end surface located on the first surface of the frame portion and separated from the cavity, and a first end surface The first bottom surface is opposite to the first bottom surface of the frame portion and is located in the opposite direction of the first bottom surface; and the second dielectric electrode extends along the second central axis along the thickness direction, has a second end surface in the frame portion and electrically connected to the first bottom surface of the first dielectric electrode, and a second bottom surface opposite to the second end surface and in contact with the substrate electrode layer on the second surface of the frame portion; when viewed from above, the The second bottom surface of the second dielectric electrode has a minimum dimension LI from the inner edge of the second surface of the frame portion, and a minimum dimension LO from the outer edge of the second surface of the frame portion, satisfying LO＞LI; the first center axis of the first dielectric electrode is farther from the inner edge of the frame portion than the second center axis of the second dielectric electrode.

Aspect 2 is a package body as in aspect 1, wherein the second end surface has a diameter DA, and the second bottom surface has a diameter DB smaller than the diameter DA.

Aspect 3 is a package as in aspect 1 or aspect 2, wherein the second dielectric electrode has a maximum diameter of less than 50 μm.

Aspect 4 is a package body as in any one of aspects 1 to 3, wherein a minimum dimension between the inner edge and the outer edge of the second surface of the frame portion is less than 200 μm.

Aspect 5 is a package body as in any one of aspects 1 to 4, wherein LO≧LI×1.5 is satisfied.

Aspect 6 is a package body as in any one of aspects 1 to 5, wherein the second dielectric electrode has a portion extending from the second end surface in a pushed-out shape in the thickness direction.

Aspect 7 is a package as in aspect 6, wherein the push-pull shape has a push-pull angle of more than 5 degrees.

Aspect 8 is a package body as in any one of aspects 1 to 7, wherein the frame portion has an outer wall surface connecting the first surface and the outer edge of the second surface; the outer wall surface has a calcined surface connected to the first surface and a broken surface connected to the second surface.

Aspect 9 is a package body as in any one of aspects 1 to 8, wherein, in a top view, the second end surface of the second intermediate electrode is separated from the first bottom surface of the first intermediate electrode.

Aspect 10 is a package body as in any one of aspects 1 to 8, wherein, in a top view, the second end surface of the second intermediate electrode at least partially overlaps with the first bottom surface of the first intermediate electrode.

Aspect 11 is a package body as in any one of aspects 1 to 8, wherein, in a plan view, the second end surface of the second intermediate electrode is included in the first bottom surface of the first intermediate electrode.

Aspect 12 is a package body as in any one of aspects 1 to 11, wherein the first dielectric electrode has a portion extending from the first end surface in a pushed-out shape in the thickness direction.

Aspect 13 is a package as in aspect 12, wherein the first dielectric electrode has a larger dimension in the thickness direction than the second dielectric electrode. [Effects of the present invention]

According to aspect 1, first, since the second bottom surface of the second dielectric electrode is arranged in a manner that satisfies LO>LI, the arrangement position of the stacking interface between ceramics can be ensured to a large extent between the outer edge of the second bottom surface of the second dielectric electrode and the outer edge of the second surface of the frame. Here, the stacking interface between ceramics has high airtightness compared to the stacking interface between metal and ceramic. Therefore, the reduction of the airtightness of the cavity caused by leakage along the stacking interface can be suppressed. Second, since the first center axis of the first interlayer electrode is farther from the inner edge of the frame than the second center axis of the second interlayer electrode, even if the second interlayer electrode is located near the cavity, to the extent that the second bottom surface of the second interlayer electrode reaches the cavity, the first end surface of the first interlayer electrode can still be located at a position separated from the cavity. In this way, the side surface of the first interlayer electrode is prevented from being exposed to the cavity near the first end surface of the first interlayer electrode. Therefore, the inflow of solder into the cavity caused by the first interlayer electrode having the first end surface on the first surface of the frame can be prevented. From the above, it is possible to ensure sufficient airtightness of the cavity and prevent solder from flowing into the cavity.

According to aspect 2, the second end surface has a diameter DA, and the second bottom surface has a diameter DB smaller than the diameter DA. Thus, the arrangement position of the stacking interface between ceramics can be ensured to a greater extent between the outer edge of the second bottom surface of the second dielectric electrode and the outer edge of the second surface of the frame. Therefore, the reduction of the airtightness of the cavity due to leakage along the stacking interface can be further suppressed.

According to aspect 3, the second dielectric electrode has a maximum diameter of 50 μm or less. This allows the width of the frame to be miniaturized. As miniaturization progresses, leakage along the laminate interface between the substrate and the frame becomes more likely to become a problem, but these problems can be effectively suppressed for the reasons described above.

According to aspect 4, the minimum dimension between the inner edge and the outer edge of the second surface of the frame is 200 μm or less. As the miniaturization progresses, leakage along the lamination interface between the substrate and the frame becomes more likely to become a problem, but such problems are effectively suppressed for the reasons described above.

According to Aspect 5, LO≧LI×1.5 is satisfied. This can more effectively suppress the reduction in the airtightness of the cavity due to leakage along the lamination interface between the substrate portion and the frame portion.

According to aspect 6, the second dielectric electrode has a portion extending in a pushed-out shape from the second end surface in the thickness direction. Thus, the arrangement position of the stacking interface between ceramics can be ensured to a greater extent between the outer edge of the second bottom surface of the second dielectric electrode and the outer edge of the second surface of the frame portion. Therefore, the reduction in the airtightness of the cavity due to leakage along the stacking interface can be further suppressed.

According to aspect 7, the push-out shape has a push-out angle of 5 degrees or more. Thus, the arrangement position of the stacking interface between ceramics can be ensured to a greater extent between the outer edge of the second bottom surface of the second dielectric electrode and the outer edge of the second surface of the frame. Therefore, the reduction of the airtightness of the cavity due to leakage along the stacking interface can be further suppressed.

According to aspect 8, the frame has an outer wall surface connecting the outer edges of the first and second surfaces; the outer wall surface has a calcined surface connected to the first surface and a fracture surface connected to the second surface. The fracture surface is formed by a fracture step, but due to the influence of the difference in the step, the distance between the outer edge of the second surface of the frame and the bottom surface of the intermediate electrode becomes smaller. However, by satisfying LO>LI as described above, the distance is not easy to become too small. Therefore, the lack of airtightness caused by the distance being too small can be prevented.

According to aspect 9, the second end surface of the second interlayer electrode is separated from the first bottom surface of the first interlayer electrode when viewed from above. Thus, in a design in which the first interlayer electrode is arranged relatively outside and the second interlayer electrode is arranged relatively inside when viewed from above, it becomes easier to make the positional difference between the first interlayer electrode and the second interlayer electrode when viewed from above large. By arranging the first interlayer electrode at a relatively outer side, the inflow of solder into the cavity caused by the first interlayer electrode can be more reliably prevented. By arranging the second interlayer electrode at a relatively inner side, the airtightness of the cavity can be more fully ensured.

According to aspect 10, the second end surface of the second dielectric electrode at least partially overlaps with the first bottom surface of the first dielectric electrode. Thus, the second dielectric electrode can be easily electrically connected to the first dielectric electrode.

According to aspect 11, the second end surface of the second interlayer electrode is included in the first bottom surface of the first interlayer electrode. Thus, in the manufacture of the package, after the first interlayer hole filled with the first interlayer electrode is formed as a non-through hole in the blank, the second interlayer hole filled with the second interlayer electrode can be formed by processing the bottom surface of the non-through hole. Therefore, in the manufacture of the package, it is not necessary to treat the portion where the first interlayer electrode is located and the portion where the second interlayer electrode is located as separate blanks that need to be stacked on each other. Therefore, the stacking step of the manufacture of the package can be simplified.

According to aspect 12, the first dielectric electrode has a portion extending from the first end face in a push-out shape in the thickness direction. Thereby, the distance between the first bottom surface of the first dielectric electrode and the outer wall surface of the frame portion in the imaginary plane between the layer including the first dielectric electrode and the layer including the second dielectric electrode can be ensured to a greater extent. The above-mentioned imaginary plane is equivalent to the stacking interface in the manufacturing method of the package body, so there are situations such as peeling and other poor stacking. Such poor stacking can easily become a path for moisture to invade from the outside of the cavity into the cavity, but by increasing the above-mentioned distance, the invasion of moisture into the cavity can be further suppressed. Thereby, the airtightness of the cavity can be more fully ensured.

Aspect 13 is a package as in aspect 12, wherein the first dielectric electrode has a larger dimension in the thickness direction than the second dielectric electrode. Thus, the distance between the first bottom surface of the first dielectric electrode and the outer wall surface of the frame in the imaginary plane between the layer including the first dielectric electrode and the layer including the second dielectric electrode can be ensured to a greater extent. Therefore, the intrusion of moisture into the cavity can be further suppressed. Thus, the airtightness of the cavity can be more fully ensured.

Hereinafter, the implementation form of the present invention will be described according to the drawings. In addition, in some drawings, an xyz rectangular coordinate system is shown for easy understanding of directions. The z direction of the coordinate system corresponds to the thickness direction described later. In addition, the arrangement in the xy plane of the coordinate system corresponds to the top view described later. In addition, in this specification, when a certain direction is defined, the "pull-out shape" extending along the direction is a shape that gradually narrows toward the direction, for example, a shape whose diameter gradually decreases toward the direction.

<Implementation Form 1> FIG. 1 is a top view schematically showing the structure of the crystal oscillator 900 (electrical component) of the present implementation form 1. FIG. 2 is a schematic cross-sectional view along the line II-II of FIG. 1. FIG. 3 is a top view schematically showing the structure after the crystal blank 890 (electrical component) is installed in the manufacturing method of the crystal oscillator 900 (FIG. 1). FIG. 4 is a schematic cross-sectional view along the line IV-IV of FIG. 3.

The crystal oscillator 900 includes a package 701, a crystal blank 890, a solder 960, and a cover 980. A cavity CV is provided in the package 701. The crystal blank 890 is accommodated in the cavity CV and mounted on the element electrode pad 211 and the element electrode pad 212 of the package 701. The cover 980 is bonded to the metallization layer 600 of the package 701 by the solder 960, thereby sealing the cavity CV. Generally speaking, the solder 960 is preferably formed of an alloy containing gold, for example, an alloy containing gold and tin, in other words, an Au-Sn alloy. The cover 980 is formed of a metal, for example, an alloy containing iron and nickel. In addition, in this specification, alloys are regarded as a type of metal.

The metallization layer 600 is formed of a metal containing at least one of molybdenum and tungsten, for example. A plating layer may be provided on the surface of the metallization layer 600 (the surface facing the solder 960), and generally, a gold plating layer is provided. In addition, a nickel plating layer may be provided as a base of the gold plating layer. In this embodiment, the metallization layer 600 directly provided on the frame top surface SF1 of the frame portion 120 of the package body 701 is bonded to the lid portion 980 only by the solder 960.

FIG5 is a top view schematically showing the structure of the package 701. FIG6 is a schematic cross-sectional view along the line VI-VI of FIG5. The package 701 has a ceramic part 100, a device electrode pad 211, a device electrode pad 212, and package body electrode pads 301 to 304. In addition, the package 701 has a structure for power supply wiring provided in the ceramic part 100, and the details will be described in detail later.

The ceramic part 100 is formed of ceramic, preferably having an oxide as a main component, more preferably having aluminum oxide as a main component, for example, substantially formed of aluminum oxide. The ceramic part 100 includes a substrate part 110 and a frame part 120. The material of the substrate part 110 may be the same as the material of the frame part 120. The frame part 120 is stacked on the substrate part 110 in the thickness direction (z direction of FIG. 6). The frame part 120 has a frame top surface SF1 (first surface) and a frame bottom surface SF2 (a second surface opposite to the first surface in the thickness direction). In addition, the frame part 120 has an inner wall surface connecting the frame top surface SF1 and the frame bottom surface SF2 to each other, and the inner wall surface is a side wall of the cavity CV. The substrate part 110 has a substrate top surface SF3 (third surface). The substrate top surface SF3 includes a support surface portion SF3S that supports the frame bottom surface SF2 of the frame portion 120, and a cavity surface portion SF3C that faces the cavity CV. The cavity surface portion SF3C serves as the bottom surface of the cavity CV.

The element electrode pad 211 and the element electrode pad 212 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) facing the cavity CV. Specifically, the element electrode pad 211 and the element electrode pad 212 are arranged on the top surface (the surface facing the cavity CV) of the substrate part 110 (FIG. 6). The package body electrode pads 301-304 (FIG. 5) are arranged on the ceramic part 100 (FIG. 6) outside the cavity CV. Specifically, the package body electrode pads 301-304 are arranged on the bottom surface (the surface opposite to the surface facing the cavity CV) of the substrate part 110 (FIG. 6).

The relay electrode 220 (FIG. 5) is disposed on the substrate top surface SF3 of the substrate portion 110 (FIG. 6). The relay electrode 220 is at least partially disposed on the support surface portion SF3S (FIG. 6). Therefore, the relay electrode 220 (FIG. 5) is at least partially covered by the frame portion 120. The relay electrode 220 may further have a portion that is not covered by the frame portion 120 and is disposed on the bottom surface of the cavity CV. In other words, the relay electrode 220 may also be only partially covered by the frame portion 120.

Fig. 7 is a top view in which the metallization layer 600 (Fig. 5) and the frame 120 (Fig. 6) are omitted. Fig. 8 is a top view schematically showing the substrate 110 and substrate interlayer electrodes 411-414 of Fig. 7, and showing the package electrode pads 301-304 in dotted lines.

The wiring layers 401 to 403 are embedded in the substrate portion 110 of the ceramic portion 100 near the top surface thereof. The wiring layer 401 contacts the element electrode pad 211, the wiring layer 402 contacts the element electrode pad 212, and the wiring layer 403 contacts the relay electrode 220. The wiring layers 401 to 403 may be covered with an insulating film 110i (see FIG. 11 ) which is a part of the substrate portion 110 within a range that does not hinder the contact therebetween, and in particular, the element electrode pad 211 and the wiring layer 403 are insulated by the insulating film 110i. The wiring layer 403 and the relay electrode 220 form the substrate electrode layer 200 .

The package 701 has substrate dielectric electrodes 411 to 414 embedded in the substrate portion 110 of the ceramic portion 100. The substrate dielectric electrode 411 connects the wiring layer 402 and the package electrode pad 301. The substrate dielectric electrode 412 connects the wiring layer 403 and the package electrode pad 302. The substrate dielectric electrode 413 connects the wiring layer 401 and the package electrode pad 303. The substrate dielectric electrode 414 connects the wiring layer 403 and the package electrode pad 304.

According to the above structure, the device electrode pad 211 is electrically connected to the package electrode pad 303 , the device electrode pad 212 is electrically connected to the package electrode pad 301 , and the relay electrode 220 is electrically connected to the package electrode pad 302 and the package electrode pad 304 .

Fig. 9 is a top view in which the metallization layer 600 of Fig. 5 is omitted. Fig. 10 is a partially enlarged view of Fig. 9. Fig. 11 is a schematic cross-sectional view along the line XI-XI of Fig. 5.

The frame bottom surface SF2 of the frame portion 120 has an inner edge EI surrounding the cavity CV and an outer edge EO surrounding the inner edge EI. The minimum dimension WD between the inner edge EI and the outer edge EO (FIG. 10) can be less than 200 μm, and is generally greater than 20 μm and less than 110 μm. The frame portion 120 has an outer wall surface SF4 connecting the frame top surface SF1 and the outer edge EO of the frame bottom surface SF2. In addition, the frame portion 120 has an inner wall surface (left side of FIG. 11) connecting the frame top surface SF1 and the inner edge EI of the frame bottom surface SF2, and the inner wall surface faces the cavity CV. In this embodiment, the outer wall surface SF4 has a calcined surface SF4A connected to the frame top surface SF1, and a fracture surface SF4B connected to the frame bottom surface SF2. The fracture surface SF4B may also be a surface substantially perpendicular to the frame top surface SF1 (a surface perpendicular to the z direction in FIG. 11 ). The calcined surface SF4A, as shown in FIG. 11 , may also be an angled surface that chamfers the frame top surface SF1 and the fracture surface SF4B. In other words, the normal direction of the calcined surface SF4A may also be different from the normal direction of the frame top surface SF1 and the fracture surface SF4B, and may also be located between them.

As described above, the substrate electrode layer 200 is formed on the substrate top surface SF3 of the substrate portion 110 by the wiring layer 403 and the relay electrode 220. In addition, as described above, the substrate portion 110 has an insulating film 110i (FIG. 11) as a part thereof. As a variation, the insulating film 110i may be omitted according to the design of the package. In addition, the substrate electrode layer 200 may also be formed by only one of the wiring layer 403 and the relay electrode 220. For example, the substrate electrode layer 200 may omit the relay electrode 220 but have the wiring layer 403. In this case, the boundary position between the wiring layer 403 and the insulating film 110i (the right end position of the wiring layer 403 in FIG. 11 ) may be shifted toward the end position of the relay electrode 220 on the support surface portion SF3S (the right end position of the relay electrode 220 in FIG. 11 ), or the relay electrode 220 may be omitted. In addition, the end of the insulating film 110i facing the cavity CV may be deformed to reach the frame portion 120. In this case, the substrate electrode layer 200 may be separated from the cavity CV by the insulating film 110i. In addition, the substrate electrode layer 200 generally spans the support surface portion SF3S and the cavity surface portion SF3C as shown in FIG11 , but as a variation, it may be arranged only on the support surface portion SF3S. In addition, the substrate electrode layer 200, as shown in FIG11 , preferably has an end (the right end in FIG11 ) separated from the outer edge EO of the frame bottom surface SF2 of the frame portion 120. In other words, the end preferably does not reach the outer edge EO. Thereby, the stacking interface of the metal and the ceramic that form the electrode layer 200 does not reach the outer edge EO. As a result, the interface between the metal and the ceramic, which has a lower airtightness than the interface between the ceramics, does not reach the outer edge EO. Therefore, the reduction in airtightness caused by the electrode layer 200 can be suppressed.

The package 701 has a first interlayer electrode 511, a second interlayer electrode 512, and a frame electrode layer 550 as a structure for supplying electric wiring provided in the frame portion 120. The electric wiring penetrates the frame portion 120 between the frame top surface SF1 and the frame bottom surface SF2.

The first interlayer electrode 511 has a first end surface SFA and a first bottom surface SFJ. The first end surface SFA is located on the frame top surface SF1 and is separated from the cavity CV. The first bottom surface SFJ is located in the frame portion 120 in the opposite direction to the first end surface SFA in the thickness direction (z-axis direction). The first interlayer electrode 511 extends along the first center axis AX1 along the thickness direction. Therefore, when viewed from above, the center position of the first end surface SFA is approximately the same as the center position of the first bottom surface SFJ. The diameter of the first bottom surface SFJ may also be smaller than the diameter of the first end surface SFA. The first interlayer electrode 511 may also have a portion extending from the first end surface SFA in a push-out shape in the thickness direction. The height (dimension in the thickness direction) of the first dielectric electrode 511 is, for example, not less than 20 μm and not more than 80 μm.

The second interlayer electrode 512 has a second end surface SFK and a second bottom surface SFB. The second end surface SFK is electrically connected to the first bottom surface SFJ of the first interlayer electrode 511 in the frame portion 120; in this embodiment, it is connected via the frame electrode layer 550. The second bottom surface SFB is opposite to the second end surface SFK in the thickness direction (z-axis direction). The second bottom surface SFB contacts the substrate electrode layer 200 at the frame bottom surface SF2, and contacts the relay electrode 220 in this embodiment. As mentioned above, the relay electrode 220 contacts the wiring layer 403; at the wiring layer 403 (Figure 7), the substrate interlayer electrode 412 and the substrate interlayer electrode 414 are connected. Therefore, the substrate dielectric electrode 412 and the substrate dielectric electrode 414 are electrically connected to the second dielectric electrode 512. Furthermore, the first end surface SFA of the first dielectric electrode 511 contacts the metallization layer 600 (FIG. 6). Therefore, the metallization layer 600 is electrically connected to the package body electrode pad 302 and the package body electrode pad 304 through the substrate dielectric electrode 412 and the substrate dielectric electrode 414, respectively (refer to FIG. 8).

The frame electrode layer 550 should preferably not contact at least one of the outer wall surface SF4 and the inner wall surface of the frame portion 120. The reason is that if the frame electrode layer 550 is in contact with both the outer wall surface SF4 and the inner wall surface, the stacking interface of the metal and the ceramic extending in a manner that makes them connected to each other reduces the airtightness of the cavity CV. The frame electrode layer 550 should preferably not contact the outer wall surface SF4 of the frame portion 120. Thereby, the stacking interface of the metal and the ceramic that becomes the frame electrode layer 550 does not reach the outer wall surface SF4. As a result, the interface of the metal and the ceramic that has lower airtightness than the interface between the ceramics does not reach the outer wall surface SF4. Therefore, the reduction in airtightness caused by the frame electrode layer 550 can be suppressed.

The second end surface SFK has a diameter DA, and the second bottom surface SFB has a diameter DB. The diameter DB is smaller than the diameter DA. The ratio of the diameter DB to the diameter DA may also be greater than 30% and less than 70%. When viewed from above, the second bottom surface SFB of the second dielectric electrode 512 has a minimum dimension LI from the inner edge EI of the frame bottom surface SF2, and a minimum dimension LO from the outer edge EO of the frame bottom surface SF2. The maximum diameter of the second dielectric electrode 512 is smaller than the minimum dimension WD of the frame portion 120, and may also be less than 50μm. In addition, the diameter DA is smaller than the minimum dimension WD of the frame portion 120, and may also be less than 50μm. The second interlayer electrode 512 may also have a portion extending from the second end surface SFK in a push-out shape in the thickness direction. The push-out shape may also have a push-out angle of 5 degrees or more. In the cross-sectional view of FIG. 11 , the push-out angle is the angle between the side surface of the portion of the second interlayer electrode 512 having the push-out shape and the thickness direction (z direction). The second interlayer electrode 512 may also have a push-out shape as a whole. In this case, the push-out ratio (the percentage of the diameter DB relative to the diameter DA) may also be less than 60%. The height (dimension in the thickness direction) of the second interlayer electrode 512 is, for example, not less than 20 μm and not more than 80 μm. The first interlayer electrode 511 may also have a greater height (greater dimension in the thickness direction) than the second interlayer electrode 512. This feature is particularly suitable when the first interlayer electrode 511 has a portion extending from the first end surface SFA in the thickness direction in a pushed-out shape.

The second interlayer electrode 512 extends along the second center axis AX2 along the thickness direction. Therefore, when viewed from above, the center position of the second end surface SFK is approximately the same as the center position of the second bottom surface SFB. The first center axis AX1 of the first interlayer electrode 511 is farther from the inner edge EI of the frame portion 120 than the second center axis AX2 of the second interlayer electrode 512. In this embodiment, when viewed from above, the second end surface SFK of the second interlayer electrode 512 is separated from the first bottom surface SFJ of the first interlayer electrode 511.

In a plan view ( FIG. 10 ), the bottom surface SFB has a minimum dimension LI from the inner edge EI of the frame bottom surface SF2 of the frame portion 120 and a minimum dimension LO from the outer edge EO of the frame bottom surface SF2 of the frame portion 120. LO>LI is satisfied, preferably LO≧LI×1.5 is satisfied.

In the planar layout shown in FIG10 , the shapes of the first end surface SFA, the first bottom surface SFJ, the second end surface SFK, and the second bottom surface SFB are generally circular, but these shapes may be slightly different from the strictly geometrically defined circle due to manufacturing errors. In this case, the diameter DA and the diameter DB can also be calculated by approximating the end surface SFA and the bottom surface SFB with a circular shape.

In addition, in the planar layout shown in FIG10, the inner edge EI of the frame bottom surface SF2 (refer to FIG11) has a first straight line portion (a straight line portion along the x direction in FIG10), a second straight line portion extending in a right angle direction relative to the first straight line portion (a straight line portion along the y direction in FIG10), and a corner portion connecting them. The minimum dimension LI may also be the dimension of the corner portion. The offset direction AS from the second center axis AX2 to the first center axis AX1 when viewed from above, as shown in FIG10, preferably includes both a directional component along the first straight line portion (x direction component) and a directional component along the second straight line portion (y direction component). In this way, the first dielectric electrode 511 can be offset toward the corner portion of the frame portion 120 relative to the second dielectric electrode 512. Therefore, it is easy to ensure the dimension between the second dielectric electrode 512 and the outer wall surface SF4 of the frame portion 120. However, without such considerations, the offset direction AS may include only one of the directional component along the first straight line portion (x-direction component) and the directional component along the second straight line portion (y-direction component).

FIG. 12 to FIG. 27 are figures used to illustrate a manufacturing method for manufacturing a plurality of packages 701 at the same time. In addition, FIG. 12 to FIG. 26 show a state earlier than the calcination step that changes the state of FIG. 26 to the state of FIG. 27. Therefore, each structure in FIG. 12 to FIG. 26 is different from the structure in the completed package 701 and is formed by uncalcined materials. However, for the convenience of explanation, in FIG. 12 to FIG. 26 showing the steps earlier than the calcination step, the same symbols as the symbols representing the structure of the package 701 obtained through the calcination step are still given. In addition, for the sake of convenience, the above-mentioned names of the structures formed by the uncalcined materials may also refer to the names of the structures in the package 701 obtained through the calcination step.

FIG. 12 is a partial top view schematically showing the structure of the substrate blank GS in the above-mentioned manufacturing method. FIG. 13 is a partial top view schematically showing the substrate portion 110 and substrate interlayer electrodes 411 to 414 of the substrate blank GS, and showing the package body electrode pads 301 to 304 in dotted lines. FIG. 14 is a schematic partial cross-sectional view along the line XIV-XIV of FIG. 12 and FIG. 13. The substrate blank GS includes a plurality of regions UN0 to UN4, each of which eventually becomes the substrate portion 110 and the structure near it of the package body 701 (FIG. 6). Regions UN1 to UN4 are all configured to be adjacent to region UN0. In addition, although only a specific structure of the area UN0 is shown in FIG. 12 and FIG. 13 , the areas UN1 to UN4 may also have the same structure.

In addition, in this specification, the term "green body" refers to the uncalcined structure that is calcined in a subsequent step. The green body is generally a powder molded body. In order to facilitate handling, the green body may also contain glass components and organic components as additives in addition to the main component. The organic component may also contain polyvinyl butyral or acrylic acid, for example. The green body is formed by any method, such as by a doctor blade method to form a green sheet that is at least a part of the green body. A green body may be further added to the green sheet, and this addition is generally performed by printing on the green sheet, or by stacking other green sheets. The printing is generally performed by screen printing. The main component of the green body that is formed into the ceramic part 100 (Figure 6) by calcination may be, for example, aluminum oxide powder. The main component of the green body that is formed into the wiring structure such as the first dielectric electrode 511, the second dielectric electrode 512 and the substrate electrode layer 200 (see FIG. 11) by calcination may be, for example, tungsten (W) powder, molybdenum (Mo) powder, a mixed powder of W powder and Mo powder, or W-Mo alloy powder.

In order to obtain the substrate blank GS, first, a blank that will become the substrate portion 110 is formed. For the blank, a via hole is formed by punching, and an electrode glue is printed into the via hole to form a blank that will become the substrate via electrode 411 to 414. In the electrode glue, at least one powder of tungsten and molybdenum is dispersed. Next, the electrode glue is printed on the blank to form a blank that will become the wiring layer 401 to 403. Next, the ceramic glue is printed on the blank to form a blank that will become the insulating film 110i. Next, the green sheet is printed with electrode glue to form a green body of the device electrode pads 211, 212 and the relay electrode 220. In addition, at any time after the green bodies of the substrate interlayer electrodes 411-414 are formed as described above, the green sheet is printed with electrode glue to form a green body of the package body electrode pads 301-304.

Figures 15 to 19 are partial cross-sectional views showing the steps related to the first frame blank GF1 for forming the structure of the portion in the thickness direction where the first dielectric electrode 511 and the metallization layer 600 are arranged in the package 701 (Figure 11). In the figure, the fracture surface BR is shown by a dot chain line, and the fracture step described later is performed along this line.

Referring to FIG. 15 , as the first frame blank GF1, first, a simple blank including a portion of the frame upper portion 120a which is a portion of the frame 120 (the upper portion in FIG. 11 ) is formed. This formation can be performed, for example, by a doctor blade method. The thickness of the frame upper portion 120a constituting the first frame blank GF1 is, for example, not less than 30 μm and not more than 90 μm.

Referring to FIG. 16 , the first via hole VH1 is formed in the frame upper portion 120a by laser processing. The laser light used for laser processing is irradiated in a manner of traveling from the frame top surface SF1 into the frame upper portion 120a. As a result, the first via hole VH1 tends to have a push-pull shape in the direction from the frame top surface SF1 into the frame upper portion 120a. The aperture in the frame top surface SF1 is larger than the aperture in the reverse surface.

Referring further to FIG. 17 , a first via hole VH1 ( FIG. 16 ) of the first frame body GF1 is formed with a first via electrode 511 ( FIG. 17 ). Specifically, the first via hole VH1 is filled with electrode glue by screen printing. The filling is preferably performed from the frame top surface SF1 to the first via hole VH1 .

Referring to FIG. 18 , a metallization layer 600 is formed on the frame top surface SF1. Specifically, electrode glue is applied. In FIG. 18 , electrode glue is applied to the entire frame top surface SF1, but the metallization layer 600 does not need to be applied to the area removed by the step of forming the cavity CV described later. Therefore, a screen printing method that does not apply the glue to at least a portion of the area can also be applied.

Referring to Fig. 19, the cavity CV is formed by stamping. Alternatively, the cavity CV may be formed in the first frame blank GF1 at an earlier time. By the above method, the first frame blank GF1 having a frame shape surrounding the cavity CV is completed.

Figures 20 to 24 are partial cross-sectional views showing the steps related to the second frame blank GF2 for forming the structure of the second dielectric electrode 512 and the frame electrode layer 550 in the thickness direction of the package 701 (Figure 11). In the figure, the fracture surface BR is shown by a dot chain line, and the fracture step described later is performed along this line.

Referring to FIG. 20 , as the second frame blank GF2, first, a simple blank including a portion of the frame lower portion 120b that is a part of the frame 120 (the lower portion in FIG. 11 ) is formed. This formation can be performed, for example, by a scraper method. The thickness of the frame lower portion 120b constituting the second frame blank GF2 is, for example, not less than 30 μm and not more than 90 μm.

Referring to FIG. 21 , the second via hole VH2 is formed in the frame lower portion 120 b by laser processing. The laser light used for laser processing is irradiated in a manner of passing through the frame lower portion 120 b and then passing through the frame bottom surface SF2. As a result, the second via hole VH2 tends to have a push-pull shape in the direction toward the frame bottom surface SF2. The aperture in the frame bottom surface SF2 is smaller than the aperture in the reverse surface.

Referring further to FIG. 22 , a second via hole VH2 ( FIG. 21 ) of the second frame body GF2 is formed with a second via electrode 512 ( FIG. 22 ). Specifically, the second via hole VH2 is filled with electrode glue by screen printing. The filling is preferably performed from the opposite side of the frame bottom surface SF2 to the second via hole VH2.

Referring to FIG. 23 , a frame electrode layer 550 is formed on the surface opposite to the frame bottom surface SF2. Specifically, electrode glue is applied. Screen printing can also be applied to this application.

Referring to Fig. 24, the cavity CV is formed by stamping. Alternatively, the cavity CV may be formed in the second frame blank GF2 at an earlier time. By the above method, the second frame blank GF2 having a frame shape surrounding the cavity CV is completed.

Referring to Fig. 25, the substrate blank GS (Fig. 14), the first frame blank GF1 (Fig. 19), and the second frame blank GF2 (Fig. 24) are stacked to form a blank 700G. The blank 700G includes a plurality of regions 701G, each of which eventually becomes a package 701 (refer to Fig. 11).

Referring to FIG. 26 , a groove TR1 is formed on the frame top surface SF1 of the blank 700G. In addition, a groove TR2 is formed on the surface of the blank 700G opposite to the frame top surface SF1. The groove TR1 and the groove TR2 are arranged to face each other in the thickness direction. The groove TR1 and the groove TR2 are formed, for example, by pressing the tip of a knife against the blank 700G. Thereafter, a calcining step of calcining the blank 700G is performed. In addition, after the calcining step, a coating step may also be performed as necessary.

Referring to FIG. 27 , a calcined sheet 700F is formed by the above-mentioned calcining step. In the calcining step, the inner surface of the groove TR1 is exposed to the calcining ambient gas. Therefore, the inner surface of the groove TR1 of the calcined sheet 700F becomes a calcined surface. The calcined surface becomes the calcined surface SF4A of the package 701 ( FIG. 11 ). By applying stress to the calcined sheet 700F, a fracture step is performed to generate cracks from the groove TR1. A fracture surface is formed by breaking the frame 120 by the fracture step. The fracture surface becomes the fracture surface SF4B of the package 701 ( FIG. 11 ). The breaking step may be a step of generating a crack between the trench TR1 and the trench TR2. Through the breaking step, a plurality of packages 701 are cut out from the calcined sheet 700F. In the above manner, the package 701 is obtained ( FIG. 11 ).

In the above-mentioned breaking step, the crack from the trench TR1, ideally, extends in the thickness direction as shown by the solid arrow in FIG. 27 . However, in practice, as shown by the dotted arrow in FIG. 27 , there is a situation where the crack unexpectedly approaches the second interlayer electrode 512 . As a result, in the package 701 having the second interlayer electrode 512 , the minimum dimension LO ( FIG. 10 ) of the frame bottom surface SF2 of the frame portion 120 becomes smaller. Since an excessively small minimum dimension LO is likely to cause leakage of the package 701 , the minimum dimension LO should have a certain degree of margin. According to the present embodiment, it is easy to ensure such a margin.

FIG. 28 is a partial cross-sectional view schematically showing the structure of the package 791 of the first comparative example in the same view as FIG. 11. The package 791 of the first comparative example has an intermediate electrode 510 instead of the first intermediate electrode 511 and the second intermediate electrode 512 connected to each other by the frame electrode layer 550 in the package 701 (FIG. 1). The intermediate electrode 510 has an end surface SFA and a bottom surface SFB on the frame top surface SF1 and the frame bottom surface SF2 of the frame portion 120, respectively. The intermediate electrode 510 has a push-out shape from the end surface SFA to the bottom surface SFB. In the package 791, from the viewpoint of improving the airtightness of the cavity CV, it is preferable to design the bottom surface SFB as close to the cavity CV as possible. In manufacturing under this design, there is an undeniable probability that a package 792 of the second comparative example shown in FIG. 29 will be manufactured if a manufacturing error occurs, such as the cavity CV and the dielectric electrode 510 being too close to each other.

In the package 792, the end surface SFA of the interlayer electrode 510 reaches the cavity CV. As a result, the side surface of the interlayer electrode 510 is exposed to the cavity CV near the end surface SFA of the interlayer electrode 510. In the step of joining the cover 980 (see FIG. 2) to the package 792, the solder 960 (see FIG. 2) easily flows into the cavity CV as shown by the arrow FL (FIG. 29). Since the inflowing solder contacts the crystal blank 890 (see FIG. 2), there is a situation where the performance of the crystal oscillator 900 (see FIG. 2) is adversely affected. In addition, the adverse effect on mechanical properties caused by the inflow of solder 960 is particularly concerned when the component mounted on the package is a crystal blank 890, but it also occurs in the case of other piezoelectric components. Furthermore, as long as the component mounted on the package is an electrical component, adverse effects on electrical properties such as unexpected short circuits are concerned.

According to the package 701 (FIG. 10 and FIG. 11) of the present embodiment, first, since the second bottom surface SFB of the second interlayer electrode 512 is arranged in a manner satisfying LO>LI (refer to FIG. 10), the arrangement position of the stacking interface between ceramics can be ensured to a large extent between the outer edge of the second bottom surface SFB of the second interlayer electrode 512 and the outer edge EO of the second surface SF2 of the frame portion 120. Here, the stacking interface between ceramics has high airtightness compared to the stacking interface between metal and ceramic. Therefore, the reduction of the airtightness of the cavity CV caused by leakage along the stacking interface can be suppressed. Second, since the first central axis AX1 of the first interlayer electrode 511 is farther from the inner edge EI of the frame portion 120 than the second central axis AX2 of the second interlayer electrode 512, even if the second interlayer electrode 512 is located near the cavity CV, to the extent that the second bottom surface SFB of the second interlayer electrode 512 reaches the cavity CV, the first end surface SFA of the first interlayer electrode 511 can still be located at a position separated from the cavity CV. In this way, the side surface of the first interlayer electrode 511 is prevented from being exposed to the cavity CV near the first end surface SFA of the first interlayer electrode 511. Therefore, it is possible to prevent the solder from flowing into the cavity CV due to the first dielectric electrode 511 having the first end surface SFA on the first surface SF1 of the frame portion 120. As described above, it is possible to ensure sufficient airtightness of the cavity CV and prevent the solder from flowing into the cavity CV.

The diameter DB of the second bottom surface SFB can also be smaller than the diameter DA of the second end surface SFK (see FIG. 10 and FIG. 11). Thus, the arrangement position of the stacking interface between ceramics can be ensured to a greater extent between the outer edge of the second bottom surface SFB of the second dielectric electrode 512 and the outer edge EO of the second surface SF2 of the frame portion 120. Therefore, the reduction in the airtightness of the cavity CV caused by leakage along the stacking interface can be further suppressed.

The maximum diameter of the second dielectric electrode 512 (FIG. 10) can also be made less than 50 μm. This can also miniaturize the width of the frame 120. As the miniaturization progresses, leakage along the stacking interface between the substrate 110 and the frame 120 is more likely to become a problem, but these problems can be effectively suppressed for the reasons described above.

The minimum dimension WD ( FIG. 10 ) between the inner edge EI and the outer edge EO of the second surface SF2 of the frame portion 120 can also be 200 μm or less. As the miniaturization progresses, leakage along the stacking interface between the substrate portion 110 and the frame portion 120 is more likely to become a problem, but such problems can be effectively suppressed for the reasons described above.

It is also possible to satisfy LO≧LI×1.5 (see FIG. 10 ). This can more effectively suppress the reduction in the airtightness of the cavity CV due to leakage along the stacking interface between the substrate portion 110 and the frame portion 120 .

The second dielectric electrode 512 (FIG. 11) may also have a portion extending in a push-out shape from the second end surface SFK in the thickness direction. Thus, between the outer edge of the second bottom surface SFB of the second dielectric electrode 512 and the outer edge EO of the second surface SF2 of the frame portion 120, the arrangement of the stacking interface between ceramics can be ensured to a greater extent. Therefore, the reduction in the airtightness of the cavity CV caused by leakage along the stacking interface can be further suppressed. The push-out shape may also have a push-out angle of more than 5 degrees. Thus, between the outer edge of the second bottom surface SFB of the second dielectric electrode 512 and the outer edge EO of the second surface SF2 of the frame portion 120, the arrangement of the stacking interface between ceramics can be ensured to a greater extent. Therefore, it is possible to further suppress the reduction in the airtightness of the cavity CV due to leakage along the stacking interface.

The outer wall surface SF4 (FIG. 11) of the frame portion 120 has a calcined surface SF4A connected to the frame top surface SF1, and a fracture surface SF4B connected to the frame bottom surface SF2. The fracture surface SF4B is formed by a fracture step (FIG. 27), but due to the influence of the difference in the step, the distance between the outer edge EO of the frame bottom surface SF2 of the frame portion 120 and the second bottom surface SFB of the second dielectric electrode 512 becomes smaller. However, by satisfying LO>LI as described above, the distance is not easy to become too small. Therefore, the lack of airtightness caused by the distance being too small can be prevented.

In the present embodiment, the second end surface SFK of the second interlayer electrode 512 is separated from the first bottom surface SFJ of the first interlayer electrode 511 when viewed from above. Thus, in a design in which the first interlayer electrode 511 is arranged on the outside and the second interlayer electrode 512 is arranged on the inside when viewed from above, it becomes easier to make the positional difference of the first interlayer electrode 511 and the second interlayer electrode 512 when viewed from above large. By arranging the first interlayer electrode 511 on the outside, the inflow of solder into the cavity CV caused by the first interlayer electrode 511 can be more reliably prevented. By disposing the second interlayer electrode 512 at a relatively inner side, the airtightness of the cavity CV can be more fully ensured.

The first interlayer electrode 511 may also have a portion extending in a push-out shape from the first end surface SFA in the thickness direction. Thereby, the distance between the first bottom surface SFJ of the first interlayer electrode 511 and the outer wall surface SF4 of the frame portion 120 in the imaginary plane between the layer including the first interlayer electrode 511 and the layer including the second interlayer electrode 512 can be ensured to a greater extent. The above-mentioned imaginary plane is equivalent to the stacking interface in the manufacturing method of the package body 701, so there are stacking defects such as peeling. Such stacking defects easily become a path for moisture to enter the cavity CV from the outside of the cavity CV, but by increasing the above-mentioned distance, the intrusion of moisture into the cavity CV can be further suppressed. Therefore, the airtightness of the cavity CV can be more fully ensured. This effect can be further enhanced by making the first dielectric electrode 511 larger in the thickness direction than the second dielectric electrode 512 .

<Implementation Form 2> FIG. 30 is a partial top view schematically showing the structure of the package body 702 of the present implementation form 2 in the same view as FIG. 10 . FIG. 31 is a partial cross-sectional view schematically showing the structure of the package body 702 in the same view as FIG. 11 .

In the package 702, unlike the package 701 (FIGS. 10 and 11), when viewed from above, the second end surface SFK of the second interlayer electrode 512 at least partially overlaps with the first bottom surface SFJ of the first interlayer electrode 511. In this embodiment, the second end surface SFK only partially overlaps with the first bottom surface SFJ. The second end surface SFK of the second interlayer electrode 512 directly contacts the first bottom surface SFJ of the first interlayer electrode 511, thereby electrically connecting the second interlayer electrode 512 to the first interlayer electrode 511. In addition, regarding the configurations other than the above, since they are almost the same as the configurations of the above-mentioned embodiment 1, the same symbols are given to the same or corresponding elements, and their descriptions are not repeated.

According to the second embodiment, it is easy to electrically connect the second dielectric electrode 512 to the first dielectric electrode 511. However, as a modification of the second embodiment, a frame electrode layer 550 ( FIG. 11 ) may be provided for the purpose of reducing the connection impedance between the first dielectric electrode 511 and the second dielectric electrode 512.

<Implementation Form 3> FIG. 32 is a partial top view schematically showing the structure of the package body 703 of the present implementation form 3 in the same view as FIG. 10 . FIG. 33 is a partial cross-sectional view schematically showing the structure of the package body 703 in the same view as FIG. 11 .

In the package 703, unlike the package 701 (FIG. 10 and FIG. 11), when viewed from above, the second end surface SFK of the second interlayer electrode 512 is included in the first bottom surface SFJ of the first interlayer electrode 511. The second end surface SFK of the second interlayer electrode 512 is in direct contact with the first bottom surface SFJ of the first interlayer electrode 511, thereby electrically connecting the second interlayer electrode 512 to the first interlayer electrode 511. In addition, since the other structures are almost the same as the structures of the above-mentioned embodiment 1, the same symbols are given to the same or corresponding elements, and their descriptions are not repeated.

34 to 39 are partial cross-sectional views schematically showing one step of the manufacturing method of the package 703. In the present embodiment 3, the first frame blank GF1 (FIG. 15 to 19) and the second frame blank GF2 (FIG. 20 to 24) in the aforementioned embodiment 1 are replaced with a step of forming the frame blank GF. This point will be specifically described below.

Referring to Fig. 34, as the frame blank GF, first, a simple green sheet including a portion to be the frame 120 (Fig. 11) is formed. This formation can also be performed by, for example, a doctor blade method.

Referring to FIG. 35 , a first via hole VH1 as a non-through hole is formed on the frame top surface SF1 of the frame portion 120 by laser processing. The laser light used for laser processing is irradiated in a manner of traveling from the frame top surface SF1 into the frame portion 120. As a result, the first via hole VH1 tends to have a push-out shape in the direction from the frame top surface SF1 into the frame portion 120.

Referring to FIG. 36 , a second via hole VH2 is formed as a through hole extending from the bottom surface of the first via hole VH1 to the frame bottom surface SF2 by laser processing. The laser light used for laser processing is irradiated in a manner of traveling from the bottom surface of the first via hole VH1 to the frame bottom surface SF2. As a result, the second via hole VH2 tends to have a push-out shape in the direction from the bottom surface of the first via hole VH1 to the frame bottom surface SF2.

Further referring to FIG. 37 , the second via hole VH2 and the first via hole VH1 ( FIG. 36 ) of the frame blank GF are respectively formed with the second via hole 512 and the first via hole 511 ( FIG. 37 ). Specifically, the electrode glue is filled into the second via hole VH2 and the first via hole VH1 by screen printing. This filling can also be performed from the frame top surface SF1 into the second via hole VH2 and the first via hole VH1 at the same time.

Referring to FIG. 38 , a metallization layer 600 is formed on the frame top surface SF1. Specifically, electrode glue is applied. In FIG. 38 , electrode glue is applied to the entire frame top surface SF1, but the metallization layer 600 does not need to be applied to the area removed by the step of forming the cavity CV described later. Therefore, a screen printing method that does not apply the glue to at least a portion of the area can also be applied.

Referring to FIG. 39 , a cavity CV is formed by stamping. Alternatively, a cavity CV may be formed on the frame blank GF at an earlier time. In the above manner, a frame blank GF having a frame shape surrounding the cavity CV is completed. By using this frame blank GF instead of the stacked body of the first frame blank GF1 and the second frame blank GF2 in the step of FIG. 25 (embodiment 1), a package 703 ( FIG. 33 ) of this embodiment 3 is obtained.

According to the third embodiment, as shown in FIG32 and FIG33, the second end surface SFK of the second interlayer electrode 512 is included in the first bottom surface SFJ of the first interlayer electrode 511. Thus, in the manufacture of the package 703, after the first interlayer hole VH1 filled with the first interlayer electrode 511 is formed as a non-through hole in the frame blank GF, the second interlayer hole VH2 filled with the second interlayer electrode 512 can be formed by processing the bottom surface of the non-through hole. Therefore, in the manufacture of the package 703, unlike the package 701 (embodiment 1), it is not necessary to treat the portion where the first interlayer electrode 511 is located and the portion where the second interlayer electrode 512 is located as separate blanks that need to be stacked on each other. Therefore, the stacking step of the package manufacturing can be simplified.

100: Ceramic part 110: Substrate part 110i: Insulating film 120: Frame part 120a: Upper part of frame 120b: Lower part of frame 200: Substrate electrode layer 211,212: Component electrode pad 220: Relay electrode 301~304: Package electrode pad 401~403: Wiring layer 411~414: Substrate dielectric electrode 510: Dielectric electrode 511: First dielectric electrode 512: Second dielectric electrode 550: Frame electrode layer 600: Metallization layer 700F: Sintered sheet 700G: blank 701,702,703: package 701G: region 791,792: package 890: crystal blank 900: crystal oscillator (electrical component) 960: solder 980: lid AX1: 1st center axis AX2: 2nd center axis BR: fracture surface CV: cavity DA,DB: diameter EI: inner edge EO: outer edge GF: frame blank GF1: 1st frame blank GF2: 2nd frame blank GS: substrate blank LI: minimum size from the inner edge LO: minimum size from the outer edge SF1: frame top surface (1st surface) SF2: frame bottom surface (2nd surface) SF3: Substrate top surface (3rd surface) SF3C: Cavity surface part SF3S: Support surface part SF4: Outer wall surface SF4A: Calcined surface SF4B: Fracture surface SFA: 1st end surface SFB: 2nd bottom surface SFJ: 1st bottom surface SFK: 2nd end surface TR1, TR2: Groove UN0~UN4: Region VH1: 1st via hole VH2: 2nd via hole WD: Minimum dimension between inner edge and outer edge

FIG. 1 is a top view schematically showing the structure of the crystal oscillator of the embodiment 1. FIG. 2 is a schematic cross-sectional view along the line II-II of FIG. 1. FIG. 3 is a top view schematically showing a step of the manufacturing method of the crystal oscillator of FIG. 1. FIG. 4 is a schematic cross-sectional view along the line IV-IV of FIG. 3. FIG. 5 is a top view schematically showing the structure of the package of the embodiment 1. FIG. 6 is a schematic cross-sectional view along the line VI-VI of FIG. 5. FIG. 7 is a top view in which the metallization layer and the frame of FIG. 5 are omitted. FIG. 8 is a top view schematically showing the substrate and the interlayer electrode of FIG. 7, and showing the package electrode pad in dotted lines. FIG. 9 is a top view in which the metallization layer on the frame of FIG. 5 is omitted. FIG. 10 is a partially enlarged view of FIG. 9 . FIG. 11 is a schematic partial cross-sectional view along line XI-XI of FIG. 5 . FIG. 12 is a partial top view schematically showing the structure of the substrate blank in the method for manufacturing a package body of embodiment 1. FIG. 13 is a partial top view schematically showing the substrate portion and substrate interlayer electrode of the substrate blank shown in FIG. 12 , and showing the package body electrode pad in dotted lines. FIG. 14 is a schematic partial cross-sectional view along line XIV-XIV of FIG. 12 and FIG. 13 . FIG. 15 is a schematic partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 16 is a schematic partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 17 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 18 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 19 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 20 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 21 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 22 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 23 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 24 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 25 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 26 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 27 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 1. FIG. 28 is a partial cross-sectional view schematically showing the structure of the package body of the first comparative example in the same view as FIG. 11. FIG. 29 is a partial cross-sectional view schematically showing the structure of the package body of the second comparative example in the same view as FIG. 11 and FIG. 26, respectively. FIG. 30 is a partial top view schematically showing the structure of the package body of the implementation form 2 in the same view as FIG. 10. FIG. 31 is a partial cross-sectional view schematically showing the structure of the package body of the implementation form 2 in the same view as FIG. 11. FIG. 32 is a partial top view schematically showing the structure of the package body of the implementation form 3 in the same view as FIG. 10. FIG. 33 is a partial cross-sectional view schematically showing the structure of the package body of the implementation form 3 in the same view as FIG. 11. FIG. 34 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package body of the implementation form 3. FIG. 35 is a partial cross-sectional view schematically showing one step of the manufacturing method of the package body of the implementation form 3. FIG. 36 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 3. FIG. 37 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 3. FIG. 38 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 3. FIG. 39 is a partial cross-sectional view schematically showing a step of the method for manufacturing a package body of embodiment 3.

110: Baseboard

110i: Insulation film

120: Frame

200: Substrate electrode layer

220: Relay electrode

302: Package electrode pad

403: Wiring layer

511: 1st dielectric electrode

512: Second dielectric electrode

550: frame electrode layer

600:Metallization layer

701:Package

AX1: 1st center axis

AX2: Second center axis

EI: Internal edge

EO: Outer Edge

SF1: Frame top (1st side)

SF2: Frame bottom (2nd side)

SF3: Substrate top surface (3rd surface)

SF3C: Cavity surface part

SF3S: Support surface part

SF4: Outer wall

SF4A: calcined surface

SF4B: Broken surface

SFA: 1st end face

SFB: 2nd bottom surface

SFJ: 1st bottom surface

SFK: 2nd end face

CV: Cavity

Claims (13)

A package body is provided with a cavity; It includes a frame portion formed of ceramic, the frame portion has a first surface, and a second surface opposite to the first surface in the thickness direction; the second surface has an inner edge surrounding the cavity, and an outer edge surrounding the inner edge; The package body further includes a substrate portion formed of ceramic; the substrate portion has a third surface, the third surface is provided with a portion supporting the second surface of the frame portion, and a portion facing the cavity; The package body further includes: A substrate electrode layer is provided on the third surface of the substrate portion; A first dielectric electrode extends along a first central axis along the thickness direction, has a first end surface located on the first surface of the frame portion and separated from the cavity, and a first bottom surface opposite to the first end surface and located in the frame portion; and The second dielectric electrode extends along the second central axis along the thickness direction, and has a second end face electrically connected to the first bottom face of the first dielectric electrode in the frame, and a second bottom face opposite to the second end face and in contact with the substrate electrode layer on the second face of the frame; When viewed from above, the second bottom face of the second dielectric electrode has a minimum dimension LI from the inner edge of the second face of the frame, and a minimum dimension LO from the outer edge of the second face of the frame, satisfying LO＞LI; The first central axis of the first dielectric electrode is farther from the inner edge of the frame than the second central axis of the second dielectric electrode. A package as claimed in claim 1, wherein the second end surface has a diameter DA, and the second bottom surface has a diameter DB smaller than the diameter DA. A package as claimed in claim 1 or 2, wherein the second dielectric electrode has a maximum diameter of less than 50 μm. A package as claimed in claim 1 or 2, wherein the minimum dimension between the inner edge and the outer edge of the second surface of the frame is less than 200 μm. For the package of claim 1 or 2, LO≧LI×1.5 is satisfied. A package as claimed in claim 1 or 2, wherein the second dielectric electrode has a portion extending from the second end surface in a push-out shape in the thickness direction. A package as claimed in claim 6, wherein the push-pull shape has a push-pull angle of more than 5 degrees. A package as claimed in claim 1 or 2, wherein: the frame portion has an outer wall surface connecting the first surface with the outer edge of the second surface; the outer wall surface has a calcined surface connected to the first surface and a broken surface connected to the second surface. A package as claimed in claim 1 or 2, wherein, when viewed from above, the second end surface of the second interlayer electrode is separated from the first bottom surface of the first interlayer electrode. A package as claimed in claim 1 or 2, wherein, when viewed from above, the second end surface of the second interlayer electrode at least partially overlaps the first bottom surface of the first interlayer electrode. A package as claimed in claim 1 or 2, wherein, when viewed from above, the second end surface of the second interlayer electrode is included in the first bottom surface of the first interlayer electrode. A package as claimed in claim 1 or 2, wherein the first dielectric electrode has a portion extending from the first end surface in a push-out shape in the thickness direction. A package as claimed in claim 12, wherein the first dielectric electrode has a larger dimension in the thickness direction than the second dielectric electrode.

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