JP2023122607A - Semiconductor element and method for manufacturing the same - Google Patents

Abstract

To provide a semiconductor element including a group III nitride semiconductor and operating in a normally-off manner and a method for manufacturing the same.SOLUTION: A third semiconductor layer 130A includes a third semiconductor layer p-type region 132A. A second region R2 surrounds a projection region in which a p-type region in a higher layer than a first semiconductor layer 110 is projected on a first surface Sub1a of a substrate Sub1 by a surface perpendicular to the projection region. A gate electrode G1 is a higher layer than the third semiconductor layer p-type region 132A, and located in a second region R2. A second semiconductor layer 120A includes a first non-dope region 121 in the first region R1, a second non-dope region 122 on the first semiconductor layer 110 side of the second region R2, and a second semiconductor layer p-type region 123A on the third semiconductor layer 130 side of the second region R2. The third semiconductor layer p-type region 132A and the second semiconductor layer p-type region 123A are continuous.SELECTED DRAWING: Figure 9

Description

TECHNICAL FIELD The technical field of the present specification relates to a semiconductor device having a Group III nitride semiconductor and a manufacturing method thereof.

Group III nitride semiconductors have a large bandgap and have been actively researched and developed for application as high-voltage, high-frequency semiconductor devices.

For example, Patent Document 1 discloses a field effect transistor having a polarized superjunction (paragraph [0044] and FIG. 3 of Patent Document 1). This field effect transistor operates normally (paragraph [0091] and FIG. 3 of Patent Document 1). On the other hand, Patent Document 2 discloses a technique of diffusing Mg into a nitride semiconductor substrate by high-pressure, high-temperature annealing (paragraph [0029] of Patent Document 2).

JP 2016-146369 A Japanese Patent Application Laid-Open No. 2020-155468

Patent Document 1 describes that a cascode circuit is introduced to operate a normally-on semiconductor device in a normally-off state (paragraph [0091] of Patent Document 1). However, if another circuit or the like is introduced to operate the semiconductor element normally off, the device mounted with the semiconductor element becomes large or complicated. It is not necessarily easy to realize a group III nitride semiconductor device that operates normally off.

The problem to be solved by the technique of the present specification is to provide a semiconductor device having a Group III nitride semiconductor and operating normally off, and a method for manufacturing the same.

A semiconductor element in a first aspect includes a substrate having a first surface, a first semiconductor layer above the substrate, a second semiconductor layer above the first semiconductor layer, and a third semiconductor above the second semiconductor layer. It has a layer, a gate electrode, and first and second regions. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are Group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer. The third semiconductor layer has a third semiconductor layer p-type region. The second semiconductor layer has a first non-doped region in the first region, a second non-doped region in the second region on the first semiconductor layer side, and a second semiconductor layer in the second region on the third semiconductor layer side. The semiconductor layer has a p-type region. The second region is a region including a projection region obtained by projecting the p-type region above the first semiconductor layer onto the first surface of the substrate on a plane perpendicular to the projection region. The first area is an area other than the second area. The gate electrode is located in the second region above the p-type region of the third semiconductor layer. The third semiconductor layer p-type region and the second semiconductor layer p-type region are continuous at the interface between the third semiconductor layer and the second semiconductor layer.

In this semiconductor element, the film thickness of the second non-doped region in the second region is sufficiently thin, and the second semiconductor layer p-type region is adjacent to the second non-doped region. Therefore, this semiconductor device operates normally off.

The present specification provides a semiconductor device having a group III nitride semiconductor and operating normally off, and a method of manufacturing the same.

1 is a schematic configuration diagram of a semiconductor device 100 according to a first embodiment; FIG. FIG. 4 is a diagram (part 1) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment; FIG. 2 is a diagram (part 2) for explaining the manufacturing method of the semiconductor device 100 of the first embodiment; 3 is a diagram (part 3) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment; FIG. 4 is a diagram (part 4) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment; FIG. FIG. 5 is a diagram (No. 5) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment; FIG. 6 is a diagram (No. 6) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment; FIG. 4 is a schematic configuration diagram of a semiconductor element 200 in a modified example of the first embodiment; It is a schematic block diagram of 100 A of semiconductor elements of 2nd Embodiment. FIG. 11 is a diagram (part 1) for explaining the method of manufacturing the semiconductor device 100A of the second embodiment; FIG. 11 is a diagram (part 2) for explaining the manufacturing method of the semiconductor device 100A of the second embodiment; FIG. 13 is a diagram (part 3) for explaining the manufacturing method of the semiconductor device 100A of the second embodiment; FIG. 14 is a diagram (part 4) for explaining the manufacturing method of the semiconductor device 100A of the second embodiment; FIG. 15 is a diagram (No. 5) for explaining the manufacturing method of the semiconductor device 100A of the second embodiment; It is a schematic block diagram of the semiconductor element 300 in the modification of 2nd Embodiment. It is a figure which shows the structure of the 1st model used for simulation. It is a figure which shows the structure of the 2nd model used for simulation. 4 is a graph showing the relationship between the gate-source voltage (Vgs) and the drain current Id in the first model; 4 is a graph showing the relationship between the gate-source voltage (Vgs) and the drain current Id in the second model; 4 is a table showing the relationship between the film thickness of the p-type AlGaN layer 423 and the threshold voltage Vth in the first model; 4 is a graph showing the relationship between the film thickness of the p-type AlGaN layer 423 and the threshold voltage Vth in the first model; FIG. 11 is a graph (part 1) showing the Id-Vd characteristics in the first model; FIG. 7 is a graph (part 2) showing Id-Vd characteristics in the first model; FIG. 11 is a graph (Part 1) showing Id-Vd characteristics in the second model; FIG. FIG. 11 is a graph (part 2) showing Id-Vd characteristics in the second model; FIG. 3 is a graph (part 3) showing Id-Vd characteristics in the first model; 4 is a graph showing the relationship between the position of the GaN semiconductor and the Si concentration; 1 is a graph showing the relationship between semiconductor position and Mg concentration. FIG. 29 is a table showing Mg concentration values in FIG. 28. FIG.

Hereinafter, specific embodiments will be described with reference to the drawings, taking a semiconductor device and its manufacturing method as an example. However, the technology herein is not limited to these embodiments. The width and thickness of each layer do not represent actual size ratios. As used herein, a non-doped region is a region that is not intentionally doped with a p-type dopant or an n-type dopant.

(First embodiment)
FIG. 1 is a schematic configuration diagram of a semiconductor device 100 of the first embodiment. Semiconductor device 100 is a field effect transistor (FET) having a polarized superjunction. The semiconductor device 100 has a Group III nitride semiconductor. The semiconductor element 100 includes a substrate Sub1, a first semiconductor layer 110, a second semiconductor layer 120, a third semiconductor layer 130, a fourth semiconductor layer 140, a source electrode S1, a drain electrode D1, and a gate electrode G1. and have

The substrate Sub1 is a sapphire substrate, Si substrate, SiC substrate, or other substrates. The substrate Sub1 has a first surface Sub1a. The first surface Sub1a is a semiconductor formation surface.

The first semiconductor layer 110 is a non-doped Group III nitride semiconductor layer. The first semiconductor layer 110 is, for example, a GaN layer. The first semiconductor layer 110 is formed on the substrate Sub1. The film thickness of the first semiconductor layer 110 is, for example, 1 μm or more and 5 μm or less. Film thicknesses other than those described above may be used.

The second semiconductor layer 120 is a Group III nitride semiconductor layer containing Al. The second semiconductor layer 120 is, for example, an AlGaN layer. A second semiconductor layer 120 is formed on the first semiconductor layer 110 . The bandgap of the second semiconductor layer 120 is larger than the bandgap of the first semiconductor layer 110 . The film thickness of the second semiconductor layer 120 is, for example, 20 nm or more and 150 nm or less. Film thicknesses other than those described above may be used.

The third semiconductor layer 130 is a Group III nitride semiconductor layer. The third semiconductor layer 130 is, for example, a GaN layer. The third semiconductor layer 130 is formed on part of the second semiconductor layer 120 . As shown in FIG. 1 , the lateral width of the third semiconductor layer 130 is smaller than the lateral width of the second semiconductor layer 120 . That is, in a cross section passing through the source electrode S1, the drain electrode D1, and the gate electrode G1, the length of the third semiconductor layer 130 in the direction parallel to the first surface Sub1a of the substrate Sub1 is equal to the length of the substrate Sub1 of the second semiconductor layer 120. It is shorter than the length in the direction parallel to one surface Sub1a. The film thickness of the third semiconductor layer 130 is, for example, 20 nm or more and 150 nm or less. Film thicknesses other than those described above may be used.

The fourth semiconductor layer 140 is a p-type Group III nitride semiconductor layer. The fourth semiconductor layer 140 is, for example, a p-type GaN layer. A fourth semiconductor layer 140 is formed on the third semiconductor layer 130 . The fourth semiconductor layer 140 has a p ⁻ GaN layer 141 and a p ⁺ GaN layer 142 . A p ⁻ GaN layer 141 overlies the third semiconductor layer 130 and a p ⁺ GaN layer 142 overlies the p ⁻ GaN layer 141 . The p ⁻ GaN layer 141 is in contact with the third semiconductor layer 130 . The p ⁺ GaN layer 142 is in contact with the gate electrode G1. The concentration of Mg in the p ⁻ GaN layer 141 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 8×10 ¹⁹ cm ^{−3 or} less. The concentration of Mg in the p ⁺ GaN layer 142 is, for example, 8×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. Thus, the Mg concentration in the p ⁺ GaN layer 142 is higher than the Mg concentration in the p ⁻ GaN layer 141 . The film thickness of the fourth semiconductor layer 140 is, for example, 20 nm or more and 200 nm or less. Film thicknesses other than those described above may be used.

The source electrode S<b>1 and the drain electrode D<b>1 are formed in contact with the second semiconductor layer 120 . A source electrode S<b>1 , a drain electrode D<b>1 and a third semiconductor layer 130 are formed on the same surface of the second semiconductor layer 120 . The source electrode S<b>1 and the drain electrode D<b>1 are in contact with the first non-doped region 121 of the second semiconductor layer 120 .

A gate electrode G1 is formed on the fourth semiconductor layer 140 . Gate electrode G1 is in contact with p ⁺ GaN layer 142 .

The bandgap of the second semiconductor layer 120 is larger than the bandgaps of the first semiconductor layer 110 and the third semiconductor layer 130 . Therefore, the semiconductor element 100 can generate a two-dimensional electron gas (2DEG) on the second semiconductor layer 120 side of the first semiconductor layer 110, and can generate a two-dimensional electron gas (2DEG) on the second semiconductor layer 120 side of the third semiconductor layer 130. A two-dimensional hole gas (2DHG) can be generated.

2. First Region and Second Region As shown in FIG. 1, the semiconductor device 100 has a first region R1 and a second region R2. The second semiconductor layer 120 has a first non-doped region 121 , a second non-doped region 122 and a second semiconductor layer p-type region 123 . The third semiconductor layer 130 has a third semiconductor layer non-doped region 131 and a third semiconductor layer p-type region 132 .

The second region R2 is a region including a projection region obtained by projecting the p-type region above the first semiconductor layer 110 onto the first surface Sub1a of the substrate Sub1 on a plane perpendicular to the projection region. A second region R2 surrounds the projection region. The outer edge of the projected region obtained by projecting the p-type region above the first semiconductor layer 110 onto the first surface Sub1a of the substrate Sub1 consists of the third semiconductor layer p-type region 132, the second semiconductor layer p-type region 123, and the fourth semiconductor layer p-type region 123. In the semiconductor layer 140, it is the outer edge of the region where the p-type dopant is most diffused in the direction (lateral direction) parallel to the first surface Sub1a.

A projection area obtained by projecting the third semiconductor layer p-type region 132 onto the first surface Sub1a of the substrate Sub1 is a projection area obtained by projecting the second semiconductor layer p-type region 123 onto the first surface Sub1a of the substrate Sub1, and a projection area obtained by projecting the fourth semiconductor layer 140 onto the first surface Sub1a of the substrate Sub1. onto the first surface Sub1a of the substrate Sub1.

The p-type region includes the third semiconductor layer p-type region 132 , the second semiconductor layer p-type region 123 and the fourth semiconductor layer 140 . The dotted regions in FIG. 1 indicate p-type regions. The area of the projection region of the p-type region projected onto the first surface Sub1a of the substrate Sub1 is smaller than the area of the projection region of the second semiconductor layer 120 projected onto the first surface Sub1a of the substrate Sub1.

The second region R2 is a region having a p-type semiconductor. The first region R1 is a region other than the second region R2. Therefore, the first region R1 is a region that does not have a p-type semiconductor.

The first semiconductor layer 110 is a non-doped region that is intentionally not doped with impurities over the first region R1 and the second region R2.

The second semiconductor layer 120 has a first non-doped region 121 in the first region R1, a second non-doped region 122 in the first semiconductor layer 110 side of the second region R2, and a third region 122 in the second region R2. It has a second semiconductor layer p-type region 123 on the semiconductor layer 130 side. Note that the second semiconductor layer 120 in the first region R1 does not have a p-type region.

The first non-doped region 121 of the first region R1 is, for example, an AlGaN layer. The first non-doped region 121 is a region not intentionally doped with impurities.

The second non-doped region 122 of the second region R2 is, for example, an AlGaN layer. The second non-doped region 122 is a region not intentionally doped with impurities.

The second semiconductor layer p-type region 123 of the second region R2 is, for example, a p-type AlGaN layer. The p-type dopant of the second semiconductor layer p-type region 123 is diffused from the fourth semiconductor layer 140 by thermal diffusion. A p-type dopant is, for example, Mg. In the second region R2, the second semiconductor layer p-type region 123 has a non-doped region on the first non-doped region 121 side. This non-doped region is a region in which Mg hardly reaches due to diffusion of Mg, which will be described later.

The third semiconductor layer 130 has a third semiconductor layer non-doped region 131 located in the first region R1 and a third semiconductor layer p-type region 132 located in the second region R2. In the second region R2, the third semiconductor layer p-type region 132 has a non-doped region on the second semiconductor layer 120 side and the third semiconductor layer non-doped region 131 side. This non-doped region is a region in which Mg hardly reaches due to diffusion of Mg, which will be described later. Therefore, as shown in FIG. 1, the third semiconductor layer p-type region 132 is T-shaped in a cross section perpendicular to the first surface Sub1a of the substrate Sub1.

The fourth semiconductor layer 140 has only p-type semiconductors. This p-type semiconductor is the fourth semiconductor layer p-type region.

The first region R1 does not have a p-type region. The second region R2 has a non-doped region and a p-type region. In the second region R2, there is a non-doped region on the substrate Sub1 side and a p-type region on the gate electrode G1 side.

In the first region R1, the first semiconductor layer 110, the first non-doped region 121 of the second semiconductor layer 120, and the third semiconductor layer non-doped region 131 of the third semiconductor layer 130 are non-doped regions.

In the second region R2, the first semiconductor layer 110 and the second non-doped region 122 of the second semiconductor layer 120 are non-doped regions.

In the second region R2, the second semiconductor layer p-type region 123 of the second semiconductor layer 120, the third semiconductor layer p-type region 132 of the third semiconductor layer 130, and the fourth semiconductor layer 140 are connected to each other. It is a continuous p-type region. The third semiconductor layer p-type region 132 of the third semiconductor layer 130 is in contact with the second semiconductor layer p-type region 123 and the fourth semiconductor layer 140 . The third semiconductor layer p-type region 132 and the second semiconductor layer p-type region 123 are continuous at the interface between the third semiconductor layer 130 and the second semiconductor layer 120 . The third semiconductor layer p-type region 132 and the fourth semiconductor layer 140 are continuous at the interface between the third semiconductor layer 130 and the fourth semiconductor layer 140 .

The source electrode S1 and the drain electrode D1 are formed in contact with the first non-doped region 121 of the first region R1. Thus, the source electrode S1 and the drain electrode D1 are positioned within the range of the first region R1.

The gate electrode G1 is formed on the p ⁺ GaN layer 142 in the second region R2. That is, the gate electrode G1 is positioned above the third semiconductor layer p-type region 132 and in the second region R2. Thus, the gate electrode G1 is positioned within the range of the second region R2.

The second semiconductor layer p-type region 123 is formed by diffusing Mg in the p-type fourth semiconductor layer 140 and the third semiconductor layer p-type region 132 . The Mg contained in the third semiconductor layer p-type region 132 includes Mg diffused from the fourth semiconductor layer 140 in addition to Mg originally present. The Mg concentration of the fourth semiconductor layer 140 tends to be higher than the Mg concentration of the third semiconductor layer p-type region 132 , and the Mg concentration of the third semiconductor layer p-type region 132 is higher than that of the second semiconductor layer p-type region 123 . concentration tends to be higher.

Further, the Mg concentration in the direction perpendicular to the first surface Sub1a of the substrate Sub1 is continuous at the boundary between the fourth semiconductor layer 140 and the third semiconductor layer p-type region 132 within the measurement error of the measuring device, It is continuous at the boundary between the third semiconductor layer p-type region 132 and the second semiconductor layer p-type region 123 .

Also, the Al composition in the second semiconductor layer 120 is uniform within the measurement error of the measuring device. That is, the Al composition in the first non-doped region 121 of the first region R1, the second non-doped region 122 of the second region R2, and the second semiconductor layer p-type region 123 of the second region R2 is uniform.

The first non-doped region 121 of the first region R1 and the second non-doped region 122 of the second region R2 are continuous. These compositions are the same within the measurement error of the measurement equipment.

The film thickness of the second non-doped region 122 of the second region R2 is, for example, 0.5 nm or more and 10.5 nm or less. Preferably, it is 1 nm or more and 10 nm or less.

The concentration of Mg in the second region R2 decreases toward the first surface Sub1a of the substrate Sub1 inside the second semiconductor layer p-type region 123 and the third semiconductor layer p-type region 132 . The second semiconductor layer p-type region 123 of the second region R2 includes a first concentration gradient region with a gentle Mg concentration gradient and a steep Mg concentration gradient with respect to the direction perpendicular to the first surface Sub1a of the substrate Sub1. and a second concentration gradient region. The first concentration gradient region is located on the third semiconductor layer 130 side, and the second concentration gradient region is located on the first semiconductor layer 110 side.

In the first concentration gradient region, the Mg concentration gradient in the direction perpendicular to the first surface Sub1a of the substrate Sub1 is, for example, 1×10 ¹² cm ⁻³ to 2×10 ¹⁶ cm ⁻³ /nm.

The Mg concentration in the second concentration gradient region decreases more steeply than the Mg concentration in the first concentration gradient region toward the first surface Sub1a of the substrate Sub1.

The difference between the Mg concentration of the third semiconductor layer p-type region 132 and the Mg concentration of the second semiconductor layer p-type region 123 is relatively small.

In this manner, the second semiconductor layer 120 has the second semiconductor layer p-type region 123, the second non-doped region 122, and the first non-doped region 121 arranged side by side in a direction parallel to the first surface Sub1a of the substrate Sub1. ing.

Note that the boundary between the second semiconductor layer p-type region 123 and the second non-doped region 122 can be distinguished by the Mg concentration. The Mg concentration sharply decreases from the second semiconductor layer p-type region 123 to the second non-doped region 122 in the direction perpendicular to the first surface Sub1a of the substrate Sub1. The boundary is, for example, an inflection point of Mg concentration in the Mg profile in the thickness direction of the semiconductor layer in SIMS analysis.

3. Two-Dimensional Electron Gas and Two-Dimensional Hole Gas The bandgap of the second semiconductor layer 120 is larger than the bandgaps of the first semiconductor layer 110 and the third semiconductor layer 130 . Therefore, the semiconductor element 100 can generate a two-dimensional electron gas (2DEG) on the side of the second semiconductor layer 120 of the first semiconductor layer 110, and the second semiconductor layer 120 of the third semiconductor layer 130 can generate a two-dimensional electron gas (2DEG). It is possible to generate a two-dimensional Hall gas (2DHG) on the side.

The semiconductor device 100 has a second semiconductor layer p-type region 123 of the second semiconductor layer 120 in the second region R2. Therefore, the state of the two-dimensional electron gas in the second region R2 is different from the state of the two-dimensional electron gas in the first region R1.

The second semiconductor layer p-type region 123 and the third semiconductor layer p-type region 132 of the second region R2 exist, and the second non-doped region 122 exists thinly. Since the p-type region is formed halfway through the second semiconductor layer 120, the band structure of the semiconductor changes. Therefore, the concentration of the two-dimensional electron gas in the second region R2 in the semiconductor device 100 becomes lower than the concentration of the two-dimensional electron gas in a conventional semiconductor device without the second region R2. As a result, the threshold voltage of the semiconductor device 100 is increased compared to conventional devices. The semiconductor device 100 of the first embodiment operates normally off.

4. Method for Manufacturing Semiconductor Device A method for manufacturing the semiconductor device 100 will be described. Layers in the middle of the manufacturing process are denoted by the same notation as the final device structure. For example, even the second semiconductor layer before the formation of the p-type region is referred to as the second semiconductor layer 120 .

4-1. Non-Dope Semiconductor Layer Forming Step FIG. 2 is a diagram (1) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment. As shown in FIG. 2, a first semiconductor layer 110, a second semiconductor layer 120, and a third semiconductor layer 130 are grown on the first surface Sub1a of the substrate Sub1. At this stage, the third semiconductor layer 130 evenly covers the upper surface of the second semiconductor layer 120 .

4-2. First Etching Step FIG. 3 is a diagram (2) for explaining the method for manufacturing the semiconductor device 100 of the first embodiment. A chlorine-based gas such as Cl ₂ is used as an etching gas to etch the semiconductor layer. A portion of the third semiconductor layer 130 is removed and a portion of the second semiconductor layer 120 is exposed by etching using a mask. By adding a small amount of oxygen to the etching atmosphere, Al on the surface is oxidized. Therefore, AlGaN is hardly etched. That is, the second semiconductor layer 120 remains without being etched. The exposed second semiconductor layer 120 and the remaining third semiconductor layer 130 constitute the recess U1.

4-3. P-Type Semiconductor Layer Forming Step FIG. 4 is a diagram (No. 3) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment. As shown in FIG. 4, a p-type semiconductor layer is grown on the exposed second semiconductor layer 120 and the remaining third semiconductor layer 130 (recess U1). This p-type semiconductor layer is a portion corresponding to the third semiconductor layer p-type region 132 and the fourth semiconductor layer 140 of the third semiconductor layer 130 .

4-4. Second Etching Step FIG. 5 is a diagram (No. 4) for explaining the method for manufacturing the semiconductor device 100 of the first embodiment. Next, by etching using a mask, part of the third semiconductor layer 130 and the fourth semiconductor layer 140 is removed, leaving the remainder. At this stage, the third semiconductor layer p-type region 132 and the fourth semiconductor layer 140 region are almost formed. Also, the regions for forming the source electrode S1 and the drain electrode D1 in the second semiconductor layer 120 are exposed.

4-5. Heat Treatment Process FIG. 6 is a diagram (No. 5) for explaining the method for manufacturing the semiconductor device 100 of the first embodiment. By performing heat treatment under high pressure, Mg in the third semiconductor layer p-type region 132 and the fourth semiconductor layer 140 diffuses into the second semiconductor layer 120 . As a result, the second semiconductor layer p-type region 123 is formed in the second region R2 of the second semiconductor layer 120 and the second non-doped region 122 is left. In this way, Mg is diffused halfway through the second semiconductor layer 120 and is not diffused into the first semiconductor layer 110 . At this stage, the second semiconductor layer p-type region 123, the third semiconductor layer p-type region 132, the non-doped region adjacent to the second semiconductor layer p-type region 123, and the third semiconductor layer p-type region 132 A non-doped region is formed.

The atmosphere gas in the heat treatment process is, for example, nitrogen. The substrate temperature in the heat treatment process is, for example, 1100° C. or higher and 1400° C. or lower. The pressure in the heat treatment step is a pressure equal to or higher than the saturated vapor pressure of the Group III nitride semiconductor at the heat treatment temperature. The pressure of the heat treatment process is, for example, 100 MPa or more and 2 GPa or less. The processing time of the heat treatment step is, for example, 1 minute or more and 60 minutes or less. The above numerical range is only a guide, and may be other than the above.

4-6. Electrode Forming Step FIG. 7 is a diagram (No. 6) for explaining the method of manufacturing the semiconductor device 100 of the first embodiment. A source electrode S1 and a drain electrode D1 are formed in a region above the second semiconductor layer 120 where the third semiconductor layer 130 is not formed. Also, a gate electrode G1 is formed on the fourth semiconductor layer 140 .

Thus, the non-doped first semiconductor layer 110 is formed above the substrate Sub1. A non-doped second semiconductor layer 120 is formed on the first semiconductor layer 110 . A p-type region is formed above the second semiconductor layer 120 . The p-type dopant is diffused from the p-type region to the middle of the second semiconductor layer 120 by performing heat treatment at a pressure equal to or higher than the saturated vapor pressure of the Group III nitride semiconductor at the heat treatment temperature. A first region R1 in which the p-type dopant is not diffused from the p-type region to the second semiconductor layer 120 and a second region R2 including a region in which the p-type dopant is diffused from the p-type region to the second semiconductor layer 120 are formed. . A gate electrode G1 is formed within the range of the second region R2.

5. Effect of First Embodiment The semiconductor device 100 of the first embodiment has a first region R1 and a second region R2. The first region R<b>1 has the first semiconductor layer 110 , the first non-doped region 121 of the second semiconductor layer 120 , and the third semiconductor layer non-doped region 131 of the third semiconductor layer 130 . The first region R1 has a non-doped layer and does not have a doped layer. The second region R2 includes the first semiconductor layer 110, the second non-doped region 122 and the second semiconductor layer p-type region 123 of the second semiconductor layer 120, and the third semiconductor layer p-type region 132 of the third semiconductor layer 130. , and a fourth semiconductor layer 140 . The second region R2 has a doped layer on the gate electrode G1 side and a non-doped layer on the substrate Sub1 side.

Also, the second non-doped region 122 of the second region R2 is sufficiently thin. Therefore, the threshold voltage of the semiconductor device 100 becomes a positive voltage, and the semiconductor device 100 operates normally off.

6. Modification 6-1. Semiconductor Device Without Polarized Superjunction FIG. 8 is a schematic configuration diagram of a semiconductor device 200 in a modification of the first embodiment. Semiconductor device 200 is a HEMT that does not have a polarized superjunction. The semiconductor element 200 has a substrate Sub1, a first semiconductor layer 110, a second semiconductor layer 120A, a p-type semiconductor layer 240, a source electrode S1, a drain electrode D1, and a gate electrode G1. The semiconductor element 200 also has a first region R1 and a second region R2. The second region R2 of the semiconductor element 200 has a first semiconductor layer 110, a second semiconductor layer 120A and a p-type semiconductor layer 240. As shown in FIG. The p-type semiconductor layer 240 is the third semiconductor layer p-type region. First semiconductor layer 110 and second non-doped region 122 are non-doped layers, and second semiconductor layer p-type region 123A and p-type semiconductor layer 240 are doped layers. That is, the second region R2 has a non-doped layer on the substrate Sub1 side and a doped layer on the gate electrode G1 side.

Even in this case, the semiconductor device 200 operates normally off.

6-2. Shape of Fourth Semiconductor Layer The fourth semiconductor layer 140 is a layer obtained by regrowing a p-type semiconductor on the concave portion U1. Therefore, the fourth semiconductor layer 140 may be recessed from its surroundings. For example, the surface of the fourth semiconductor layer 140 may be located closer to the first surface Sub1a of the substrate Sub1 than the surface of the third semiconductor layer 130 is.

6-3. p-type dopant p-type dopants other than Mg may be used.

6-4. Stacked Structure The stacked structure of the semiconductor layers may be a stacked structure different from that of the semiconductor element 100 of the first embodiment. For example, there may be other layers between the substrate Sub1 and the first semiconductor layer 110 .

6-5. Combinations The above variations may be combined.

(Second embodiment)
A second embodiment will be described. Differences from the first embodiment will be described.

1. Semiconductor Device FIG. 9 is a schematic configuration diagram of a semiconductor device 100A of the second embodiment. The semiconductor element 100A differs from the first embodiment in the second semiconductor layer 120A and the third semiconductor layer 130A. The second semiconductor layer 120A has a first non-doped region 121, a second non-doped region 122, and a second semiconductor layer p-type region 123A. The third semiconductor layer 130A has a third semiconductor layer non-doped region 131 and a third semiconductor layer p-type region 132A.

The second semiconductor layer p-type region 123A and the third semiconductor layer p-type region 132A hardly have a non-doped region within the range of the second region R2. The lateral widths of the Mg diffusion regions in the fourth semiconductor layer 140, the second semiconductor layer p-type region 123A, and the third semiconductor layer p-type region 132A are substantially equal.

1. Manufacturing method of semiconductor element 1-1. Semiconductor Layer Forming Step FIG. 10 is a diagram (part 1) for explaining the method of manufacturing the semiconductor element 100A of the second embodiment. A first semiconductor layer 110, a second semiconductor layer 120A, a third semiconductor layer 130A, and a fourth semiconductor layer 140 are grown in this order on the first surface Sub1a of the substrate Sub1. However, at this stage, the second semiconductor layer 120A and the third semiconductor layer 130A are non-doped layers, and the fourth semiconductor layer 140 is a p-type semiconductor layer.

1-2. First Etching Step FIG. 11 is a diagram (part 2) for explaining the method of manufacturing the semiconductor device 100A of the second embodiment. A portion of the fourth semiconductor layer 140 is removed by dry etching using a mask. At this time, a region for forming the gate electrode G1 is left. The fourth semiconductor layer 140 in the region corresponding to the first region R1 is removed, and the fourth semiconductor layer 140 that is part of the p-type region corresponding to the second region R2 remains.

1-3. Heat Treatment Process FIG. 12 is a diagram (part 3) for explaining the method of manufacturing the semiconductor device 100A of the second embodiment. As a result, Mg in the fourth semiconductor layer 140 diffuses halfway through the third semiconductor layer 130A and the second semiconductor layer 120A. Thereby, the p-type region of the second region R2 of the semiconductor element 100A is formed. The heat treatment conditions are the same as in the first embodiment. Since the semiconductor layer directly above the second semiconductor layer 120A is a non-doped layer, the heat treatment time may be longer than in the first embodiment.

1-4. Second Etching Step FIG. 13 is a diagram (No. 4) for explaining the method of manufacturing the semiconductor device 100A of the second embodiment. A portion of the third semiconductor layer 130A is removed by dry etching using a mask. As a result, regions for forming the source electrode S1 and the drain electrode D1 are exposed.

1-5. Electrode Forming Step FIG. 14 is a diagram (No. 5) for explaining the method of manufacturing the semiconductor device 100A of the second embodiment. A source electrode S1 and a drain electrode D1 are formed to contact the second semiconductor layer 120A in the first region R1. A gate electrode G1 is formed on the fourth semiconductor layer 140 in the second region R2.

2. Effects of the Second Embodiment In the method for manufacturing a semiconductor device 100A of the second embodiment, when forming the second region R2, the second semiconductor layer 120A facing the third semiconductor layer 130A is exposed to an etching gas. There is no Therefore, there is no possibility that the surface of the second semiconductor layer 120A facing the third semiconductor layer 130A will be roughened. In addition, since there is no need to perform regrowth after etching, there is no contamination of the regrowth interface with impurities such as Si. Therefore, leakage current of the semiconductor element is suppressed.

3. Modification 3-1. Semiconductor Device FIG. 15 is a schematic configuration diagram of a semiconductor device 300 in a modification of the second embodiment. The semiconductor element 300 has a first semiconductor layer 110, a second semiconductor layer 120A, a third semiconductor layer 130A, a fourth semiconductor layer 340, a source electrode S1, a drain electrode D1, and a gate electrode G1. .

The fourth semiconductor layer 340 has a p ⁺ GaN layer 341 , a p ⁻ GaN layer 342 and a p ⁺ GaN layer 343 from the side of the third semiconductor layer 130 . The concentration of Mg in the p ⁺ GaN layer 341 is, for example, 8×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. The concentration of Mg in the p ⁻ GaN layer 342 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 8×10 ¹⁹ cm ^{−3 or} less. The concentration of Mg in the p ⁺ GaN layer 343 is, for example, 8×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less.

You may combine with the modification of 1st Embodiment. For example, when manufacturing a semiconductor device 200 as shown in FIG. 8, a p-type semiconductor is formed on the second semiconductor layer 120 .

(simulation)
1. Simulation Method Atlas manufactured by Silvaco was used for the simulation. Based on this, the Id-Vd characteristics, the threshold voltage, and the like were evaluated.

FIG. 16 is a diagram showing the structure of the first model used for the simulation. FIG. 16 shows an element structure corresponding to the semiconductor element 100A of the second embodiment. The total thickness of the AlGaN layer 422 and the p-type AlGaN layer 423 in the second region R2 is the same as the thickness of the AlGaN layer 421 in the first region R1. The thickness of the AlGaN layer 421 in the first region R1 was fixed at 25 nm, and the thickness of the p-type AlGaN layer 423 in the second region R2 was varied.

The film thickness of the AlGaN layer 421 was set to 25 nm. The total thickness of the AlGaN layer 422 and the p-type AlGaN layer 423 was set to 25 nm. The horizontal length of the AlGaN layer 422 and the p-type AlGaN layer 423 was set to 4 μm. The Al composition of the AlGaN layer 421 was set to 0.25 (molar fraction). The Al composition of the AlGaN layer 422 and the Al composition of the p-type AlGaN layer 423 were set to 0.25. The donor concentration of the AlGaN layers 421 and 422 was set to 1×10 ¹⁵ cm ⁻³ . This value is comparable to the donor concentration of non-doped GaN. The acceptor concentration of the p-type AlGaN layer 423 was set to 3×10 ¹⁹ cm ⁻³ . In the simulation, the film thickness of the p-type AlGaN layer 423 was changed, and the film thickness of the AlGaN layer 422 was also changed accordingly.

The film thickness of the GaN layer 410 was set to 1.5 μm. The donor concentration of the GaN layer 410 was set to 1×10 ¹⁵ cm ⁻³ .

The film thickness of the GaN layer 431 was set to 10 nm. The lateral length of the GaN layer 431 was set to 6 μm. The donor concentration of the GaN layer 431 was set to 1×10 ¹⁵ cm ⁻³ .

The film thickness of the p-type GaN layer 432 was set to 10 nm. The lateral length of the p-type GaN layer 432 was set to 4 μm. The acceptor concentration of the p-type GaN layer 432 was set to 3×10 ¹⁹ cm ⁻³ .

The film thickness of the p-type GaN layer 440 was set to 30 nm. The lateral length of the p-type GaN layer 440 was set to 4 μm. The acceptor concentration was set to 3×10 ¹⁹ cm ⁻³ .

The polarization superjunction length (L _PSJ ) was set to 6 μm. The lateral width of the gate electrode G1 is set to 3 μm.

FIG. 17 is a diagram showing the structure of the second model used for the simulation. FIG. 17 discloses an element structure corresponding to a conventional PSJ type semiconductor element. The element structure shown in FIG. 17 corresponds to the case where the heat treatment process is not performed in the manufacturing process of the semiconductor element 100 of the first embodiment. That is, Mg does not diffuse from the p-type GaN layer 540 immediately below the gate electrode G1 into the GaN layer 530 and AlGaN layer 520 in contact with the p-type GaN layer 540 . That is, in the second model, no p-type semiconductor layer exists in the regions corresponding to the second semiconductor layer and the third semiconductor layer.

The thickness of the AlGaN layer 520 was set to 25 nm. The Al composition of the AlGaN layer 520 was set to 0.25 (molar fraction). The AlGaN layer 520 has a donor concentration of 1×10 ¹⁵ cm ⁻³ .

The film thickness of the GaN layer 530 was set to 10 nm. The lateral length of the GaN layer 530 was set to 10 μm. The donor concentration of the GaN layer 530 was set to 1×10 ¹⁵ cm ⁻³ .

The film thickness of the p-type GaN layer 540 was set to 30 nm. The lateral length of the p-type GaN layer 540 was set to 4 μm. The acceptor concentration of the p-type GaN layer 540 was set to 3×10 ¹⁹ cm ⁻³ .

The polarization superjunction length (L _PSJ ) was set to 6 μm. The lateral width of the gate electrode G1 is set to 3 μm.

2. Simulation result 2-1. Threshold Voltage FIG. 18 is a graph showing the relationship between the gate-source voltage (Vgs) and the drain current Id in the first model. The horizontal axis of FIG. 18 is the gate-source voltage (Vgs). The vertical axis in FIG. 18 is the drain current Id. The thickness of the p-type AlGaN layer 423 was set to 20 nm, and the thickness of the AlGaN layer 422 was set to 5 nm. A drain-source voltage (Vds) was set to 20V.

As shown in FIG. 18, the drain current Id rises when the gate-source voltage (Vgs) has a positive value. The threshold voltage is approximately 2V. In this way, Mg diffuses halfway through the AlGaN layer, thereby increasing the threshold voltage. The semiconductor device at this time operates normally off.

FIG. 19 is a graph showing the relationship between the gate-source voltage (Vgs) and the drain current Id in the second model. The horizontal axis of FIG. 19 is the gate-source voltage (Vgs). The vertical axis of FIG. 19 is the drain current Id. A drain-source voltage (Vds) was set to 20V.

As shown in FIG. 19, the drain current Id rises when the gate-source voltage (Vgs) has a negative value. The threshold voltage is approximately -4V. The semiconductor element at this time operates normally on.

2-2. Relationship Between Mg Diffusion Region and Threshold Voltage FIG. 20 is a table showing the relationship between the thickness of the p-type AlGaN layer 423 and the threshold voltage Vth in the first model. The threshold voltage Vth tends to increase as the thickness of the p-type AlGaN layer 423 increases.

FIG. 21 is a graph showing the relationship between the thickness of the p-type AlGaN layer 423 and the threshold voltage Vth in the first model. The horizontal axis of FIG. 21 is the film thickness of the p-type AlGaN layer 423 . The vertical axis of FIG. 21 is the threshold voltage Vth.

As shown in FIG. 21, the more Mg is diffused toward the second semiconductor layer 120, the higher the threshold voltage Vth. The threshold voltage Vth takes a positive value when the thickness of the p-type AlGaN layer 423 is approximately 14.5 nm or more, that is, when the thickness of the AlGaN layer 422 immediately below the p-type AlGaN layer 423 is approximately 10.5 nm or less. . Under this condition, the semiconductor device operates normally off.

2-3. Id-Vd Characteristics FIG. 22 is a graph (part 1) showing the Id-Vd characteristics in the first model. The horizontal axis of FIG. 22 is the drain-source voltage (Vds). The vertical axis in FIG. 22 is the drain current Id (10 ⁻⁵ A).

As shown in FIG. 22, forward current flows at positive drain-source voltage (Vds).

FIG. 23 is a graph (part 2) showing the Id-Vd characteristics in the first model. The horizontal axis of FIG. 23 is the drain-source voltage (Vds). The vertical axis in FIG. 23 is the drain current Id (pA).

FIG. 24 is a graph (Part 1) showing the Id-Vd characteristics in the second model. The horizontal axis of FIG. 24 is the drain-source voltage (Vds). The vertical axis in FIG. 24 is the drain current Id (10 ⁻⁵ A).

FIG. 25 is a graph (part 2) showing the Id-Vd characteristics in the second model. The horizontal axis of FIG. 25 is the drain-source voltage (Vds). The vertical axis of FIG. 25 is the drain current Id (pA).

FIG. 26 is a graph (part 3) showing the Id-Vd characteristics in the first model. The horizontal axis of FIG. 26 is the drain-source voltage (Vds). The vertical axis in FIG. 26 is the drain current Id (10 ⁻⁵ A). The film thickness of the p-type AlGaN layer 423 was set to 20 nm.

(experiment)
1. Segregation of Si 1-1. Experimental Method After growing the GaN layer on the sapphire substrate inside the MOCVD furnace, the substrate was taken out from the MOCVD furnace and placed again inside the MOCVD furnace to grow the GaN layer. The Si concentration of the GaN layer was measured by SIMS.

1-2. Experimental Results FIG. 27 is a graph showing the relationship between the position of the GaN semiconductor and the Si concentration. The horizontal axis of FIG. 27 is the depth of the GaN semiconductor from the surface. The vertical axis of FIG. 27 is the Si concentration.

As shown in FIG. 27, in the region where GaN is grown inside the MOCVD furnace, the Si concentration ranges from about 1×10 ¹⁴ cm ⁻³ to about 1×10 ¹⁵ cm ⁻³ . The Si concentration is as high as about 1×10 ¹⁷ cm ⁻³ in the GaN region that is thought to have come into contact with the atmosphere when taken out of the MOCVD furnace.

2. Diffusion of Mg 2-1. Experimental Method An undoped GaN layer was grown to a thickness of 2 μm on a sapphire substrate, an undoped AlGaN layer having an Al composition of 0.25 was grown thereon to a thickness of 25 nm, and Mg-doped p-type GaN was grown thereon. The layer was grown with a thickness of 120 nm. The Mg concentration of this p-type GaN layer was 3×10 ¹⁸ cm ⁻³ . Further, a highly Mg-doped p-type GaN layer was grown thereon to a thickness of 3 nm. The Mg concentration of this p-type GaN layer was 8×10 ¹⁹ cm ⁻³ .

A heat treatment step was performed. The heat treatment temperature was 1300°C or 1400°C. The pressure in the furnace was 1 GPa. Processing time was 5 minutes. The atmospheric gas was nitrogen gas.

2-2. Experimental Results FIG. 28 is a graph showing the relationship between the position of the semiconductor and the Mg concentration. The horizontal axis of FIG. 28 is the depth of the semiconductor from the surface. The vertical axis of FIG. 28 is the Mg concentration. UHPA in FIG. 28 indicates a heat treatment process (ultra-high pressure annealing).

FIG. 28 shows the Mg concentration before heat treatment and the Mg concentration after heat treatment. As shown in FIG. 28, by performing heat treatment at high temperature and high pressure, Mg diffuses from the surface side of the semiconductor toward the inner side of the semiconductor.

When the heat treatment temperature is high, Mg diffuses to a farther position. As the heat treatment temperature rises, the change rate of the Mg concentration in the direction perpendicular to the plate surface of the substrate becomes gentle.

FIG. 29 is a table showing Mg concentration values in FIG. At a position 30 nm deep from the surface of the semiconductor, the Mg concentration before annealing was 5.1×10 ¹⁸ cm ⁻³ and after annealing at 1300° C. was 2.7×10 ¹⁸ cm ⁻³ . At a position 119 nm deep from the surface of the semiconductor, the Mg concentration before annealing was 7.4×10 ¹⁷ cm ⁻³ and after annealing at 1300° C. was 2.0×10 ¹⁸ cm ⁻³ . By performing annealing in this way, the Mg concentration decreases in the region near the surface of the semiconductor and increases in the region far from the surface of the semiconductor.

(Appendix)
A semiconductor element in a first aspect includes a substrate having a first surface, a first semiconductor layer above the substrate, a second semiconductor layer above the first semiconductor layer, and a third semiconductor above the second semiconductor layer. It has a layer, a gate electrode, and first and second regions. The first semiconductor layer, the second semiconductor layer and the third semiconductor layer are Group III nitride semiconductor layers. The bandgap of the second semiconductor layer is larger than the bandgap of the first semiconductor layer. The third semiconductor layer has a third semiconductor layer p-type region. The second semiconductor layer has a first non-doped region in the first region, a second non-doped region in the second region on the first semiconductor layer side, and a second semiconductor layer in the second region on the third semiconductor layer side. The semiconductor layer has a p-type region. The second region is a region including a projection region obtained by projecting the p-type region above the first semiconductor layer onto the first surface of the substrate on a plane perpendicular to the projection region. The first area is an area other than the second area. The gate electrode is located in the second region above the p-type region of the third semiconductor layer. The third semiconductor layer p-type region and the second semiconductor layer p-type region are continuous at the interface between the third semiconductor layer and the second semiconductor layer.

The semiconductor device in the second aspect has a fourth semiconductor layer over the third semiconductor layer. The fourth semiconductor layer is a Group III nitride semiconductor layer and has a fourth semiconductor layer p-type region.

In the semiconductor device according to the third aspect, the second semiconductor layer in the first region does not have a p-type region.

In the semiconductor device according to the fourth aspect, the second semiconductor layer p-type region of the second region has a Mg concentration gradient of 2×10 ¹⁶ cm ⁻³ /nm or less in a direction perpendicular to the first surface. It has a concentration gradient region.

A semiconductor device in a fifth aspect has a source electrode and a drain electrode. A source electrode and a drain electrode are in contact with the second semiconductor layer in the first region.

In the method of manufacturing a semiconductor device according to the sixth aspect, a non-doped first semiconductor layer made of a Group III nitride semiconductor is formed above the substrate. A non-doped second semiconductor layer made of a Group III nitride semiconductor and having a bandgap larger than that of the first semiconductor layer is formed on the first semiconductor layer. A p-type region made of a Group III nitride semiconductor is formed above the second semiconductor layer. The p-type dopant is diffused from the p-type region to the middle of the second semiconductor layer by performing heat treatment at a pressure equal to or higher than the saturated vapor pressure of the group III nitride semiconductor at the heat treatment temperature. A first region that does not diffuse the p-type dopant from the p-type region into the second semiconductor layer and a second region that includes a region that diffuses the p-type dopant from the p-type region into the second semiconductor layer are formed. A gate electrode is formed in the second region. The second region is a region including a projection region obtained by projecting the p-type region above the first semiconductor layer onto the first surface of the substrate on a plane perpendicular to the projection region.

In the method of manufacturing a semiconductor device according to the seventh aspect, a non-doped or p-type third semiconductor layer is formed on the second semiconductor layer. The first etching removes a portion of the third semiconductor layer to form a recess exposing a portion of the second semiconductor layer. A p-type region is formed over the recess. Mg is diffused from the p-type region to the middle of the second semiconductor layer by heat treatment.

In the method of manufacturing a semiconductor device according to the eighth aspect, a non-doped or p-type third semiconductor layer is formed on the second semiconductor layer. A p-type semiconductor layer is formed on the third semiconductor layer. A first etch removes a portion of the p-type semiconductor layer to leave a portion of the p-type region. Mg is diffused from the p-type region to the middle of the second semiconductor layer by heat treatment.

DESCRIPTION OF SYMBOLS 100... Semiconductor element 110... First semiconductor layer 120... Second semiconductor layer 121... First non-doped region 122... Second non-doped region 123... Second semiconductor layer p-type region 130... Third semiconductor layer 131... Third semiconductor layer non-doped Region 132 Third semiconductor layer p-type region 140 Fourth semiconductor layer 141 p ⁻ GaN layer 142 p ⁺ GaN layer S1 Source electrode D1 Drain electrode G1 Gate electrode R1 First region R2 Second region

Claims (8)

a substrate having a first surface;
a first semiconductor layer above the substrate;
a second semiconductor layer above the first semiconductor layer;
a third semiconductor layer above the second semiconductor layer;
a gate electrode;
a first region and a second region;
has
The first semiconductor layer, the second semiconductor layer, and the third semiconductor layer are
A group III nitride semiconductor layer,
The bandgap of the second semiconductor layer is
larger than the bandgap of the first semiconductor layer,
The third semiconductor layer is
Having a third semiconductor layer p-type region,
The second semiconductor layer is
Having a first non-doped region in the first region,
having a second non-doped region on the first semiconductor layer side of the second region;
having a second semiconductor layer p-type region on the third semiconductor layer side of the second region;
The second region is
a region including a projection region obtained by projecting the p-type region above the first semiconductor layer onto the first surface of the substrate on a plane perpendicular to the projection region;
The first region is
A region other than the second region,
The gate electrode is
located in the second region above the third semiconductor layer p-type region,
The semiconductor element, wherein the third semiconductor layer p-type region and the second semiconductor layer p-type region are continuous at an interface between the third semiconductor layer and the second semiconductor layer. The semiconductor device according to claim 1,
a fourth semiconductor layer above the third semiconductor layer;
The fourth semiconductor layer is
A semiconductor device comprising a group III nitride semiconductor layer and having a fourth semiconductor layer p-type region. In the semiconductor device according to claim 1 or claim 2,
The second semiconductor layer in the first region,
A semiconductor device, including not having a p-type region. In the semiconductor device according to any one of claims 1 to 3,
The second semiconductor layer p-type region of the second region is
A semiconductor device comprising a first concentration gradient region having a Mg concentration gradient of 2×10 ¹⁶ cm ⁻³ /nm or less in a direction perpendicular to the first surface. In the semiconductor device according to any one of claims 1 to 4,
having a source electrode and a drain electrode,
The source electrode and the drain electrode are
A semiconductor device, comprising contacting the second semiconductor layer of the first region. forming a non-doped first semiconductor layer made of a group III nitride semiconductor above the substrate;
forming a non-doped second semiconductor layer made of a Group III nitride semiconductor and having a bandgap larger than that of the first semiconductor layer on the first semiconductor layer;
forming a p-type region made of a group III nitride semiconductor above the second semiconductor layer;
The p-type dopant is diffused from the p-type region to the middle of the second semiconductor layer by performing heat treatment at a pressure equal to or higher than the saturated vapor pressure of the group III nitride semiconductor at the heat treatment temperature,
forming a first region that does not diffuse the p-type dopant from the p-type region into the second semiconductor layer and a second region that includes a region that diffuses the p-type dopant from the p-type region into the second semiconductor layer; ,
forming a gate electrode in the second region;
The second region is
A method of manufacturing a semiconductor device, including a region including a projection region obtained by projecting the p-type region above the first semiconductor layer onto the first surface of the substrate in a plane perpendicular to the projection region. In the method for manufacturing a semiconductor device according to claim 6,
forming a non-doped or p-type third semiconductor layer on the second semiconductor layer;
removing a portion of the third semiconductor layer by a first etching to form a recess exposing a portion of the second semiconductor layer;
forming the p-type region on the recess;
A method of manufacturing a semiconductor device, including diffusing Mg from the p-type region to the middle of the second semiconductor layer by the heat treatment. In the method for manufacturing a semiconductor device according to claim 6,
forming a non-doped or p-type third semiconductor layer on the second semiconductor layer;
forming a p-type semiconductor layer on the third semiconductor layer;
removing a portion of the p-type semiconductor layer by a first etching to leave a portion of the p-type region;
A method of manufacturing a semiconductor device, including diffusing Mg from the p-type region to the middle of the second semiconductor layer by the heat treatment.

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