KR20110074163A - Enhancement normally off nitride vertical semiconductor device and manufacturing method thereof - Google Patents

Abstract

PURPOSE: An enhancement normally off nitride vertical semiconductor device and a manufacturing method thereof are provided to easily implement a normally off enhancement device by forming a recess area to remove a hetero-junction layer and blocking a second dimensional electron gas. CONSTITUTION: In an enhancement normally off nitride vertical semiconductor device and a manufacturing method thereof, a doped first nitride semiconductor layer is formed on the top side a substrate in which a buffer layer is formed(S100,S200). P-type or a high resistivity first nitride semiconductor layer is formed on the top side of the doped layer(S300). A second nitride semiconductor layer is formed on the top side of the P-type or the high resistivity first nitride semiconductor layer(S400). A source electrode is formed in the side of the second nitride semiconductor layer(S600). The gate insulating layer is formed on the top side of the second nitride semiconductor layer and the etched layer(S700). A gate electrode is formed on the top side of the gate insulating layer of the gate region(S800).

Description

Enhancement normally off nitride vertical semiconductor device and manufacturing method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nitride semiconductor device and a method of manufacturing the same, and more particularly, to a method for manufacturing an enhancement normally-off nitride semiconductor device by forming a gate recess region up to a doping layer, and a device thereof. will be.

High electron mobility transistors (HEMTs) are an example of traditional power semiconductor devices. HEMTs are fabricated using Group III nitride semiconductors, which refer to semiconductor alloys from GaN, AlGaN, InGaN or such AlInGaN systems, as mentioned herein.

According to conventionally known techniques, HEMTs are for example a group 1 III nitride semiconductor body composed of undoped GaN and a group II nitride nitride disposed over the group 1 III nitride semiconductor body and composed of AlGaN, for example. A semiconductor body.

As is well known, the heterojunctions of the first group III nitride semiconductor body and the second group III nitride semiconductor body form a conductive region, commonly referred to as a two-dimensional electron gas (2DEG). A typical HEMT also includes at least two power electrodes. Current is conducted through the 2DEG between these two power electrodes.

The HEMT also includes a gate arrangement, which is operated to enable or suppress the 2DEG as desired, thereby enabling the device to be turned on or off. As a result, the HEMT can be operated like a field effect transistor (FET). In fact, such devices are sometimes referred to as heterojunction field effect transistors (HFETs).

Heterojunction power semiconductor devices of group III nitride based systems having high current carrying capacity and high breakdown voltage performance are suitable for power applications because of their low loss. However, many group III nitride semiconductor devices are normally ON devices, which means that biasing the gate is required to turn the device off.

Normally on devices are less desirable for power applications because: a) these devices operate less efficiently than normally off devices, and b) the drive circuits for the normally on devices are more complex and therefore more expensive. Because. It is therefore desirable to provide a normally off group III nitride power semiconductor device.

The AlGaN / GaN heterostructure is used as a high output field effect transistor. The AlGaN / GaN heterostructure uses a two-dimensional electron gas (2DEG) at the AlGaN / GaN interface to control the flow of the source-drain current through the gate voltage. This two-dimensional electron gas is generated due to a polarization phenomenon in which the opposite of the positive charge is generated below the AlGaN surface. This amount of charge is very sensitive to the surrounding environment, causing fluctuations in the source-drain current.

An object of the present invention for solving the above problems is an inefficient, complicated driving circuit generated by two-dimensional electron gas (2DEG) generated near the interface between nitride semiconductor layers having different band gaps, and high manufacturing cost. It is to provide a manufacturing method that can easily manufacture a normally off nitride power semiconductor device other than the normally on device.

A first aspect of the present invention for solving the above-mentioned problems is (a) forming a doped first nitride semiconductor layer on top of a substrate on which a buffer layer is formed; (b) forming a P-type or high resistive first nitride semiconductor layer over the doped layer; (c) forming a second nitride semiconductor layer over the P-type or high resistive first nitride semiconductor layer; (d) etching from the second nitride semiconductor layer in the gate region to a depth of the doped first nitride semiconductor layer; (e) forming a source electrode on the side of the second nitride semiconductor layer; (f) forming a gate insulating film over the second nitride semiconductor layer and the etched layer; (g) forming a gate electrode on the gate insulating film in the gate region; And (h) etching the lower portion of the substrate to a depth of the buffer layer to form a drain electrode.

Here, the step (a) may include forming a first nitride semiconductor layer doped with N ⁺ on the buffer layer; And the second the first nitride semiconductor layer may be a GaN layer, is preferable, and a step of forming a first nitride semiconductor layer doped with N ^_ the first nitride semiconductor layer above the doped to the N ⁺ The nitride semiconductor layer is preferably an AlGaN layer.

In addition, preferably, the first nitride semiconductor layer and the second nitride semiconductor layer may be formed by MOCVD, and the insulating layer may be Al ₂ O _3. , HfO ₂ And SiO ₂ It may be made of any one material, it may be to control the breakdown voltage by adjusting the thickness of the first nitride semiconductor layer doped with N ⁺ .

In addition, a second aspect of the present invention provides a method for manufacturing a semiconductor device, the method comprising: (a) forming a doped first nitride semiconductor layer over a substrate on which a buffer layer is formed; (b) forming a P-type or high resistive first nitride semiconductor layer over the doped layer; (c) forming a second nitride semiconductor layer over the P-type or high resistive first nitride semiconductor layer; (d) etching from the second nitride semiconductor layer in the gate region to a depth of the doped first nitride semiconductor layer; (e) forming a source electrode on the side of the second nitride semiconductor layer; (f) forming a gate insulating film over the second nitride semiconductor layer and the etched layer; (g) forming a gate electrode on the gate insulating film in the gate region; And (h) etching a side surface of the second nitride semiconductor layer to a predetermined depth to form a drain electrode.

Here, the step (a) may include forming a first nitride semiconductor layer doped with N ⁺ on the buffer layer; And the second the first nitride semiconductor layer may be a GaN layer, is preferable, and a step of forming a first nitride semiconductor layer doped with N ^_ the first nitride semiconductor layer above the doped to the N ⁺ The nitride semiconductor layer is preferably an AlGaN layer.

In addition, preferably, the first nitride semiconductor layer and the second nitride semiconductor layer may be formed by MOCVD, and the insulating layer may be Al ₂ O _3. , HfO ₂ And SiO ₂ It may be made of any one of the materials.

In addition, as a third aspect of the present invention, a nitride semiconductor device is manufactured by the method described above.

According to the present invention, by forming a recessed layer region by etching under the gate region to remove the heterojunction layer, the 2DEG is essentially blocked to easily remove the normally off enhancement element. It provides a way to implement it. In addition, the present invention can easily provide a semiconductor device having a simple driving circuit as an enhancement normally off power semiconductor device.

In addition, the distance to the drain is adjusted according to the depth of the thickness recessed region of the doped layer, thereby changing and improving breakdown voltage.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 (FIGS. 1A to 1E) is an embodiment according to the present invention, illustrating a manufacturing process of a normally-off nitride power semiconductor device, and FIG. 3 is a furnace according to an embodiment of the present invention. A flowchart of a manufacturing process of a far off nitride semiconductor device is illustrated and will be described below with reference to the following.

The process of the present invention generally includes forming a buffer layer 15 on a substrate 10; Forming a doped first nitride semiconductor layer on the substrate on which the buffer layer is formed (S100 and S200); Forming a P-type or high resistivity first nitride semiconductor layer on the doped layer (S300); Forming a second nitride semiconductor layer on the P-type or high resistive first nitride semiconductor layer (S400); Etching (S500) from the second nitride semiconductor layer in the gate region to a depth of the doped first nitride semiconductor layer; Forming a source electrode on a side of the second nitride semiconductor layer (S600); Forming a gate insulating layer on the second nitride semiconductor layer and the etched layer (S700); Forming a gate electrode on the gate insulating layer in the gate region (S800); And etching to the depth of the buffer layer below the substrate to form a drain electrode (S900).

 As shown in FIG. 1A, first, a buffer layer 15 made of AlN is formed as a buffer layer for lowering interfacial stress in order to grow a nitride semiconductor layer on a semiconductor substrate 10 such as Si and SiC. Of course, low temperature GaN layers are also possible. Then, a layer of gallium nitride (GaN) 30, which is a doped first nitride semiconductor, is grown on the buffer layer 15 using MOCVD or MBE (S200, S300).

The formation of the doping layer first forms a GaN layer of a predetermined depth, implants N ⁺ ions into the implantation or plasma doping equipment, and forms a heavy doping layer (low resistance) (S200). , again re-growth of the GaN layer by MOCVD and, N ^_ implanting ions again to form the low-concentration doped layers (lightly doping) (high resistance). (S300)

Here, the N-doped epitaxy GaN layers 23 and 25 are important in that they serve as a resistance which is one of on resistances. The role of the membrane is to maintain the blocking voltage, and the resistance of the membrane is directly related to the voltage rating of the device. High voltage MOSFETs require lightly doped (ie high resistance) thick films. Low-voltage transistors, on the other hand, require thin films with only heavy doped levels (ie low resistance). As a result, the resistance of the doped GaN layer is a major factor causing the resistance of high voltage MOSFETs. Therefore, the thickness doped structure of the doped layer is an important factor in determining the role of resistance to drift current and controlling the breakdown voltage.

After the N ^_ doping layer 25 is formed (S200), a P-type GaN layer or a high resistive GaN layer 27 is formed on the upper portion again by using the MOCVD method or the MBE method (S300). An AlGaN layer 30 that is a second nitride semiconductor layer is formed on the top (S300).

That is, as shown in FIG. 1A, the AlGaN layer 30 including aluminum, which is a second gallium nitride semiconductor layer 30 having different bandgaps, is heterogeneously formed on the highly resistive gallium nitride layer 27. Heterojunction. This is because a two-dimensional electron gas 35 (2DEG) is formed in a heterojunction of two semiconductor materials having different bandgap energies.

Here, the GaN layer 30 and the AlGaN layer 40 are preferably epitaxially grown using MOCVD. MOCVD is a method of forming a semiconductor thin film on a substrate 10 by gas pyrolysis of an organometallic compound and a hydrogen compound. As an epitaxial growth method, GaAs thin film was developed in 1968 and is applied to the growth of many semiconductors. In particular, in 1982, MOCVD was found to be unique to the synthesis of various low-dimensional nanostructures in addition to the three-dimensional epitaxy process. have.

The epitaxial growth of GaN using MOCVD is performed on the GaN buffer layer (AlN) on the silicon (Si) substrate 10 as described above to solve the lattice mismatch with the substrate 10 such as Si, SiC, sapphire, and the like. A two-stage growth method of growing (15) and growing the GaN epitaxial layer 30 thereon is used.

In the two-stage growth method, thermal etching is performed at the epitaxial growth temperature or higher (1100 ° C), and then the GaN buffer layer (AlN) 15 is grown at about 550 ° C. How to grow. As such, the MOCVD method has an advantage that the source of the reaction gas used in the thin film formation reaction is an organometallic precursor having a high partial pressure of the source at a low temperature and good decomposition. In addition, a highly purified source can be used to improve the properties of the growing thin film.

In addition, 2DEG 29 is an accumulation layer in the smaller, undoped bandgap material and may have a very high sheet electron concentration. Electrons from wider bandgap semiconductors also migrate to 2DEG 29 with high electron mobility because of the reduced scattering of ionized impurities.

This combination of high carrier concentrations and high carrier mobility can impart very large transconductances to HEMTs and can provide more powerful performance advantages over metal-semiconductor field effect transistors in high frequency applications.

However, while HEMT is a heterojunction power semiconductor device of group III nitride based system having high current carrying capacity and high breakdown voltage performance, due to its low loss, many group III nitride semiconductor devices are normal. It is a normally ON device, which is disadvantageous in terms of power since it must bias the gate to turn off the device. In order to improve the above, the present invention proposes a method of blocking the formation of the 2DEG 29 under the gate region.

Referring to FIG. 1B, as shown in FIG. 1A, a base layer for forming a nitride semiconductor element is formed, and a recess of a gate region is formed. In the AlGaN layer, which is the second nitride semiconductor layer, the N ⁺ doped layer 23 is formed. ) Etch to the top. Etching may be performed by wet etching, dry etching, or etching using an exposure apparatus. The etching to the N ⁺ doped layer 23 of the first nitride semiconductor layer in the gate region is a two-dimensional electron gas (2DEG) formed by heterojunction between the undoped GaN layer 27 and the AlGaN layer 30. This is to form a normally off semiconductor device by blocking the (29) is formed in the lower portion of the gate region.

That is, since the 2DEG 29 is caused by polarization between the GaN layer 27 and the AlGaN layer 30 interface, which are heterojunctions having different band gaps, the 2DEG 29 is formed on top of the GaN layer that is the first nitride semiconductor layer 27. Etching to the top of the N ⁺ highly doped layer 23 under the gate region portion of the AlGaN layer 30, the epitaxially grown second nitride semiconductor layer, essentially blocks the formation of the 2DEG 29. (S500) In this way, the interface The 2DEG 29 formed near the interface is formed only under the source electrode 50 region and is not formed under the gate electrode 40 region, thereby forming a semiconductor device having a normally off. It becomes possible.

In addition, it is possible to adjust the threshold voltage according to the depth of the high-resistance GaN layer 27 that is the first nitride semiconductor layer is etched and recessed. That is, the present invention has the advantage that the threshold voltage is easily controlled in the nitride semiconductor through the above-described structure, and the customized design is easy.

The gate region is recessed and source electrodes 50 are formed on both sides of the device. The material of the source electrode is metal or alloy, and any material having high conductivity and easy for ohmic bonding can be used. For example, it is preferable to form Ta / Ti / Al / Ni / Au as a material (see Fig. 1C).

After the source electrode is formed, as shown in FIG. 1D, the gate insulating layer 35 is formed in the etched and recessed portion of the gate region, and is formed again on the gate electrode 40. The gate insulating layer 35 is a structure for controlling a source / drain current with a voltage applied to the gate electrode 40 by forming one capacitor as a dielectric layer between the gate electrode 40 and the nitride semiconductor layer.

That is, an insulating film 35 is formed over the AlGaN layer 30 and the recess region etched to insulate the channel region GaN layer portion and the gate electrode 50 (metal) material for applying the bias. S700) wherein the insulating layer 35 is Al ₂ O ₃ , SiO _{2 ,} HfO ₂ Although it is preferable that it is either, etc., if it is a thin film which is easy to form a thin film and is highly insulating, of course, it can be used with what kind of material. In this case, the characteristics of the device vary according to the thickness and dielectric constant of the insulating layer 35, and as the thickness and dielectric constant are higher, gate leakage increases and a higher voltage may be applied to the gate electrode 40.

Then, as shown in FIG. 1E, the substrate 10 is etched upward from the lower surface of the substrate corresponding to the gate region to form the drain electrode 60. The drain electrode 60 is also formed by an ohmic junction, and can be formed of a metal or an alloy having high conductivity.

In general, the source / drain electrodes 50 and 60 in the FET device use an alloy for ohmic contact between the AlGaN layer 30 and the buffer layer 15, which is a difference in the work function of both metals in contact. Because it reduces.

Ohmic contact refers to an ohmic contact having a small contact resistance between the electrode metal and the semiconductor so that the electrode metal does not significantly affect the characteristics of the device when the metal wire is drawn from the semiconductor device. However, in general, when a metal is brought into contact with a semiconductor having a low impurity concentration, a good ohmic contact cannot be expected because a potential barrier is formed on the contact surface. In principle, the height of the potential barrier is determined by the difference in the work function between the metal and the semiconductor. Therefore, by selecting the appropriate metal, it is necessary to prevent the formation of the potential barrier for the carrier (conducting electrons or holes in the state of movement in the semiconductor).

When the work function of the metal is fm and the work function of the semiconductor is fs, a combination of fm <fs for n-type semiconductors and fm> fs for p-type semiconductors does not create a potential barrier to carriers. In the present invention, by forming an ion doped layer having a predetermined depth under the interface, the potential barrier between the semiconductor AlGaN and the metal can be lowered, thereby reducing the difference in work function, thereby enabling ohmic contact.

As described above, the present invention is a vertical diffusion FET device, which is formed by etching a gate of the gate region to a depth of a heavily doped first nitride semiconductor layer, and forming a gate insulating film in the recessed portion, By forming the gate electrode, the portion in contact with the second nitride semiconductor layer (AlGaN) is essentially blocked, and when 2DEG is biased in the channel region formed along the gate insulating film, current can flow vertically to the drain electrode. As a structure of the present invention, there is provided a method capable of easily forming a normally off nitride semiconductor element which is efficiently efficient by a simple manufacturing method.

2 is a view illustrating a configuration of a normally off nitride semiconductor device as another embodiment according to the present invention. As shown in FIG. 2, the present embodiment is manufactured through the same process as the manufacturing process of FIG. 1, but the drain electrode 60 is not back-etched on the lower portion of the substrate 10, but the upper source. A side surface of the electrode 50 is etched to a predetermined depth in the highly doped first nitride semiconductor layer 23 to form a source electrode.

The fabrication of such a structure is different in that the processes of FIGS. 1A to 1D are the same, and the drain electrode is formed by lateral etching in the process of FIG. 1E.

Thus, the structure of the embodiment of the present invention forms a normally off MOSFET by varying the depth of the gate electrode, the thickness and material of the gate insulating layer 35, the thickness and composition ratio of the AlGaN layer 30, and the like. The gate length is determined according to the thickness of the P-type or high-resistance GaN layer 27, and the distance from the drain 60 can be adjusted according to the thickness of the N ^_ doped (low concentration doped) GaN layer. There is an advantage to change and improve the breakdown voltage.

Here, in the case of a silicon (Si) substrate, the back side etching (see FIG. 1E) is possible, so that the drain electrode may be easily formed on the back side of the substrate, but in the case of the sapphire substrate, the side surface etching is not easy. It is preferable to form a drain electrode by lateral etching.

The steps of the process of the present invention are not limited to those in a complete time series order, but the invention is easily described according to the order of application to a general semiconductor high process, and the process order of the invention can be changed or modified as necessary. Of course. In addition, the nitride semiconductor refers to various semiconductors including nitride, and is not limited to the semiconductor applied in the above embodiment.

While the invention has been shown and described with respect to the specific embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined by the appended claims. Anyone with it will know easily.

FIG. 1 (FIGS. 1A to 1E) is a diagram illustrating a manufacturing process of a normally-off nitride power semiconductor device as an embodiment according to the present invention.

2 is a diagram illustrating a configuration of a normally off nitride semiconductor device as another embodiment according to the present invention.

3 is a flowchart illustrating a manufacturing process of a normally off nitride semiconductor device according to an exemplary embodiment of the present invention.

<Detailed Description of Main Parts of Drawing>

10: substrate, 15: buffer layer, 23: N ⁺ doped layer, 25: N ^_ doped layer, 30: high resistivity GaN layer

35: gate insulating film, 40: gate electrode, 50: source electrode: 60: drain electrode

Claims (12)

(a) forming a doped first nitride semiconductor layer over the substrate on which the buffer layer is formed; (b) forming a P-type or high resistive first nitride semiconductor layer over the doped layer; (c) forming a second nitride semiconductor layer over the P-type or high resistive first nitride semiconductor layer; (d) etching from the second nitride semiconductor layer in the gate region to a depth of the doped first nitride semiconductor layer; (e) forming a source electrode on the side of the second nitride semiconductor layer; (f) forming a gate insulating film over the second nitride semiconductor layer and the etched layer; (g) forming a gate electrode on the gate insulating film in the gate region; And (h) forming a drain electrode by etching the lower portion of the substrate to a depth of the buffer layer. The method of claim 1, Step (a) may include forming a first nitride semiconductor layer doped with N ⁺ on the buffer layer; And And forming an N ^_ doped first nitride semiconductor layer over the N ⁺ doped first nitride semiconductor layer. The method according to claim 1 or 2, And the first nitride semiconductor layer is a GaN layer, and the second nitride semiconductor layer is an AlGaN layer. The method of claim 3, wherein And the first nitride semiconductor layer and the second nitride semiconductor layer are formed by MOCVD. The method according to claim 1 or 2, The insulating film is Al ₂ O ₃ , HfO ₂ And SiO ₂ Nitride semiconductor device manufacturing method characterized in that any one of the material. The method of claim 2, A method of manufacturing a nitride semiconductor device comprising controlling a breakdown voltage by adjusting a thickness of the first nitride semiconductor layer doped with N ⁺ . (a) forming a doped first nitride semiconductor layer over the substrate on which the buffer layer is formed; (b) forming a P-type or high resistive first nitride semiconductor layer over the doped layer; (c) forming a second nitride semiconductor layer over the P-type or high resistive first nitride semiconductor layer; (d) etching from the second nitride semiconductor layer in the gate region to a depth of the doped first nitride semiconductor layer; (e) forming a source electrode on the side of the second nitride semiconductor layer; (f) forming a gate insulating film over the second nitride semiconductor layer and the etched layer; (g) forming a gate electrode on the gate insulating film in the gate region; And (h) forming a drain electrode by etching a side surface of the second nitride semiconductor layer to a predetermined depth of the doped layer. The method of claim 7, wherein Step (a) may include forming a first nitride semiconductor layer doped with N ⁺ on the buffer layer; And And forming an N ^_ doped first nitride semiconductor layer over the N ⁺ doped first nitride semiconductor layer. 9. The method according to claim 7 or 8, And the first nitride semiconductor layer is a GaN layer, and the second nitride semiconductor layer is an AlGaN layer. 10. The method of claim 9, And the first nitride semiconductor layer and the second nitride semiconductor layer are formed by MOCVD. 9. The method according to claim 7 or 8, The insulating film is Al ₂ O ₃ , HfO ₂ And SiO ₂ A method of manufacturing a vertical nitride semiconductor device, characterized in that any one of the materials. A normally-off vertical nitride semiconductor device, which is produced by the method of claim 1.

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