JP6233088B2 - Field effect transistor - Google Patents

Description

  The present disclosure relates to a semiconductor element used for high current / high withstand voltage applications.

  Group III nitride semiconductors have a larger band gap and dielectric breakdown field than conventional semiconductors such as silicon (Si), and are promising as materials for high-current / high-voltage heterojunction field effect transistors (HFETs). It is.

In order to further increase the current, a heterojunction interface exemplified by an aluminum gallium nitride (Al _x Ga _1-x N (0 ≦ x ≦ 1)) electron barrier layer and a gallium nitride (GaN) channel layer is used. It is expected to further increase the carrier density of the generated two-dimensional electron gas (2DEG: Two Dimensional Electron Gas). For example, the carrier density can be increased by increasing the spontaneous polarization of the electron barrier layer.

Therefore, indium aluminum gallium nitride (In _x Al _y Ga _{1 -xy} N (0 ≦ x ≦ 1, which can be lattice-matched with GaN and can have a spontaneous polarization larger than that when AlGaN is used by adjusting the composition). 0.ltoreq.y.ltoreq.1, 0.ltoreq.x + y.ltoreq.1)) is used as an electron barrier layer of a group III nitride HFET (Patent Document 1).

Hereinafter, unless otherwise specified, In _x Ga _1-x N (0 <x <1) that is a ternary mixed crystal is InGaN, Al _y Ga _1-y N (0 <y <1) is AlGaN, In _z Al _1-z N a (0 <z <1) abbreviated as InAlN, a quaternary mixed crystal _{in x Al y Ga 1-xy} N (0 <x <1,0 <y <1,0 <x + y <1) is abbreviated as InAlGaN.

JP 2007-158143 A

  However, when the InAlGaN electron barrier layer is used, there is a problem that the leakage current is remarkably increased and the off breakdown voltage is reduced as compared with the case where the AlGaN electron barrier layer is used. Even if the increase in carrier density due to the use of the InAlGaN layer is taken into account, the off breakdown voltage is very low. Therefore, the crystallinity of the InAlGaN layer is deteriorated, so that the electron barrier layer is n-type. Presumed to be the main cause.

  At the time of crystal growth of the InAlGaN electron barrier layer, it is necessary to lower the crystal growth temperature by about 100 ° C. than that of the AlGaN electron barrier layer in order to easily incorporate In having a high vapor pressure. However, when the crystal growth temperature is low, atoms constituting the group III nitride semiconductor do not migrate sufficiently on the crystal surface, and thus crystal defects are likely to be generated. In this case, it is considered that nitrogen vacancies are formed among the crystal defects. Since the nitrogen vacancy functions as a donor in the group III nitride semiconductor, the crystal becomes n-type without doping.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a group III field effect transistor having a large current, a high off breakdown voltage, and a small gate leakage current.

  In order to solve the above problems, a field effect transistor of the present invention includes a substrate, a channel layer made of a first nitride semiconductor, disposed on the substrate, and an electron supply layer formed on the channel layer. A source electrode, a gate electrode and a drain electrode formed on the electron supply layer, wherein the electron supply layer is a layer made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor. And a third nitride semiconductor layer containing In and having a larger band gap than the first nitride semiconductor, formed on the second nitride semiconductor layer. In the third nitride semiconductor layer, an acceptor impurity is added to compensate the donor.

  With this configuration, the third nitride semiconductor layer contains In, and acceptor impurities are added to compensate the donor, thereby increasing the off breakdown voltage and reducing the leakage current.

  In the field effect transistor of the present invention, it is preferable that the second second nitride semiconductor further contains In. According to this preferable configuration, more carriers due to spontaneous polarization can be supplied to the channel layer below the channel layer, and more current can flow.

  In the field effect transistor of the present invention, it is preferable that the second nitride semiconductor layer and the third nitride semiconductor layer have the same composition. According to this preferable configuration, both the off breakdown voltage and the increase in current can be achieved.

  In the field effect transistor of the present invention, the impurity concentration of the layer made of the third nitride semiconductor is preferably larger than the impurity concentration of the layer made of the second nitride semiconductor.

  In the field effect transistor of the present invention, the electron supply layer is further closer to the channel layer than the layer made of the second nitride semiconductor, than the fourth nitride semiconductor having a band gap larger than that of the second nitride semiconductor. It is preferable to have a layer.

  In the field effect transistor of the present invention, the band gap of the fourth nitride semiconductor is preferably larger than the band gap of the third nitride semiconductor.

  In the field effect transistor of the present invention, the electron supply layer further includes a fifth nitride semiconductor layer disposed between the second nitride semiconductor layer and the fourth nitride semiconductor layer. The band gap of the fifth nitride semiconductor is preferably smaller than the band gap of the fourth nitride semiconductor.

  In the field effect transistor of the present invention, the In composition of the layer made of the fifth nitride semiconductor is preferably smaller than the In composition of the layer made of the second nitride semiconductor. According to this preferable configuration, InAlGaN alloy scattering is suppressed, and sheet resistance can be reduced by improving mobility.

In the field effect transistor of the present invention, the acceptor impurity concentration of the layer made of the third nitride semiconductor is preferably 5 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less. According to this preferable configuration, the donor of the layer made of the third nitride semiconductor can be sufficiently compensated.

  In the field effect transistor of the present invention, the electron supply layer is further provided with a recessed portion that reaches from the third nitride semiconductor layer to the fourth nitride semiconductor layer, and a gate electrode is formed at the bottom of the recessed portion. It is preferred that According to this preferable configuration, the threshold voltage of the field effect transistor can be controlled.

  The field effect transistor of the present invention preferably further includes an insulating layer between the channel layer and the gate electrode. According to this preferable configuration, the gate leakage current can be reduced, a large current and an off breakdown voltage can be increased.

  According to the field effect transistor according to the present invention, the donor impurity in the electron supply layer is compensated, whereby a field effect transistor having a large current and a high off breakdown voltage can be realized.

The top view of the field effect transistor which concerns on the 1st Embodiment of this invention Sectional view of the field effect transistor according to the first embodiment Diagram showing the correlation of the gate-drain distance or off-voltage when doped with Mg to _{In x Al y Ga 1-xy} N electron barrier layer of the field effect transistor Shows a drain current-drain voltage characteristic when doped with Mg to _{In x Al y Ga 1-xy} N electron barrier layer of the field effect transistor Shows a drain current-drain voltage characteristic when doped with Mg to _{In x Al y Ga 1-xy} N electron barrier layer of the field effect transistor The top view of the field effect transistor concerning the 2nd Embodiment of this invention Sectional drawing of the field effect transistor which concerns on the said 2nd Embodiment Top view of a field effect transistor according to a third embodiment of the present invention Sectional drawing of the field effect transistor which concerns on the said 3rd Embodiment Top view of a field effect transistor according to a fourth embodiment of the invention Sectional drawing of the field effect transistor which concerns on the same 4th Embodiment Top view of a field effect transistor according to a fifth embodiment of the invention Sectional drawing of the field effect transistor which concerns on the same 5th Embodiment Top view of a field effect transistor according to a fifth embodiment of the invention Sectional drawing of the field effect transistor which concerns on the same 5th Embodiment

  Embodiments of the present invention will be described below with reference to the drawings.

(First embodiment)
The field effect transistor according to the first embodiment will be described below together with the manufacturing method. FIG. 1 is a top view of the field effect transistor according to the first embodiment, and FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG.

First, by MOCVD, a channel layer 102 made of, for example, GaN having a film thickness of 2 μm and a first layer made of, for example, AlN having a film thickness of 1 nm are formed on the main surface of the substrate 101 made of Si having a surface orientation of (111). One electron barrier layer 103, a second electron barrier layer 104 made of, for example, Al _0.30 Ga _0.70 N having a thickness of 10 nm, a third electron barrier layer 105 made of, for example, In _0.18 Al _0.82 N, having a thickness of 7.5 nm, and Mg A fourth electron barrier layer 106 made of, for example, In _0.18 Al _0.82 N having a doped film thickness of 7.5 nm is sequentially grown. An electron supply layer is formed by the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106. Next, an ion implantation portion 107 is formed by implanting, for example, B ions after resist patterning. Next, a source electrode 108 and a drain electrode 109 made of, for example, Ti / Al (20 nm / 200 nm) are sequentially formed on the fourth electron barrier layer 106. Next, the gate electrode 110 made of, for example, Ni / Au (film thickness 100 nm / 500 nm) is formed.

Here, the Mg concentration of the fourth electron barrier layer 106 is 5 × 10 ¹⁸ cm ^−3, which is a concentration that sufficiently self-compensates the donor in the fourth electron barrier layer 106. The Mg concentration was measured by secondary ion mass spectrometry (SIMS).

When the Mg concentration of the fourth electron barrier layer 106 is 5 × 10 ¹⁸ cm ⁻³ , the donor in the fourth electron barrier layer 106 is sufficiently self-compensated for the following reason.

That is, the fourth electron barrier layer 106 is made of InAlGaN and becomes n-type when Mg is not added, and has a carrier concentration of about 10 ¹⁷ cm ⁻³ to 10 ¹⁸ cm ⁻³ . On the other hand, in the case of GaN, for example, when the Mg concentration is 5 × 10 ¹⁸ cm ⁻³ , the p-type carrier concentration is 8 × 10 ¹⁷ cm ⁻³ . That is, when Mg having a concentration of 5 × 10 ¹⁸ cm ⁻³ is added to the fourth electron barrier layer 106, p-type carriers of about 8 × 10 ¹⁷ cm ⁻³ are generated. The p-type carrier and the n-type carrier generated when Mg is not added cancel each other. In this way, the donor in the fourth electron barrier layer 106 is sufficiently self-compensated.

  The source electrode 108 and the drain electrode 109 are in ohmic conduction with the channel layer 102, and the gate electrode 110 makes a Schottky contact with the fourth electron barrier layer 106. The source electrode 108 and the drain electrode 109 are in ohmic conduction with the channel layer 102 because the first electron barrier layer 103, the second electron barrier layer 104, and the third electron barrier layer 105 are n-type, and the fourth electron barrier This is because the layer 106 is thin.

  The plane orientations of the main surfaces of the channel layer 102, the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106 are the (0001) plane (c-plane). .

  The layer structure of the field effect transistor according to the present invention manufactured as described above is as shown in Table 1 below.

  In the field effect transistor of the present invention, the longitudinal direction of the gate electrode 110 is the <11-20> direction. Therefore, the direction connecting the source electrode 108 and the gate electrode 110 is the <1-100> direction. The gate length (the width along the <1-100> direction of the gate electrode 110) is 2 μm, the distance between the opposite ends of the source electrode 108 and the gate electrode 110 is 1.5 μm, and the drain electrode 109 and the gate The distance between the electrodes opposite to the electrode 110 is 10 μm. The element size of the field effect transistor is 250 μm in the <11-20> direction and 250 μm in the <1-100> direction. The ion implantation part 107 is provided up to a position of 20 μm from the end of the field effect transistor.

  Note that the critical film thickness of InAlGaN lattice-matched with GaN should theoretically be infinite, but in reality, when the film thickness is 50 nm or more, the crystallinity is drastically lowered.

  Here, when the film thickness is d and the ratio Δa / a of the lattice constant a between the substrate and the epitaxial film and the lattice constant a of the substrate is defined as the degree of lattice mismatch, in order to obtain a good crystal without cracks,

It was experimentally confirmed that a lattice mismatch degree satisfying the above condition is preferable. Furthermore, among these conditions, the total thickness of the third electron barrier layer 105 and the fourth electron barrier layer 106 is particularly preferably 50 nm or less.

  The characteristics of the field transistor according to the first embodiment will be described below.

As the field effect transistor examined here, the third electron barrier layer 105 and the fourth electron barrier layer 106 are both undoped (sample A), and the third electron barrier layer 105 and the fourth electron barrier layer 106 have one in them. Similarly, there are three types: a sample doped with Mg (sample B), a sample in which the third electron barrier layer 105 is undoped, and a sample in which the fourth electron barrier layer 106 is doped with Mg (sample C). The Mg concentration of the doped layers in Sample B and Sample C is 5 × 10 ¹⁸ cm ^−3, which is a concentration that sufficiently self-compensates the donor in the layer.

  Table 2 shows the relationship between the presence or absence of Mg doping in the third electron barrier layer 105 and the fourth electron barrier layer 106 and the Mg concentration of the examined samples.

(1) Off-breakdown voltage characteristics First, with respect to the samples A to C, the distance between the gate electrode 110 and the drain electrode 109 was used as a parameter, and a voltage was applied to the gate electrode 110 to measure the off-breakdown voltage. Here, the off breakdown voltage refers to a breakdown voltage between the source and the rain in a state where the gate voltage of the field effect transistor is equal to or lower than a threshold voltage (that is, an off state). As a result, the result shown in FIG. 3 was obtained. FIG. 3 shows that the off breakdown voltage of sample B and sample C is improved as compared with sample A. Table 3 shows the off breakdown voltage when the distance between the gate electrode 110 and the drain electrode 109 is 10 μm.

  From Table 3, the off breakdown voltage of sample A in which Mg is not doped in the fourth electron barrier layer 106 is 60V, and the off breakdown voltages of sample B and sample C in which the fourth electron barrier layer 106 is doped with Mg are both 400V. I found out that From this, it was found that doping the fourth electron barrier layer 106 with Mg dramatically improved the off breakdown voltage from about 60V to over 400V.

  The improvement of the off breakdown voltage will be described below.

  During the crystal growth of the third electron barrier layer 105 and the fourth electron barrier layer 106, in order to facilitate the incorporation of In having a high vapor pressure, the third electron barrier layer 105 and the fourth electron barrier layer 106 are 100 ° C. than when AlGaN is used. It is necessary to lower the crystal growth temperature to a certain extent. However, when the crystal growth temperature is low, atoms constituting the group III nitride semiconductor do not migrate sufficiently on the crystal surface, and thus crystal defects are likely to be generated. In this case, it is considered that nitrogen vacancies are formed among the crystal defects. Since the nitrogen vacancy functions as a donor in the group III nitride semiconductor, the crystal becomes n-type without doping.

  Therefore, when InAlGaN is used for the third electron barrier layer 105 and the fourth electron barrier layer 106, it is considered that the leakage current increases and the avalanche breakdown is likely to occur, so that the off breakdown voltage is reduced.

  Therefore, the inventors of the present application generated holes by doping Mg into the third electron barrier layer 105 and the fourth electron barrier layer 106 of InAlGaN, and self-compensated the electrons generated by the nitrogen vacancies by the holes. I tried to make it. As a result, it was found that the leakage current is reduced and the off breakdown voltage is improved.

  As a result, the distance between the gate electrode 110 and the drain electrode 109 was 10 μm and the off breakdown voltage was only 60V, which was improved to 400V.

In addition, it turned out that the 4th electron barrier layer 106 becomes a high resistance or a semi-insulation from the improvement of an off-breakdown pressure | voltage.
(2) Id-Vd Characteristics Next, drain current / drain voltage characteristics (hereinafter referred to as Id-Vd characteristics) regarding Sample A, Sample B, and Sample C will be described.

  First, the Id-Vd characteristics of Sample A and Sample B are shown in FIG. In FIG. 4, the horizontal axis represents the drain voltage (unit: V), the vertical axis represents the drain current (unit: A / mm), graph A is a graph related to sample A, and graph B is a graph related to sample B. The gate voltage is changed in a 1V step between -2V to 6V for each graph.

  When Mg which sufficiently self-compensates electrons as in Sample B is doped into the third electron barrier layer 105 and the fourth electron barrier layer 106, it is remarkably maximum as compared with the case where Mg is not doped (Sample A). The drain current decreased. This is presumably due to an increase in sheet resistance due to a significant decrease in electron mobility due to an increase in impurity scattering accompanying Mg doping.

  Next, the drain current drain voltage characteristics of the sample B and the sample C were examined, and the results are shown in FIG. In FIG. 5, the horizontal axis is the drain voltage (unit is V), the vertical axis is the drain current (unit is A / mm), the graph B is a graph regarding the sample B, and the graph C is a graph regarding the sample C. The gate voltage is changed in a 1V step between -2V to 6V for each graph. From FIG. 4, the drain current drain voltage characteristic sample B was significantly reduced in current, while sample C had a drain current equivalent to that of sample A.

  As described above, according to the present embodiment, it has been found that the off-breakdown voltage is dramatically improved and a large-current field effect transistor can be realized.

If the Mg concentration is 5 × 10 ¹⁷ cm ⁻³ or more and 5 × 10 ²⁰ cm ⁻³ or less, particularly if the Mg concentration is 5 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ , the fourth electron barrier layer. In 106, the donor in the layer can be sufficiently self-compensated to obtain a suitable fourth electron barrier layer 106.

  In the above embodiment, the composition of the third electron barrier layer and the composition of the fourth electron barrier layer are equal, but the composition of the third electron barrier layer and the composition of the fourth electron barrier layer are not necessarily equal. It does not have to be.

  In the case where the gate electrode 110 is formed on the fourth electron barrier layer 106, it is easy to concentrate the electric field on the end portion of the gate electrode 110, and therefore it is preferable to particularly increase the off breakdown voltage of the fourth electron barrier layer 106. .

  In general, when Mg is excessively doped by increasing the In composition of InAlGaN, Mg does not fit in the lattice position where it acts as an acceptor, and it also acts as a donor. Therefore, the In composition of the fourth electron barrier layer 106 Is preferably lower for the purpose of improving the off breakdown voltage.

  However, when the In composition of the fourth electron barrier layer 106 is lowered, a trade-off occurs in which the current decreases. Therefore, when it is desired to achieve both off breakdown voltage and large current, the composition of the fourth electron barrier layer 106 is The same composition as the third electron barrier layer 105 is preferable.

  Further, since InAlGaN is a quaternary mixed crystal composed of In, Al, Ga, and N, the lower the mobility due to alloy scattering, the higher the In composition. Therefore, the band gap between the second electron barrier layer 104 and the third electron barrier layer 105 is smaller than that of the second electron barrier layer 104 and the third electron barrier layer 105, and is smaller than that of the third electron barrier layer 105. A nitride semiconductor layer having a small composition may be inserted. Thereby, the alloy scattering of InAlGaN is suppressed, and the sheet resistance can be reduced by improving the mobility.

(Second Embodiment)
The field effect transistor according to the second embodiment will be described below together with the manufacturing method. FIG. 6 is a top view of the field effect transistor according to the second embodiment, and FIG. 7 is a cross-sectional view taken along the line AA ′ of FIG. 6 and FIG. 7, the same elements as those in FIG. 2 and FIG. Similarly to the first embodiment, the channel layer 102, the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106 are sequentially formed on the substrate 101 by MOCVD. Deposit. Next, an ion implantation portion 107 is formed by implanting, for example, B ions after resist patterning. Next, the recess 201 is formed by dry etching after resist patterning. The bottom surface of the recess portion 201 reaches the first electron barrier layer 103 or the second electron barrier layer 104 so that the threshold voltage does not become excessively negative. In the present embodiment, the recess portion 201 is formed so as to reach the upper surface of the first electron barrier layer 103.

  For the recess portion 201, the recess width (the width along the <1-100> direction) is 1 μm. Other parameters relating to the field effect transistor are the same as those in the first embodiment.

  Next, the source electrode 108 and the drain electrode 109 are sequentially formed on the fourth electron barrier layer 106. Next, the gate electrode 110 is formed on the recess portion 201.

  As the field effect transistor examined here, a sample with the recess portion 201 is referred to as a sample D, and a sample without the recess portion 201 is referred to as a sample E. When the threshold voltage was examined for sample D and sample E, it was as shown in Table 4.

  In the case of sample E without the recess portion 201, the carrier density under the gate electrode 110 was very high and the threshold voltage was −15 V or less. However, in the case of the sample D having the recess portion 201, the threshold was set. The value voltage can be about -3V.

  As described above, according to the present embodiment, it is possible to realize a large-current field effect transistor in which the off breakdown voltage is dramatically improved and the threshold voltage is controlled to about −3V.

  Note that the threshold voltage of the bottom surface of the recess portion 201 shifts more positively as the first electron barrier layer 103 is thinner. However, when the recess portion 201 is formed so that the thickness of the first electron barrier layer 103 is reduced, the third electron barrier layer 105 is made n-type by forming nitrogen vacancies. Since contact with the layer 105 causes an increase in leakage current, for example, by increasing the resistance by ion implantation or the like in the portion where the gate electrode 110 of the third electron barrier layer 105 is in contact, or forming an insulating layer, It is preferable to reduce the gate leakage current.

(Third embodiment)
The nitride semiconductor device according to the third embodiment will be described below together with the manufacturing method. FIG. 8 is a top view of a field effect transistor according to the third embodiment, and FIG. 9 is a cross-sectional view taken along the line AA ′ of FIG. 8 and 9, the same elements as those in FIGS. 2 and 3 are denoted by the same reference numerals, and the description thereof is omitted. Similarly to the first embodiment, the channel layer 102, the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106 are sequentially formed on the substrate 101 by MOCVD. Deposit. Next, an ion implantation portion 107 is formed by implanting, for example, B ions after resist patterning. Next, a recess portion 201 is formed by dry etching after resist patterning, and a source electrode 108 and a drain electrode 109 are formed on the fourth electron barrier layer 106, and a gate electrode 110 is formed on the recess portion 201. In the second embodiment, the gate electrode is in contact with the third electron barrier layer 105 and the fourth electron barrier layer 106. However, in this embodiment, as shown in FIG. The gate electrode 110 is not in contact with the third electron barrier layer 105 and the fourth electron barrier layer 106. In the present embodiment, the recess portion 201 is formed so as to reach the upper surface of the first electron barrier layer 103.

  For the recess portion 201, the recess width (the width along the <1-100> direction) is 1 μm. Other parameters relating to the field effect transistor are the same as those in the first embodiment.

  The third electron barrier layer 105 contains In and has many nitrogen vacancies. Therefore, the gate leakage current can be suppressed by separating the third electron barrier layer 105 and the gate electrode 110. In the field effect transistor according to the third embodiment, the threshold voltage can be set to about −3 V by including the recess portion 201 as in the case of the second embodiment.

  As described above, according to the present embodiment, it is possible to realize a large-current field effect transistor in which the off breakdown voltage is dramatically improved and the threshold voltage is controlled to about −3V.

(Fourth embodiment)
The nitride semiconductor device according to the fourth embodiment will be described below together with the manufacturing method. FIG. 10 is a top view of a field effect transistor according to the fourth embodiment, and FIG. 11 is a cross-sectional view taken along the line AA ′ of FIG. 10 and FIG. 11, the same elements as those in FIG. 2 and FIG.

  Similarly to the first embodiment, the channel layer 102, the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106 are formed on the substrate 101 by MOCVD. Deposit sequentially. Next, an ion implantation portion 107 is formed by implanting, for example, B ions after resist patterning. Next, an insulating film 202 made of, for example, SiN having a thickness of 100 nm is formed so as to cover the fourth electron barrier layer 106. Next, an ohmic window 203 is formed on the fourth electron barrier layer 106 by resist patterning. Next, the source electrode 108 and the drain electrode 109 are formed on the ohmic window 203. Next, the gate electrode 110 is formed on the recess portion 201 and the insulating film 202.

  In the present embodiment, the recess portion 201 is formed so as to reach the upper surface of the first electron barrier layer 103.

  For the recess portion 201, the recess width (the width along the <1-100> direction) is 1 μm. Other parameters relating to the field effect transistor are the same as those in the first embodiment.

  In the field effect transistor according to the third embodiment manufactured as described above, the gate leakage current is suppressed by the insulating film 202.

  As described above, according to the present embodiment, it is possible to realize a field effect transistor having a large off-breakdown voltage and a large current / low gate leakage current.

(Fifth embodiment)
A nitride semiconductor device according to the fifth embodiment will be described below together with a manufacturing method. FIG. 12 is a top view of a field effect transistor according to the fifth embodiment, and FIG. 13 is a cross-sectional view taken along the line AA ′ of FIG. 12 and 13, the same elements as those in FIGS. 2 and 3 are given the same reference numerals and description thereof is omitted.

  Similarly to the first embodiment, the channel layer 102, the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106 are formed on the substrate 101 by MOCVD. Deposit sequentially. Next, an ion implantation portion 107 is formed by implanting, for example, B ions after resist patterning. Next, the recess portion 201 is formed by dry etching after resist patterning. Next, an insulating film 202 made of, for example, SiN is formed so as to cover the recess portion 201 and the fourth electron barrier layer 106. Next, an ohmic window 203 is formed on the fourth electron barrier layer 106 by resist patterning. Next, the source electrode 108 and the drain electrode 109 are formed on the ohmic window 203. Next, the gate electrode 110 is formed on the recess portion 201 and the insulating film 202.

  In the present embodiment, the recess portion 201 is formed so as to reach the upper surface of the first electron barrier layer 103.

  For the recess portion 201, the recess width (the width along the <1-100> direction) is 1 μm. Other parameters relating to the field effect transistor are the same as those in the first embodiment.

  Since the gate leakage current is suppressed by the insulating film 202 and the recess portion 201 is provided, the threshold voltage can be shifted more positively than the field effect transistor of the fourth embodiment.

  As described above, according to the present embodiment, it is possible to realize a field effect transistor having a large current and a low gate leakage current while controlling the threshold voltage and dramatically improving the off breakdown voltage.

(Sixth embodiment)
The nitride semiconductor device according to the sixth embodiment will be described below together with the manufacturing method. FIG. 14 is a top view of a field effect transistor according to the sixth embodiment, and FIG. 15 is a cross-sectional view taken along the line AA ′ of FIG. 14 and FIG. 15, the same elements as those in FIG. 2 and FIG.

  Similarly to the first embodiment, the channel layer 102, the first electron barrier layer 103, the second electron barrier layer 104, the third electron barrier layer 105, and the fourth electron barrier layer 106 are formed on the substrate 101 by MOCVD. Deposit sequentially. Next, an ion implantation portion 107 is formed by implanting, for example, B ions after resist patterning. Next, the recess portion 201 is formed by dry etching after resist patterning. Next, an insulating film 202 made of, for example, SiN is formed so as to cover the recess portion 201 and the fourth electron barrier layer 106. Next, an ohmic window 203 is formed on the fourth electron barrier layer 106 by resist patterning. Next, the source electrode 108 and the drain electrode 109 are formed on the ohmic window 203. Next, the gate electrode 110 is formed on the recess portion 201 and the insulating film 202. In the fifth embodiment, the side surface of the gate electrode 110 and the insulating film 202 are in contact with each other. However, in this embodiment, the width of the recess portion 201 is larger than the width of the gate electrode 110 as shown in FIG. In general, the side surface of the gate electrode 110 and the insulating film 202 are not in contact with each other.

  In the present embodiment, the recess portion 201 is formed so as to reach the upper surface of the first electron barrier layer 103.

  For the recess portion 201, the recess width (the width along the <1-100> direction) is 1 μm. Other parameters relating to the field effect transistor are the same as those in the first embodiment.

  In the field effect transistor according to the present embodiment, the electrons generated in the third electron barrier layer 105 do not tunnel through the insulating film 202 and reach the gate electrode 110, and the field effect according to the fifth embodiment is achieved. The gate leakage current can be further suppressed than the transistor. Further, by including the recess portion 201 as in the fifth embodiment, the threshold voltage can be shifted more positively than in the field effect transistor according to the fourth embodiment.

  As described above, according to the present embodiment, it is possible to realize a field effect transistor having a large current and a low gate leakage current while controlling the threshold voltage and dramatically improving the off breakdown voltage.

  In the first to sixth embodiments, the composition and thickness of each semiconductor layer constituting the field effect transistor and the width of the recess 201 are not limited to the above. Further, the electrode metal constituting the source electrode 108, the drain electrode 109, and the gate electrode 110 and the film thickness thereof are not limited to the above. Further, the region of the ion implantation part 107 is not limited to the above.

In the fourth embodiment, the insulating film 202 is not limited to SiN, and SiO ₂ , SiON (silicon oxynitride film), aluminum oxide, aluminum nitride, or the like may be used.

  In the first to sixth embodiments, sapphire, silicon carbide, gallium nitride, aluminum nitride, gallium oxide, or the like can be used as the substrate 101 in addition to Si having a main surface of (111).

  In the first to sixth embodiments, Mg is used as the acceptor impurity, but Be, C, and Zn may be used in addition to Mg.

  In the first to sixth embodiments, Mg is used as the acceptor impurity, but Be, C, and Zn may be used in addition to Mg.

  The field effect transistor according to the present invention is capable of suppressing a gate leakage current and improving an off breakdown voltage by doping Mg into an electron barrier layer made of a nitride semiconductor containing In. Transistors can be used greatly in the field of power devices that require high breakdown voltage, such as air conditioning and automobile control.

DESCRIPTION OF SYMBOLS 101 Substrate 102 Channel layer 103 First electron barrier layer 104 Second electron barrier layer 105 Third electron barrier layer 106 Fourth electron barrier layer 107 Ion implantation part 108 Source electrode 109 Drain electrode 110 Gate electrode 201 Recess part 202 Insulating film 203 Ohmic film Window

Claims (13)

A substrate,
A channel layer made of a first nitride semiconductor and disposed on the substrate;
An electron supply layer formed on the channel layer;
A source electrode, a gate electrode and a drain electrode formed on the electron supply layer,
The electron supply layer contains In, formed on a layer made of a second nitride semiconductor having a band gap larger than that of the first nitride semiconductor and a layer made of the second nitride semiconductor. And a layer made of a third nitride semiconductor having a band gap larger than that of the first nitride semiconductor,
In the third nitride semiconductor layer, acceptor impurities are added to compensate the donor ,
The electron supply layer is provided with a recess that reaches the layer made of the third nitride semiconductor, and the gate electrode is formed at the bottom of the recess,
The width of the recess is wider than the width of the gate electrode, and the gate electrode and the third nitride semiconductor layer are separated from each other . The field effect transistor according to claim 1, wherein the second nitride semiconductor contains In.   The field effect transistor according to claim 2, wherein the second nitride semiconductor layer and the third nitride semiconductor layer have the same composition.   The impurity concentration of the layer made of the third nitride semiconductor is higher than the impurity concentration of the layer made of the second nitride semiconductor, 4. Field effect transistor.   The electron supply layer has a layer made of a fourth nitride semiconductor having a band gap larger than that of the second nitride semiconductor at a position closer to the channel layer than the layer made of the second nitride semiconductor. The field effect transistor according to claim 1, wherein:   6. The field effect transistor according to claim 5, wherein a band gap of the fourth nitride semiconductor is larger than a band gap of the third nitride semiconductor. The electron supply layer is
A fifth nitride semiconductor layer disposed between the second nitride semiconductor layer and the fourth nitride semiconductor layer;
The field effect transistor according to claim 5 or 6, wherein a band gap of the fifth nitride semiconductor is smaller than a band gap of the fourth nitride semiconductor.   The field effect transistor according to claim 7, wherein an In composition of the fifth nitride semiconductor is smaller than an In composition of the second nitride semiconductor. 9. The acceptor impurity concentration of the third nitride semiconductor layer is 5 × 10 ¹⁸ cm ⁻³ or more and 5 × 10 ¹⁹ cm ⁻³ or less, according to any one of claims 1 to 8, 2. The field effect transistor according to item 1.   The electron supply layer is provided with a recess portion that reaches the layer made of the fourth nitride semiconductor from the layer made of the third nitride semiconductor, and the gate electrode is formed at the bottom of the recess portion. Item 6. The field effect transistor according to Item 5.   The field effect transistor according to claim 1, further comprising an insulating layer between the electron supply layer and the gate electrode. The field effect transistor according to any one of claims 1 to 11, wherein Mg is added as an impurity to the layer made of the third nitride semiconductor. 9. The field effect transistor according to claim 8, wherein the layer made of the second nitride semiconductor, the layer made of the third nitride semiconductor, and the layer made of the fifth nitride semiconductor are InAlGaN.

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