JP2023109224A - Deterioration detection device, power conversion device, and deterioration detection method - Google Patents

Abstract

To detect deterioration of a bonding material under a semiconductor chip with accuracy.SOLUTION: A deterioration detection device comprises: a conductor layer; a semiconductor chip whose rear face is bonded with a front face of the conductor layer with a bonding material; a wire bonded with a front face of the semiconductor chip; a first terminal electrically connected with the rear face of the semiconductor chip via the bonding material and the conductor layer; a second terminal electrically connected with the front face of the semiconductor chip via the wire; a third terminal electrically connected with the bonding material in the vicinity of the semiconductor chip; and a monitoring part that monitors an electric resistance between the first and third terminals, and when the electric resistance becomes larger than a predetermined value, outputs a predetermined signal.SELECTED DRAWING: Figure 5

Description

The present disclosure relates to a deterioration detection device, a power conversion device, and a deterioration detection method.

Conventionally, the collector-emitter voltage Vce is measured when a constant collector current is flowing through the semiconductor element. A technique for determining closeness is known (see Patent Document 1, for example).

Japanese Unexamined Patent Application Publication No. 2011-200033

However, the measured value of the voltage Vce described above increases not only due to deterioration of the bonding material (for example, solder) under the semiconductor chip, but also due to deterioration of the bonding portion between the semiconductor chip and the bonding wire. Therefore, the above-described method of monitoring the measured value of the voltage Vce may not be able to accurately detect the deterioration of the bonding material under the semiconductor chip.

The present disclosure provides a deterioration detection device, a power conversion device, and a deterioration detection method capable of accurately detecting deterioration of a bonding material under a semiconductor chip.

In one aspect of the present disclosure,
a conductor layer;
a semiconductor chip whose back surface is bonded to the surface of the conductor layer with a bonding material;
a wire bonded to the surface of the semiconductor chip;
a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer;
a second terminal electrically connected to the surface of the semiconductor chip via the wire;
a third terminal electrically connected to the bonding material near the semiconductor chip;
and a monitoring unit that monitors electrical resistance between the first terminal and the third terminal and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

In another aspect of the present disclosure,
a plurality of semiconductor devices for power conversion;
a control unit that controls switching of the plurality of semiconductor devices,
Each of the plurality of semiconductor devices includes:
a conductor layer;
a semiconductor chip whose back surface is bonded to the surface of the conductor layer with a bonding material;
a wire bonded to the surface of the semiconductor chip;
a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer;
a second terminal electrically connected to the surface of the semiconductor chip via the wire;
a third terminal electrically connected to the bonding material near the semiconductor chip;
The power conversion device is provided, wherein the control unit monitors electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value.

In another aspect of the present disclosure,
A conductor layer, a semiconductor chip whose back surface is bonded to the surface of the conductor layer with a bonding material, a wire bonded to the surface of the semiconductor chip, and a back surface of the semiconductor chip via the bonding material and the conductor layer. A first terminal electrically connected, a second terminal electrically connected to the surface of the semiconductor chip via the wire, and a second terminal electrically connected to the bonding material near the semiconductor chip. A deterioration determination method for a semiconductor device having three terminals,
A deterioration detection method is provided, wherein the electrical resistance between the first terminal and the third terminal is monitored, and a predetermined signal is output when the electrical resistance exceeds a predetermined value.

According to the present disclosure, it is possible to accurately detect the deterioration of the bonding material under the semiconductor chip.

FIG. 4 is a cross-sectional view of a portion of the power semiconductor module when wire joints are degraded; FIG. 4 is a cross-sectional view of a part of the power semiconductor module when the bonding material under the semiconductor chip is deteriorated; FIG. 2 is a diagram showing examples of semiconductor chips (an IGBT chip and a diode chip); FIG. 4 is a diagram illustrating a relationship between a voltage Vce_on between main terminals when the power semiconductor module is in a conducting state and an operating time of the power semiconductor module; It is a block diagram which shows an example of the degradation detection apparatus which concerns on this embodiment. It is a cross-sectional view of part of the power semiconductor module according to the present embodiment. 1 is an equivalent circuit diagram of a power semiconductor module according to this embodiment; FIG. It is a block diagram which shows an example of a monitoring part. It is a figure which shows the whole structure of the power converter device which concerns on this embodiment. FIG. 10 is a diagram illustrating waveforms of respective parts accompanying detection operation of voltage Vcc_1 in an ON state; 4 is a timing chart for explaining a method of detecting deterioration of a bonding material using electrical resistance R1;

Embodiments will be described below.

In recent years, power converters have been used in applications that require high reliability (power systems, mobile bodies such as trains and automobiles, etc.), and along with this, the demand for high reliability of power converters is increasing. In response to this demand, expectations are rising for the realization of predictive maintenance that predicts failures and takes countermeasures in advance.

A power semiconductor module is one of the main failure factors of power converters. A major failure of power semiconductor modules is caused by thermal stress stress caused by repeated current conduction and switching operations that degrade bonding wires and solder. As the bonding wires and solder deteriorate, the conduction resistance between the main terminals increases when the power semiconductor module is in the ON state (conducting state). Von rises. Therefore, deterioration of the power semiconductor module can be detected by detecting an increase in the voltage Von.

FIG. 1 is a cross-sectional view of a portion of a power semiconductor module when a wire joint deteriorates. FIG. 2 is a cross-sectional view of a portion of the power semiconductor module when the bonding material under the semiconductor chip has deteriorated. 1 and 2, the power semiconductor module includes a semiconductor chip 11, wires 16 for connecting the semiconductor chip 11 to the outside, and a bonding material 8 for bonding the semiconductor chip 11 to a substrate (not shown). It is a semiconductor device.

Wire 16 is a conductor whose one end is bonded to surface 12 of semiconductor chip 11 . The wire 16 is, for example, a bonding wire such as an aluminum wire. The bonding material 8 is a conductor that contacts the back surface 13 of the semiconductor chip 11 . The bonding material 8 is typically solder, but may be another bonding material such as an adhesive. Thermal stress generated by repeated conduction/interruption operations of the semiconductor chip 11 degrades the bonding portion between the wire 16 and the semiconductor chip 11 and the bonding material 8 such as solder.

As the deterioration of the wire 16 progresses, for example, a crack 9 occurs at the junction between the wire 16 and the surface 12, increasing the resistance of the junction. On the other hand, if the deterioration of the bonding material 8 progresses, for example, a crack 9 will occur in the bonding material 8 and the resistance of the bonding material 8 will increase. Therefore, as the deterioration of the wire 16 and the bonding material 8 progresses, the voltage Von between the main terminals of the power semiconductor module in the conducting state (see FIG. 3. If the power semiconductor module is an IGBT, the voltage Von between the collector and the emitter in the conducting state The voltage Vce_on) increases slowly (see FIG. 4). By monitoring the rise of this voltage Von (Vce_on), it is possible to detect a sign of failure of the power semiconductor module.

However, the increase in the voltage Von (Vce_on) between the main terminals in the conductive state of the power semiconductor module is due to the deterioration of the bonding portion of the wire 16 and the deterioration of the bonding material 8, as described above. and the rising portion. Therefore, even if the rise of the voltage Von (Vce_on) is monitored, it may not be possible to accurately detect the deterioration of the bonding material 8 under the semiconductor chip 11 .

The deterioration detection device and the power conversion device according to the present embodiment are configured to accurately detect the deterioration of the bonding material under the semiconductor chip. The configuration of the deterioration detection device and the power conversion device according to this embodiment, and the deterioration detection method executed by the deterioration detection device or power conversion device according to this embodiment will be described below.

FIG. 5 is a configuration diagram showing an example of the deterioration detection device according to this embodiment. A deterioration detection device 200 shown in FIG. 5 is a device for detecting deterioration of the power semiconductor module 100 . The deterioration detection device 200 has a power semiconductor module 100 and a monitoring section 40 .

Power semiconductor module 100 is an example of a semiconductor device. FIG. 5 shows the power semiconductor module 100 in plan view. The power semiconductor module 100 includes an insulating substrate 1, a semiconductor chip 11, a collector terminal C, an emitter terminal E, a gate terminal G, an auxiliary emitter terminal EA, an auxiliary collector terminal CA, and wires 16, 17, 18, 19.

The insulating substrate 1 is a substrate on which a semiconductor chip 11 is mounted, and for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Blazing) substrate, or the like can be adopted. The insulating substrate 1 is fixed onto a base substrate (not shown) formed on the bottom surface of the housing of the power semiconductor module 100 via a bonding material (not shown) such as solder.

The insulating substrate 1 includes conductor layers 2-6 formed on its surface. The conductor layers 2 to 6 are provided on the upper surface of the insulating layer of the insulating substrate 1 using a conductive metal such as copper or aluminum. The conductor layers 2 to 6 may be conductor plates or conductor foils.

The conductor layer 2 is a rectangular planar conductor arranged in a region on the back surface side of the semiconductor chip 11 in plan view of the semiconductor chip 11 . The conductor layer 3 is a rectangular planar conductor arranged in a region in a first direction (downward direction in the drawing) with respect to the semiconductor chip 11 in a plan view of the semiconductor chip 11, and extends from the conductor layer 2 in the first direction. located away from. The conductor layers 4 and 5 are rectangular conductor layers arranged in a region in a second direction (a direction opposite to the first direction, an upward direction in the drawing) with respect to the semiconductor chip 11 in plan view of the semiconductor chip 11 . It is a planar conductor and is located away from the conductor layer 2 in the second direction. The conductor layer 6 is arranged in a region of a third direction (a direction perpendicular to the first direction and the second direction, leftward direction in the drawing) with respect to the semiconductor chip 11 in a plan view of the semiconductor chip 11 . It is a planar conductor and is located away from the conductor layer 2 in the third direction. The sizes, shapes and positions of the conductor layers 2 to 6 are not limited to those shown in the drawings.

The semiconductor chip 11 is a semiconductor element incorporated in the power semiconductor module 100, and is, for example, a semiconductor switching element having electrodes on each of its front and back surfaces. The semiconductor chip 11 may be either a Si semiconductor element or a SiC semiconductor element. FIG. 5 illustrates a case where the semiconductor chip 11 is an insulated gate bipolar transistor (IGBT) chip.

FIG. 6 is a cross-sectional view of part of the power semiconductor module according to this embodiment. The semiconductor chip 11 has a front surface 12 on which an emitter electrode 11e and a gate electrode 11g (see FIG. 5) are arranged, and a back surface 13 on which a collector electrode 11c is arranged. The collector electrode 11c is an example of a first main electrode that the semiconductor chip 11 has, and is formed on the rear surface 13 in this example. The emitter electrode 11 e is an example of a second main electrode that the semiconductor chip 11 has and is formed on the surface 12 . The gate electrode 11g is an example of a control electrode that the semiconductor chip 11 has and is formed on the surface 12. As shown in FIG. The semiconductor chip 11 is fixed on the insulating substrate 1 (see FIG. 5) at the rear surface 13 by bonding the collector electrode 11c to the conductor layer 2 with a bonding material 8 such as solder.

In FIG. 5, a collector terminal C, an emitter terminal E, a gate terminal G, an auxiliary emitter terminal EA, and an auxiliary collector terminal CA are external terminals for connecting the power semiconductor module 100 to the outside. Each of these external terminals is made of a conductive metal such as copper or aluminum and formed into a cylindrical shape or a flat plate shape.

The collector terminal C is a main terminal electrically connected to the collector electrode 11c (see FIG. 6) of the semiconductor chip 11 via the conductor layer 2 and the bonding material 8. As shown in FIG. The emitter terminal E is a main terminal electrically connected to the emitter electrode 11 e of the semiconductor chip 11 via the conductor layer 3 and wire 16 . The gate terminal G is a control terminal electrically connected to the gate electrode 11g of the semiconductor chip 11 via the conductor layer 4 and the wire 17. As shown in FIG. The auxiliary emitter terminal EA is an auxiliary terminal electrically connected to the emitter electrode 11 e of the semiconductor chip 11 via the conductor layer 5 and the wire 18 . The auxiliary collector terminal CA is an auxiliary terminal electrically connected to the bonding material 8 near the semiconductor chip 11 via the conductor layer 6 and the wire 19 .

The wires 16 to 19 are linear members formed with a diameter of 300 to 500 μm using, for example, a conductive metal such as copper or aluminum or a conductive alloy such as an iron-aluminum alloy. The wire 16 is one or more (four in this example) wires that connect the emitter electrode 11 e , which is the surface electrode of the semiconductor chip 11 , to the conductor layer 3 . The wire 17 is one or more (in this example, one) wire that connects the gate electrode 11g, which is the surface electrode of the semiconductor chip 11, to the conductor layer 4. FIG. The wire 18 is one or a plurality of (in this example, one) wire that connects the emitter electrode 11 e , which is the surface electrode of the semiconductor chip 11 , to the conductor layer 5 . The wire 19 is one or more (in this example, one) wire that connects the bonding material 8 to the conductor layer 6 . The wire 19 has one end connected to the bonding material 8 near the semiconductor chip 11 and the other end connected to the conductor layer 6 .

In this example, one end of the wire 19 is electrically joined to the conductor plate 7 in contact with the upper surface of the joining material 8 so as to be conductive. The conductor plate 7 is provided near the semiconductor chip 11 (in this example, near the corner of the semiconductor chip 11). The conductor plate 7 may be provided near the sides of the semiconductor chip 11 . The conductor plate 7 functions as an electrode to which one end of the wire 19 is joined. The conductor plate 7 is a plate-like or foil-like conductor made of a conductive metal such as copper or aluminum. The conductor plate 7 is connected via at least one wire 19 to the auxiliary collector terminal CA. The place where the conductor plate 7 is installed is not limited to one, and may be plural.

In FIG. 6, a semiconductor chip 11 has a rear surface 13 bonded to a surface of a conductor layer 2 with a bonding material 8 . One end of the wire 16 is joined to the emitter electrode 11 e on the surface 12 of the semiconductor chip 11 . The collector terminal C is an example of a first terminal electrically connected to the back surface 13 of the semiconductor chip 11 via the bonding material 8 and the conductor layer 2 . Emitter terminal E is an example of a second terminal electrically connected to surface 12 of semiconductor chip 11 via wire 16 . The auxiliary collector terminal CA is an example of a third terminal electrically connected to the bonding material 8 near the semiconductor chip 11 .

When the semiconductor chip 11 becomes conductive between the collector electrode 11c and the emitter electrode 11e, the current Ic flows through the collector terminal C, the conductor layer 2, the bonding material 8, the semiconductor chip 11, the wire 16 and the emitter terminal E in this order. When the current Ic is repeatedly turned on and off, the deterioration of the bonding material 8 progresses.

When a crack 9 (particularly, a crack 9 substantially parallel to the back surface 13 of the semiconductor chip 11) occurs in the bonding material 8 as the bonding material 8 deteriorates, the current Ic flowing through the bonding material 8 will flow through the conductor layer 2 and the collector electrode. 11c becomes difficult to flow in the vertical direction facing each other. Therefore, the electric resistance R1 (see FIG. 7) between the collector terminal C and the auxiliary collector terminal CA becomes large. In FIG. 6, since the conductor layer 2 and the collector terminal C are less likely to deteriorate than the bonding material 8, the increase in the electrical resistance of the conductor layer 2 and the collector terminal C due to deterioration is extremely small. Therefore, the increase in the electrical resistance R1 is mostly accounted for by the increase caused by the deterioration of the bonding material 8. FIG.

Focusing on this point, the monitoring unit 40 (see FIG. 5) monitors the electrical resistance R1 between the collector terminal C and the auxiliary collector terminal CA, and in the ON state between the collector terminal C and the emitter terminal E When the electrical resistance R1 of the circuit exceeds a predetermined value, it outputs a predetermined signal. Output of a predetermined signal represents detection of deterioration of the bonding material 8 . As described above, the deterioration detection device 200 includes the monitoring unit 40 that outputs a predetermined signal when the electrical resistance R1 to be monitored exceeds a predetermined value, so deterioration of the bonding material 8 under the semiconductor chip 11 can be accurately detected. .

The monitoring unit 40 monitors, for example, the voltage Vcc between both terminals of the collector terminal C and the auxiliary collector terminal CA, detects the on-voltage Vcc_on that is the voltage Vcc between the two terminals in the on state, and An on-current Ic_on, which is the current Ic flowing in the on-state during the period, is measured. The monitoring unit 40 may monitor a value obtained by dividing the detected value of the on-voltage Vcc_on by the measured value of the on-current Ic_on as the electrical resistance R1. By performing such division, the monitoring unit 40 can easily derive the electrical resistance R1.

FIG. 8 is a configuration diagram showing an example of a monitoring unit. The monitoring unit 40 shown in FIG. 8 outputs a predetermined signal indicating detection of deterioration of the bonding material 8 using the electrical resistance R1 obtained by dividing the detected value of the on-voltage Vcc_on by the measured value of the on-current Ic_on. It has the function to The functions shown in FIG. 8 may be realized only by hardware resources such as circuits, or may be realized by cooperation between hardware resources and software.

The monitoring unit 40 may be, for example, a control device including a processor such as a CPU (Central Processing Unit) and a memory, or a part thereof. The function of the monitoring unit 40 is implemented by the processor operating according to the program stored in the memory. The function of the monitoring unit 40 may be realized by FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

The sample timing generator 41 generates the detected value of the voltage Vcc according to the timing when the command value of the current i flowing between the collector terminal C and the emitter terminal E passes through a predetermined non-zero current value Ith. and generate a timing to sample the measured value of current i.

The detected value of the voltage Vcc is sampled and held by the sample and hold section 42 at the timing generated by the sample timing generation section 41 . The sample-and-hold value obtained by the sample-and-hold unit 42 corresponds to the detected value of the ON voltage Vcc_on. The measured value of the current i is sampled and held by the sample and hold section 43 at the timing generated by the sample timing generation section 41 . The sample-and-hold value obtained by the sample-and-hold unit 43 corresponds to the measured value of the on-current Ic_on. As for the measured value of the on-current Ic_on, the calculator 45 calculates the reciprocal of the measured value of the on-current Ic_on. The electric resistance R1 is calculated by multiplying the detected value of the on-voltage Vcc_on and the reciprocal of the measured value of the on-current Ic_on by the multiplier 44 .

The electrical resistance R1 may be corrected by an estimated value of the temperature Tj of the semiconductor chip 11 in the ON state. The temperature correction unit 46 estimates the temperature Tj of the semiconductor chip 11 in the ON state, and corrects the output timing of a predetermined signal representing deterioration detection of the bonding material 8 according to the estimated value of the temperature Tj. As a result, it is possible to suppress deterioration in the accuracy of deterioration detection due to changes in the temperature Tj of the semiconductor chip 11 .

The temperature correction unit 46 acquires the temperature detection value Th of the heat sink of the semiconductor chip 11 at the timing generated by the sample timing generation unit 41, for example, and estimates the temperature Tj of the semiconductor chip 11 from the acquired temperature detection value Th. . The temperature correction unit 46 derives a correction value ΔR corresponding to the estimated value of the temperature Tj based on a relational rule (for example, a map or an arithmetic expression) between the estimated value of the temperature Tj and the correction value ΔR. The correction value .DELTA.R is a value for removing the variation in the electrical resistance R1 caused by the change in the temperature Tj of the semiconductor chip 11. FIG. The electric resistance R1_0 (electric resistance R1 before temperature correction) calculated by the multiplier 44 and the correction value ΔR derived by the temperature correction unit 46 are added by the adder 47 to obtain the electric resistance after temperature correction. A resistor R1 is derived.

The failure sign determination unit 48 compares the electrical resistance R1 with a determination threshold, and outputs a deterioration detection signal according to the magnitude relationship between the electrical resistance R1 and the determination threshold. The determination threshold is set to a predetermined value (eg, a predetermined multiple (eg, 1.05 times) of the initial value R1_s of the electrical resistance R1). A deterioration detection signal is input to the latch circuit 49 . Triggered by the input of the deterioration detection signal, the latch circuit 49 outputs a determination value (an example of a predetermined signal) indicating that there is a sign of failure due to deterioration of the bonding material 8 in the power semiconductor module 100 .

When the latch circuit 49 outputs a determination value indicating that there is a sign of failure, the predetermined notification device notifies a predetermined external device or user that there is a sign of failure due to deterioration of the bonding material 8 of the power semiconductor module 100. Notice. By notifying that there is a sign of failure, it is possible to take maintenance measures before failure of the power semiconductor module 100 occurs.

FIG. 9 is a diagram showing an example of the overall configuration of the power converter according to this embodiment. The power converter 101 shown in FIG. 9 includes a main circuit unit 10 that converts DC power supplied from a DC power supply 33 into AC power that is supplied to a load 14, and control for controlling the power conversion operation of the main circuit unit 10. a part 20; FIG. 9 illustrates a form in which the main circuit unit 10 converts DC power into three-phase AC power.

The main circuit section 10 includes a plurality of power semiconductor modules 111-116, a plurality of gate driving sections 121-126, and a current detecting section 30. FIG. The power semiconductor modules 111 to 116 are examples of semiconductor devices for power conversion.

Note that FIG. 9 illustrates, as a power semiconductor module, a 1-in-1 package IGBT module incorporating an IGBT chip for one arm of an inverter and a diode chip (FWD chip) connected in anti-parallel thereto. IGBT is an abbreviation for Insulated Gate Bipolar Transistor, an IGBT chip is an example of a power semiconductor device, and an FWD chip is an example of a rectifying device. However, the package configuration of the power semiconductor module may be another type of package configuration such as 6in1, and the power semiconductor element configured in the power semiconductor module may be another type of power semiconductor element such as MOSFET. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Further, the plurality of power semiconductor modules 111-116 have the same configuration, and the plurality of gate driving units 121-126 have the same configuration. Therefore, for the sake of convenience, the u-phase upper arm will be described below as an example.

In the example shown in FIG. 9, the u-phase upper arm power semiconductor module 111 has an IGBT chip Q1 and a FWD chip D1. The power semiconductor module 111 also has a collector terminal C, an emitter terminal E, a gate terminal G, an auxiliary emitter terminal EA and an auxiliary collector terminal CA. The collector terminal C is an example of a first terminal, the emitter terminal E is an example of a second terminal, the auxiliary collector terminal CA is an example of a third terminal, and the gate terminal G is an example of a control terminal. be.

The IGBT chip Q1 is an example of a switching element (semiconductor element) having a collector electrode 11c, an emitter electrode 11e and a gate electrode 11g. The collector electrode 11c is an example of a first main electrode, the emitter electrode 11e is an example of a second main electrode, and the gate electrode 11g is an example of a control electrode.

The FWD chip D1 is an example of a rectifying device (semiconductor device) having an anode electrode 11a and a cathode electrode 11k.

The collector terminal C is electrically connected to the collector electrode 11c and the cathode electrode 11k. The emitter terminal E is electrically connected to the emitter electrode 11e and the anode electrode 11a. The gate terminal G is electrically connected to the gate electrode 11g. The auxiliary emitter terminal EA is electrically connected to the emitter electrode 11e and the anode electrode 11a. The auxiliary collector terminal CA is electrically connected to the collector electrode 11c and the cathode electrode 11k.

The gate drive unit 121 is a drive circuit that includes a predriver PD1 and a voltage detection circuit Vcc1.

The pre-driver PD1 is a circuit that drives the gate electrode 11g of the IGBT chip Q1 according to the ON or OFF switching command S_1 supplied from the control unit 20. FIG.

Voltage detection circuit Vcc1 detects voltage Vcc_1 between collector terminal C and auxiliary collector terminal CA of IGBT chip Q1 of power semiconductor module 111 and transmits the detected value of Vcc_1 to control unit 20 .

The current detection unit 30 is a current sensor that detects three-phase alternating currents iu, iv, and iw flowing between the power semiconductor modules 111 to 116 and the load 14 and transmits the detected three-phase alternating currents iu, iv, and iw to the control unit 20 .

The control unit 20 is, for example, a control device including a processor such as a CPU (Central Processing Unit) and a memory. The functions of the control unit 20 are implemented by the processor operating according to the programs stored in the memory. The functions of the control unit 20 may be realized by FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

The main circuit section 10 may include a heat sink temperature detection section 80 . The heat sink temperature detection unit 80 is a temperature sensor that detects the temperature of heat sinks (for example, fins) for cooling the power semiconductor modules 111 to 116 and transmits the heat sink temperature detection value Th to the control unit 20 .

Next, an example of a method for detecting the voltage Vcc_1 when the IGBT chip is on will be described.

FIG. 10 is a diagram exemplifying the waveforms of each part accompanying the detection operation of the voltage Vcc_1 in the ON state. In this example, iu is a sinusoidal current and the U-phase voltage command is a sinusoidal voltage. The ON state and OFF state of the U-phase upper and lower arms are determined by the magnitude relationship between the U-phase voltage command and the carrier wave. In this example, the control unit 20 outputs a switching command S_1 that turns on Q1 and turns off Q2 during a period in which the U-phase voltage command is greater than the carrier wave. On the other hand, the control unit 20 outputs a switching command S_1 to turn off Q1 and turn on Q2 during a period in which the U-phase voltage command is smaller than the carrier wave.

When Q1 is on and iu is positive, the same current Ic1 as iu flows through Q1. When Q2 is off and iu is negative, the same current as iu flows through D1. These currents and the chip temperature of Q1 or D1 respectively determine the voltage Vcc1_on when Q1 or D1 respectively is in a conductive state. The voltage Vcc1_on is transmitted as a discrete value from the voltage detection circuit Vcc1 to the control unit 20 at the frequency of the carrier wave. In the illustrated example, the sampling timing of Vcc1_on is each bottom of the carrier wave. The control unit 20 samples the detected value of the current iu detected by the current detection unit 30 at each bottom of the carrier wave and acquires the values from the current detection unit 30 .

Note that the method of detecting the voltage Vcc_on1 between the main terminals in the ON state is not limited to this.

The control unit 20 has the function of the monitoring unit 40 described above. The control unit 20 acquires the detected value of the voltage Vcc_on1 and the measured value of the current Ic1 at the same timing, and divides the detected value of the voltage Vcc_on1 by the measured value of the current Ic1 to obtain the electric resistance R1_1 of the bonding material 8 of Q1. calculate.

When the determination value indicating that there is a failure sign is output from the latch circuit 49, the control unit 20 notifies the external device of the power conversion device 101 or the power converter 101 that there is a failure sign due to the deterioration of the bonding material 8 of the power semiconductor module 111. Notify the user. Even if the control unit 20 notifies that there is a failure sign of the main circuit unit 10 in which the power semiconductor module 111 is mounted, or notifies that there is a failure sign of the power conversion device 101 in which the main circuit unit 10 is mounted. good. By notifying that there is a sign of failure, it becomes possible to take maintenance measures before failure of the power semiconductor module 111 occurs.

Thus, the power conversion device 101 includes the control section 20 having the function of the monitoring section 40 . Therefore, the control unit 20 can detect (determine) the deterioration of the bonding material 8 by executing the deterioration determination method as described above.

FIG. 11 is a timing chart for explaining a method of detecting deterioration of a bonding material using an electrical resistance R1. At the initial stage, the electrical resistance R1 between the collector terminal C and the auxiliary collector terminal CA is substantially constant regardless of the applied voltage and the flowing current. As the deterioration of the bonding material 8 progresses due to repeated thermal stress, the electrical resistance R1 gradually increases. The increase in electrical resistance R1 results from deterioration of the bonding material 8 (increase in thermal resistance). The monitoring unit 40 determines that the bonding material 8 has deteriorated when the electrical resistance R1 observed online exceeds the determination threshold value Rt. The determination threshold Rt is set, for example, to 1.05 times the initial value R1_s of the electrical resistance R1.

Although the embodiments have been described above, the present invention is not limited to the above embodiments. Various modifications and improvements such as combination or replacement with part or all of other embodiments are possible.

For example, semiconductor chips are not limited to power transistors such as IGBTs, but may be diodes, thyristors, gate turn-off thyristors, triacs, and the like.

The semiconductor chip may be a vertical power metal oxide semiconductor field effect transistor (power MOSFET). In the above-described embodiments, when the semiconductor chip is a MOSFET chip, the collector is replaced with the drain and the emitter is replaced with the source, so that deterioration of the bonding material under the MOSFET chip can be detected with high accuracy.

A semiconductor chip may be a diode. The diode may be a diode connected in antiparallel to a switching element such as an IGBT. In the above-described embodiment, when the semiconductor chip is a diode chip, the collector is replaced with the cathode and the emitter is replaced with the anode, so that deterioration of the bonding material under the diode chip can be detected with high accuracy.

Also, the temperature detection unit may directly observe and estimate the temperature of the semiconductor chip instead of indirectly estimating the temperature of the semiconductor chip from the temperature of the heat sink.

Reference Signs List 1 insulating substrate 2 to 6 conductor layer 7 conductor plate 8 bonding material 9 crack 10 main circuit section 11 semiconductor chip 11a anode electrode 11c collector electrode 11e emitter electrode 11g gate electrode 11k cathode electrode 12 front surface 13 rear surface 14 load 16, 17, 18, 19 wire 20 control unit 30 current detection unit 33 power supply 40 monitoring unit 80 heat sink temperature detection unit 100 power semiconductor module 101 power conversion device 111 to 116 power semiconductor module 121 to 126 gate drive unit 200 deterioration detection device C collector terminal CA auxiliary collector terminal E Emitter terminal EA Auxiliary emitter terminal G Gate terminal

Claims (6)

a conductor layer;
a semiconductor chip whose back surface is bonded to the surface of the conductor layer with a bonding material;
a wire bonded to the surface of the semiconductor chip;
a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer;
a second terminal electrically connected to the surface of the semiconductor chip via the wire;
a third terminal electrically connected to the bonding material near the semiconductor chip;
a monitoring unit that monitors electrical resistance between the first terminal and the third terminal and outputs a predetermined signal when the electrical resistance exceeds a predetermined value. 2. The deterioration detection device according to claim 1, wherein said electrical resistance is a resistance in an ON state between both terminals of said first terminal and said second terminal. The monitoring unit detects an ON voltage, which is a voltage between the terminals in the ON state, and an ON current, which is a current flowing between the terminals in the ON state, and detects the ON voltage as the ON current. 3. The deterioration detection device according to claim 2, wherein a value obtained by division is monitored as said electrical resistance. The monitoring unit estimates the temperature of the semiconductor chip in an ON state between both terminals of the first terminal and the second terminal, and corrects the output timing of the predetermined signal according to the estimated value of the temperature. 4. The deterioration detection device according to any one of claims 1 to 3. a plurality of semiconductor devices for power conversion;
a control unit that controls switching of the plurality of semiconductor devices,
Each of the plurality of semiconductor devices includes:
a conductor layer;
a semiconductor chip whose back surface is bonded to the surface of the conductor layer with a bonding material;
a wire bonded to the surface of the semiconductor chip;
a first terminal electrically connected to the back surface of the semiconductor chip via the bonding material and the conductor layer;
a second terminal electrically connected to the surface of the semiconductor chip via the wire;
a third terminal electrically connected to the bonding material near the semiconductor chip;
The power conversion device, wherein the control unit monitors electrical resistance between the first terminal and the third terminal, and outputs a predetermined signal when the electrical resistance exceeds a predetermined value. A conductor layer, a semiconductor chip whose back surface is bonded to the surface of the conductor layer with a bonding material, a wire bonded to the surface of the semiconductor chip, and a back surface of the semiconductor chip via the bonding material and the conductor layer. A first terminal electrically connected, a second terminal electrically connected to the surface of the semiconductor chip via the wire, and a second terminal electrically connected to the bonding material near the semiconductor chip. A deterioration determination method for a semiconductor device having three terminals,
A deterioration detection method, comprising: monitoring an electrical resistance between the first terminal and the third terminal; and outputting a predetermined signal when the electrical resistance exceeds a predetermined value.

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