JP6024177B2 - Power semiconductor module - Google Patents

Description

  The present invention relates to a power semiconductor module having a switching element such as an IGBT (insulated gate bipolar transistor) and a freewheeling diode connected in antiparallel to the switching element, for example, a Schottky barrier diode.

  The fields where power semiconductor modules are used range from home appliances to electric railways, electric cars, industrial robots, and power systems. As the usefulness of power semiconductor devices expands, improvement in performance is expected, and higher frequency, smaller size, and higher power are increasingly desired.

  Many of the power semiconductor modules used in these fields are used in conversion circuits such as AC-DC conversion, DC-AC conversion, and DC-DC conversion. In these power semiconductor modules, for example, switching elements such as IGBTs (Insulated Gate Bipolar Transistors) and MOSFETs (MOS Field Effect Transistors), and FWDs (free diodes) connected in reverse parallel to these switching elements are included. Wheeling diode).

  FIG. 7 is a single-phase bridge inverter circuit diagram. This is an example of a conventional inverter circuit, and portions 6A, 6B, 6C, and 6D surrounded by broken lines indicate power semiconductor modules.

  In this example, each power semiconductor module 6A, 6B, 6C, 6D includes one free-wheeling diode (FWD) 7A, 7B, 7C, 7D and one switching element (IGBT in this example) 3A, 3B, 3C, 3D. Are installed in pairs. The free-wheeling diode is connected in antiparallel to each IGBT that is a switching element. Reference numeral 54 in the figure is a load having an inductance. Reference numeral 55 denotes a DC power source.

  When performing DC-AC conversion using an inverter circuit including a switching element such as IGBT or MOSFET having a self-extinguishing function, a PWM (pulse width modulation) method is generally used.

  FIG. 8 is an output waveform diagram to the load when DC-AC conversion is performed by the PWM method using the single-phase bridge inverter circuit of FIG. In the PWM method, the square pulse waveform of the gate signal of the switching element is modulated so that the load voltage becomes an AC waveform when viewed on a time average basis. When a pulse voltage obtained by modulating the pulse width in the positive direction is output to the load 4 by the on / off operation of the IGBTs 3A and 3D, a sine wave as shown by a solid line Vm in FIG. Is output to the load. However, during this operation period (TAD), the IGBTs 3B and 3C which are switching elements are in an OFF state. Next, a pulse voltage in the negative direction is output to the load 4 by the on / off operation of the IGBTs 3B and 3C, and a sine wave half wave corresponding to the remaining half cycle (TBC) is output to the load.

  During the pulse operation period of the IGBTs 3A and 3D in FIG. 8, for example, when the IGBT 3A is turned off from the on state, the collector voltage of the IGBT 3A is, as shown in FIG. 9, due to the floating inductance of the circuit wiring connected to the IGBT 3A. The dynamic avalanche voltage Vavd0 (clamping voltage) jumps to the dynamic avalanche voltage Vavd0 (clamping voltage). Thereafter, the collector voltage of the IGBT 3A is held at the power supply voltage. In the figure, Ic is the collector current of the IGBT, Vc is the collector voltage, di / dt is the falling slope of the collector current Ic, and Vavs2 is the static avalanche voltage of SiC-SBD2.

Patent Document 1 describes an example in which the FWD in FIG. 7 is composed of two SiC-SBDs connected in series to reduce reverse recovery loss generated in the FWD.
In the following description, Si is silicon, SiC indicates silicon carbide, a device formed on the silicon substrate is indicated by Si, and a device formed on the silicon carbide substrate is indicated by SiC. SBD is a Schottky barrier diode. That is, Si-IGBT is an IGBT formed on a Si substrate, and SiC-SBD is an SBD formed on a SiC substrate. Furthermore, as described above, the FWD (free wheeling diode) is a freewheeling diode, here an SBD.

  In Patent Document 2, the on-resistance, switching speed, and temperature characteristics are improved rather than using a Si-switching element in which a DC-DC converter is composed of SiC-SIT (electrostatic induction transistor) and SiC-Di (diode). An example in which the bonding temperature is 160 ° C. to 300 ° C. is described.

  Patent Document 3 describes an example in which Si-FWD and SiC-FWD are connected in series, and the temperature characteristics of Si-FWD are canceled by the temperature characteristics of SiC-FWD to prevent thermal runaway of Si-FWD.

  Patent Document 4 describes an example in which the temperature rise of a chip can be halved by using SiC-FWD as compared with the case of Si-FWD.

Japanese Patent No. 4559477 JP 2006-187147 A ([0054] to [0056]) Japanese Patent No. 4808290 ([0033], [0067]) Japanese Patent No. 4722229 ([0052])

  FIG. 10 is a circuit diagram of one phase 30 of a conventional inverter. Here, one phase 30 means a circuit in which an upper arm and a lower arm are connected in series. Moreover, as shown in the said patent document 1, the example in which the power semiconductor module was comprised by Si-IGBT31 and SiC-SBD32 is shown here.

  Since SiC-SBD32 generally has many crystal defects, the yield rate is low in the case of a large chip size. Therefore, generally it is often configured with a small size (for example, 2 mm □). At this time, since the number of wires that can be struck on the anode pad is reduced, the heat generation at the junction between the anode pad and the wire is also increased, and there is a concern that the power cycle resistance is reduced. Therefore, it is necessary to reduce the loss generated in the SiC-SBD 2 functioning as the FWD to suppress heat generation.

  Further, when the circuit wiring inductance (floating inductance L) is large, as shown in FIG. 9, the Si-IGBT 1 has a dynamic avalanche voltage due to a decrease in circuit inductance (L) and main current (collector current Ic) during switching. Vavd is applied. The SiC-SBD 32 having a high static avalanche voltage Vavs2 indicated by a dotted line is used so that the SiC-SBD 32 does not enter the avalanche at the voltage Vavd so that the SiC-SBD 32 is not broken by the application of the voltage Vavd.

  However, the SiC-SBD 32 having a high static avalanche voltage Vavs2 has a thick drift layer, so that the forward voltage drop, commonly referred to as the on-voltage (VF) increases, and the loss generated in the SiC-SBD 32 functioning as the FWD. Becomes larger. As a result, there is a concern about a decrease in power cycle capability.

  Moreover, in patent document 1-patent document 4, SiC-SBD which has a large static avalanche tolerance is used, and the static avalanche voltage of SiC-SBD is made lower than the dynamic avalanche voltage of Si-IGBT1. By reducing the static avalanche voltage of the SiC-SBD, the thickness of the drift layer of the SiC-SBD is reduced, and the on-voltage is lowered. There is no description about reducing the loss generated in the SiC-SBD by reducing the on-voltage to improve the power cycle capability of the SiC-SBD.

  An object of the present invention is to provide a power semiconductor module capable of solving the above-described problems and increasing the power cycle tolerance of a free wheel diode formed on a wide band gap substrate.

In order to achieve the above object, according to the first aspect of the present invention, in a power semiconductor module having a switching element and a free-wheeling diode connected in reverse parallel to the switching element, the switching element There is formed on a silicon substrate, the return diode is formed in wide bandgap substrate, static avalanche voltage of the freewheeling diode in the entire range of junction temperatures in use rather low than the dynamic avalanche voltage of the switching element, the switching A configuration in which the avalanche resistance of the freewheeling diode is larger than the loss generated during the dynamic avalanche period when the element is turned off.

According to the invention described in claim 2, it is preferable that in the invention described in claim 1 , the wide band gap substrate is a semiconductor substrate made of silicon carbide.
According to a third aspect of the present invention, in the first or second aspect , the switching element is an insulated gate bipolar transistor or a MOS field effect transistor, and the free wheel diode Is a Schottky barrier diode.

According to the invention described in claim 4 of the claims , in the invention described in any one of claims 1 to 3 , the reflux diode may be connected to an external lead terminal by a bonding wire.

  According to the present invention, the power cycle resistance of SiC-SBD can be improved by making the static avalanche voltage of SiC-SBD lower than the dynamic avalanche voltage of Si-IGBT.

It is a circuit block diagram of the power semiconductor module 100 which concerns on one Example of this invention. It is a figure explaining the measure which improves the static avalanche tolerance of SiC-SBD, (the figure (a)) is a figure where the avalanche current Iav concentrates on the corner, the figure (b) shows the avalanche current Iav over the active region. FIG. It is a schematic diagram which shows the dynamic avalanche voltage Vavd of Si-IGBT1, the static avalanche voltage Vavs2 of SiC-SBD2, and the relationship of junction temperature. It is a schematic diagram explaining a static avalanche voltage. It is a schematic diagram explaining the dynamic avalanche voltage Vavd of Si-IGBT and the static avalanche voltage Vavs2 of SiC-SBD. It is the schematic diagram explaining the mechanism in which the static avalanche voltage Vavs and the dynamic avalanche voltage Vavd rise when temperature becomes high. It is a single phase bridge inverter circuit diagram. FIG. 8 is an output waveform diagram to a load when DC-AC conversion is performed by a PWM method using the single-phase bridge inverter circuit of FIG. 7. It is a schematic diagram explaining the dynamic avalanche voltage (clamp voltage) generated at the time of turn-off of IGBT3A. It is a circuit diagram of one phase 30 of the conventional inverter.

Embodiments will be described in the following examples.
<Example>
FIG. 1 is a circuit configuration diagram of a power semiconductor module 100 according to one embodiment of the present invention. Here, the power semiconductor module 100 is described as an example in which one set of anti-parallel circuits of switching elements and FWDs is stored in a package to form a 1 in 1 module. If two antiparallel circuits are connected in series and stored in one package, a 2-in-1 module is obtained. When two of the above antiparallel circuits are connected in series and two of these series circuits are connected in parallel and stored in one package, a 4-in-1 module is formed and a single-phase inverter is configured. Similarly, when three of the above series circuits are connected in parallel and stored in one package, a 6-in-1 three-phase inverter is configured.

  The power semiconductor module 100 includes a Si-IGBT 1 and a SiC-SBD 2 connected in reverse parallel thereto. The collector 1a of the Si-IGBT 1 and the cathode 2b of the SiC-SBD 2 are connected to each other and further connected to the collector terminal 3. The emitter 1 b of the Si-IGBT 1 and the anode 2 a of the SiC-SBD 2 are connected to each other and further connected to the emitter terminal 4.

  Although not shown, in this example, the collector 1a of the Si-IGBT 1 and the cathode 2b of the SiC-SBD 2 are joined to the circuit pattern of the insulating substrate and connected to the external lead-out terminal (collector terminal 3) via this circuit pattern. Is done. The emitter 1b of the Si-IGBT 1 and the anode 2a of the SiC-SBD 2 are connected by a bonding wire and connected to an external lead-out terminal (emitter terminal 4).

  SiC-SBD2 is selected in which the static avalanche voltage Vavs2 of the SiC-SBD2 is lower than the dynamic avalanche voltage Vavd of the Si-IGBT1 and the avalanche resistance is large in the entire junction temperature range during use of the power semiconductor module 100.

  This selection is performed prior to the assembly process of the power semiconductor module. In addition, various characteristics of the element are measured and selected. Specifically, the static avalanche voltage Vavs2 of the SiC-SBD2 is measured using a curve dresser that is a withstand voltage measuring device. The dynamic avalanche voltage Vavd of the Si-IGBT 1 is measured using a turn-off device that simulates an inverter circuit. Further, the static avalanche withstand capability of SiC-SBD2 is measured by using a device that can flow a large current at a high voltage with a pulse. These measurements are performed to select an element.

  The dynamic avalanche voltage Vavd generated by the floating inductance of the circuit wiring when the Si-IGBT1 is turned off is suppressed by the static avalanche voltage Vavs2 of the SiC-SBD2, and the dynamic avalanche current flowing through the Si-IGBT1 is commutated to the SiC-SBD2. To do. Since SiC-SBD2 is designed to have a high static avalanche resistance (confirmed by measurement), SiC-SBD2 does not break. Even when an overvoltage such as a surge voltage is applied to the power semiconductor module 100, the SiC-SBD2 is not destroyed because the static avalanche resistance of the SiC-SBD is designed to be high.

  2A and 2B are schematic views showing a method for improving the static avalanche resistance of SiC-SBD. FIG. 2A is a plan view of the main part of the chip, and FIG. 2B is a cross-sectional view of the main part of the chip. is there. The static avalanche withstand capability is a withstand capability in which the element is not destroyed due to loss generated when the avalanche current Iav flows, and is usually represented by the product of the avalanche current Iav and its energization time. As shown in FIG. 5A, in the design in which the avalanche current Iav flows through the breakdown voltage structure 16 at the end 15a of the chip 15, the avalanche current Iav flows in a concentrated manner at the corner portion 17 of the chip 15 to increase the current density. It becomes easy to destroy. That is, the static avalanche resistance is small. As shown in FIG. 2B, the avalanche current Iav is designed not to flow through the breakdown voltage structure 16 and to flow through the entire active region 18 inside the chip 15. With this design, the current density of the avalanche current Iav flowing through the SiC-SBD 2 is reduced, and the static avalanche resistance can be increased even if the thickness of the substrate is reduced. Further, the on-voltage can be reduced by making the drift layer thinner. Therefore, in SiC-SBD2, even if SiC-SBD2 and an external lead-out terminal are connected by a bonding wire, the power cycle tolerance can be increased.

  FIG. 3 is a schematic diagram showing the relationship between the junction temperature and the dynamic avalanche voltage Vavd of Si-IGBT1 and the static avalanche voltage Vavs2 of SiC-SBD2. These data were obtained experimentally. Moreover, TL of the code | symbol in a figure is minimum junction temperature. Here, an example in which TL is −40 ° C. is given, but depending on the element design, it may be −50 ° C. or lower.

  The junction temperature dependence of the static avalanche voltage Vavs2 of SiC-SBD2 becomes gentler than the dynamic avalanche voltage Vavd of Si-IGBT1. Moreover, both the dynamic avalanche voltage Vavd of Si-IGBT1 and the static avalanche voltage Vavs2 of SiC-SBD2 increase as the junction temperature Tj increases.

FIG. 4 is a schematic diagram for explaining a static avalanche voltage. The vertical axis is current and the horizontal axis is voltage. When a voltage is applied to the element, a leakage current flows. When the applied voltage is increased and the applied voltage reaches an electric field strength (about 5 × 10 ⁵ V / cm for silicon) that causes an avalanche (when the rising voltage is reached), electrons are generated by colliding with the lattice. The number of currents increases like an avalanche, and the leakage current suddenly rises to become an avalanche current. The voltage through which this avalanche current flows is the static avalanche voltage. The loss that the element can withstand the avalanche current, the static avalanche voltage, and the loss (WS) that occurs at the time when no breakdown occurs even when the avalanche current flows is the avalanche resistance.

  FIG. 5 is a schematic diagram for explaining the Si-IGBT dynamic avalanche voltage Vavd and the SiC-SBD static avalanche voltage Vavs2. A collector current Ic is passed through the Si-IGBT 1 through the inductance. When the Si-IGBT 1 is turned off, the collector current Ic decreases. In the process of decreasing the collector current Ic (turn-off process), a voltage is generated by L × (di / dt). When this voltage increases, the Si-IGBT 1 enters an avalanche (breakdown), and becomes a constant voltage while flowing an avalanche current. This constant voltage is referred to as a dynamic avalanche voltage Vavd or a clamp voltage. The dynamic avalanche voltage Vavd is lower than the static avalanche voltage Vavs1.

  However, since the static avalanche voltage Vavs2 of SiC-SBD2 is lower than the dynamic avalanche voltage Vavd of Si-IGBT1, the collector current Ic flows as the avalanche current of SiC-SBD2.

  Note that, as a measure for reducing the static avalanche voltage Vavs2 of SiC-SBD2, the impurity concentration and thickness of the epitaxial layer may be controlled. That is, it is preferable to reduce the thickness of the epitaxial layer, reduce the specific resistance (increase the impurity concentration), or both.

  Next, the relationship between the static avalanche resistance of SiC-SBD2 and the loss (WS) generated in the dynamic avalanche period (application time in the figure) generated at the turn-off of Si-IGBT1 will be described.

  When the collector current Ic at the turn-off of the Si-IGBT 1 decreases linearly, a loss (WS) determined by Ic × Vc ÷ 2 × application time occurs in the Si-IGBT 1. However, when the jumping voltage at the turn-off time of the Si-IGBT 1 reaches the static avalanche voltage Vavs2 of the SiC-SBD2, all the collector current Ic is commutated to the SiC-SBD2 and flows as an avalanche current. Therefore, the loss (WS) generated in the Si-IGBT 1 is consumed as a loss expressed by the product of the avalanche current, the static avalanche voltage, and the application time of the SiC-SBD 2.

  By making the static avalanche resistance of SiC-SBD2 larger than the loss (WS) generated in Si-IGBT1, destruction of SiC-SBD2 can be prevented. Therefore, it is preferable to select a SiC-SBD2 having a static avalanche resistance greater than the loss (WS) generated in the Si-IGBT1.

  Further, the static avalanche resistance of SiC-SBD2 decreases as the temperature increases, while the loss (WS) generated at the turn-off of Si-IGBT1 increases as the temperature increases. Therefore, by confirming that the static avalanche resistance of SiC-SBD2 is higher than the loss (WS) generated at the turn-off of Si-IGBT1 at the highest junction temperature in use, it is possible to achieve the full range of junction temperatures in use. It can be confirmed that the static avalanche resistance of SiC-SBD2 is larger than the loss (WS) generated at the turn-off of Si-IGBT1.

  FIG. 6 is a schematic diagram illustrating a mechanism in which the static avalanche voltage Vavs and the dynamic avalanche voltage Vavd increase as the temperature increases. Here, a Si crystal is taken as an example, but the same applies to a SiC crystal. First, the static avalanche voltage Vavs will be described.

  A voltage Vo is applied across the Si substrate 10. When the temperature of the Si substrate 10 rises, the vibration 12 of the crystal lattice 11 becomes intense. When this lattice vibration becomes intense, the distance D (mean free path) until the electrons 13 collide with the lattice 11 becomes short. Then, the electrons 13 cannot obtain sufficiently high energy before the collision. Therefore, even if the electrons 13 collide with the lattice 11, the electrons 13a restrained by the lattice 11 cannot be blown off, and avalanche hardly occurs. In order to cause avalanche in this state, it is necessary to further increase the applied voltage Vo. Therefore, the temperature dependence of the static avalanche voltage Vavs increases as the temperature increases.

  Next, the dynamic avalanche voltage Vavd will be described. This is because the number of electrons described above becomes extremely large (when a large current flows), and the electrons collide with the lattice, so that the electrons jump out of the lattice. The mechanism of popping out at this time is determined by the ionization rate peculiar to the crystal, and becomes a voltage lower than the static avalanche voltage. Also, according to experiments, the temperature dependence of the dynamic avalanche voltage Vavd increases as the temperature increases, as does the static avalanche voltage Vavs.

  Further, according to experiments, the temperature dependence of the static avalanche voltage Vavs2 of the SiC-SBD2 is smaller than the temperature dependence of the dynamic avalanche voltage Vavd of the Si-IGBT1.

  By selecting an element in which the static avalanche voltage Vavs2 of SiC-SBD2 is lower than the dynamic avalanche voltage Vavd of Si-IGBT1 at the minimum junction temperature TL shown in FIG. The static avalanche voltage Vavs2 can be made lower than the static avalanche voltage Vavs1 of the Si-IGBT1.

  Therefore, the static avalanche voltage Vavs2 of the SiC-SBD2 and the dynamic avalanche voltage Vavd of the Si-IGBT1 are measured at one point of the lowest temperature TL of the junction temperature in use, and the static avalanche voltage Vavs2 of the SiC-SBD2 is measured with the Si-IGBT1. If an element lower than the dynamic avalanche voltage Vavd is selected, the static avalanche voltage Vavs2 of the SiC-SBD2 can be made lower than the dynamic avalanche voltage Vavd of the Si-IGBT1 over the entire range of the junction temperature in use. The dynamic avalanche voltage Vavd generated when the Si-IGBT 1 is turned off is suppressed by the static avalanche voltage Vavs 1 of the Si-IGBT 1. Further, since the static avalanche voltage Vavs2 of the SiC-SBD2 is made lower than the dynamic avalanche voltage Vavd of the Si-IGBT1, the on-voltage of the SiC-SBD2 can be lowered. The ON loss is reduced due to the reduction of the ON voltage, and the power cycle tolerance of the SiC-SBD can be improved.

  In the above description, the example of the combination of Si-IGBT1 and SiC-SBD2 is given, but the present invention can also be applied to the combination of Si-MOSFET (MOS type field effect transistor) and SiC-SBD2.

  The SiC-SBD having a large static avalanche resistance is selected, and the static avalanche voltage of the SiC-SBD is made lower than the dynamic avalanche voltage of the Si-IGBT, thereby reducing the thickness of the drift layer of the SiC-SBD. Reduce the on-voltage. The ON loss is reduced due to the reduction of the ON voltage, and the power cycle tolerance of the SiC-SBD can be improved.

1 Si-IGBT
1a collector 1b emitter 2 SiC-SBD
2a Anode 2b Cathode 3 Collector Terminal 4 Emitter Terminal 5 Gate Terminal 10 Substrate 11 Crystal Lattice 12 Lattice Vibration 13 Electron 13a Bounced Electron 15 Chip 15a End 16 Withstand Voltage Structure 17 Corner 18 Active Region 100 Power Semiconductor Module Iav Avalanche Current Vavs1, Vavs2 Static avalanche voltage Vavd Dynamic avalanche voltage

Claims (4)

In a power semiconductor module having a switching element and a free-wheeling diode connected in reverse parallel to the switching element,
The switching elements are formed on a silicon substrate, the return diode is formed in wide bandgap substrate, static avalanche voltage of the freewheeling diode in the entire range of the junction temperature during use of a low Ku than the dynamic avalanche voltage of the switching element The power semiconductor module is characterized in that the avalanche resistance of the freewheeling diode is larger than the loss generated during the dynamic avalanche period when the switching element is turned off. The power semiconductor module according to claim 1 , wherein the wide band gap substrate is a semiconductor substrate made of silicon carbide. 3. The power semiconductor module according to claim 1, wherein the switching element is an insulated gate bipolar transistor or a MOS field effect transistor, and the freewheeling diode is a Schottky barrier diode. The power semiconductor module according to any one of claims 1 to 3, wherein the reflux diode is connected to an external lead-out terminal by a bonding wire.

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