JP6007578B2 - Power semiconductor module and assembly method thereof - Google Patents

Description

  The present invention relates to a power semiconductor module having a switching element such as an IGBT (insulated gate bipolar transistor) and a freewheeling diode connected in reverse parallel to the switching element, for example, a Schottky barrier diode.

  The fields where power semiconductor modules are used range from home appliances to electric railways, electric cars, industrial robots, and power systems. As the usefulness of power semiconductor devices expands, improvement in performance is expected, and higher frequency, smaller size, and higher power are increasingly desired.

  Many of the power semiconductor modules used in these fields are used in conversion circuits such as AC-DC conversion, DC-AC conversion, and DC-DC conversion. In these power semiconductor modules, for example, switching elements such as MOSFETs (MOS field effect transistors) and IGBTs (insulated gate bipolar transistors) and FWDs which are free-wheeling diodes connected in antiparallel with these switching elements are mounted. Has been.

  FIG. 6 is a single-phase bridge inverter circuit diagram. This is an example of a conventional inverter circuit, and portions 6A, 6B, 6C, and 6D surrounded by broken lines indicate power semiconductor modules.

  In this example, each power semiconductor module 6A, 6B, 6C, 6D includes one free-wheeling diode (FWD) 7A, 7B, 7C, 7D and one switching element (IGBT in this example) 3A, 3B, 3C, 3D. Are installed in pairs. The free-wheeling diode is connected in antiparallel to each IGBT that is a switching element. Reference numeral 54 in the figure is a load having an inductance. Reference numeral 55 denotes a DC power source.

  When performing DC-AC conversion using an inverter circuit including a switching element such as IGBT or MOSFET having a self-extinguishing function, a PWM (pulse width modulation) method is generally used.

  FIG. 7 is an output waveform diagram to the load when DC-AC conversion is performed by the PWM method using the single-phase bridge inverter circuit of FIG. In the PWM method, the square pulse waveform of the gate signal of the switching element is modulated so that the load voltage becomes an AC waveform when viewed on a time average basis. When a pulse voltage in which the pulse width in the positive direction is modulated is output to the load 54 by the on / off operation of the IGBTs 3A and 3D, a sine wave as shown by a solid line Vm in FIG. Is output to the load. However, during this operation period (TAD), the IGBTs 3B and 3C which are switching elements are in an OFF state. Next, a pulse voltage in the negative direction is output to the load 54 by the on / off operation of the IGBTs 3B and 3C, and a half wave of a sine wave corresponding to the remaining half cycle (TBC) is output to the load.

  During the pulse operation period of the IGBT 3A and 3D in FIG. 6, for example, when the IGBT 3A is turned off from the on state, the collector voltage of the IGBT 3A is, as shown in FIG. 8, due to the floating inductance of the circuit wiring connected to the IGBT 3A. The dynamic avalanche voltage Vavd0 (clamping voltage) jumps to the dynamic avalanche voltage Vavd0 (clamping voltage). Thereafter, the collector voltage of the IGBT 3A is held at the power supply voltage. In the figure, Ic is the collector current of the IGBT, and Vc is the collector voltage.

Patent Document 1 describes an example in which the FWD in FIG. 6 is composed of two SiC-SBDs connected in series to reduce reverse recovery loss generated in the FWD.
In the following description, Si is silicon, SiC indicates silicon carbide, a device formed on the silicon substrate is indicated by Si, and a device formed on the silicon carbide substrate is indicated by SiC. SBD is a Schottky barrier diode. That is, Si-IGBT is an IGBT formed on a Si substrate, and SiC-SBD is an SBD formed on a SiC substrate. Furthermore, as described above, the FWD (free wheeling diode) is a freewheeling diode, here an SBD.

  In Patent Document 2, the on-resistance, switching speed, and temperature characteristics are improved rather than using a Si-switching element in which a DC-DC converter is composed of SiC-SIT (electrostatic induction transistor) and SiC-Di (diode). An example in which the bonding temperature is 160 ° C. to 300 ° C. is described.

  Patent Document 3 describes an example in which Si-FWD and SiC-FWD are connected in series, and the temperature characteristics of Si-FWD are canceled by the temperature characteristics of SiC-FWD to prevent thermal runaway of Si-FWD.

  Patent Document 4 describes an example in which the temperature rise of a chip can be halved by using SiC-FWD as compared with the case of Si-FWD.

Japanese Patent No. 4559477 JP 2006-187147 A ([0054] to [0056]) Japanese Patent No. 4808290 ([0033], [0067]) Japanese Patent No. 4722229 ([0052])

  FIG. 9 is a circuit diagram of one phase 30 of a conventional inverter. Here, one phase 30 means a circuit in which an upper arm and a lower arm are connected in series. When a module is formed by combining a device formed on the Si substrate and a device formed on the SiC substrate, the power semiconductor module is usually manufactured by matching the voltage rating of the Si-IGBT 31 and the voltage rating of the SiC-SBD 32.

  However, even if the voltage ratings are matched, the static avalanche voltage designed to be about 1.1 to 1.2 times higher than the voltage rating (usually referred to as an avalanche voltage) is different between the two. When the static avalanche voltage of the SiC-SBD 32 is low, the surge voltage or the dynamic avalanche voltage generated by the product of the stray inductance (L) of the inverter circuit and the fall of the collector current Ic (di / dt) when the Si-IGBT 31 is turned off. (Clamp voltage) is suppressed by the static avalanche voltage of the SiC-SBD 32, and an avalanche current flows through the SiC-SBD 32.

  Normally, the avalanche resistance of the SiC-SBD 32 is lower than the avalanche resistance of the Si-IGBT 31. Therefore, when this surge voltage or the dynamic avalanche voltage of the Si-IGBT 31 is applied to the SiC-SBD 32, the SiC-SBD 32 may be destroyed. Note that the avalanche resistance is a resistance that does not break due to a loss generated when the element enters the avalanche. In the figure, P is a positive terminal, N is a negative terminal, and M is an intermediate potential terminal.

  Moreover, in patent document 1-patent document 4, when the arm of an inverter circuit is comprised with the combination of Si-switching element and SiC-freewheeling diode (FWD), the static avalanche voltage of SiC-freewheeling diode is set to Si-switching element. There is no mention of preventing destruction of the SiC-freewheeling diode over the full range of junction temperatures in use by selecting an element higher than the static avalanche voltage.

  The object of the present invention is to solve the above-mentioned problems and provide a power semiconductor module capable of preventing the destruction of the SiC-freewheeling diode when the surge voltage or the dynamic avalanche voltage of the Si-switching element is applied to the SiC-freewheeling diode. It is to be.

In order to achieve the above object, according to the first aspect of the present invention, in a power semiconductor module having a switching element and a free-wheeling diode connected in reverse parallel to the switching element, the switching element Is formed on a silicon substrate, the freewheeling diode is formed on a wide band gap substrate, the static avalanche voltage of the freewheeling diode is higher than the static avalanche voltage of the switching device at the highest junction temperature according to the device design, and is in use The static avalanche voltage of the freewheeling diode is configured to be higher than the static avalanche voltage of the switching element in the entire junction temperature range.

According to the invention described in claim 2, it is preferable that in the invention described in claim 1, the wide band gap substrate is a semiconductor substrate made of silicon carbide.
According to a third aspect of the present invention, in the first aspect, the switching element is an insulated gate bipolar transistor or a MOS field effect transistor, and the free wheel diode is a Schottky. It may be a barrier diode.

  According to the present invention, the SiC-FWD (SiC-SBD) static avalanche voltage is higher than the static avalanche voltage of the Si-switching element (Si-IGBT or Si-MOSFET) over the entire range of junction temperatures in use. -A power semiconductor module is comprised using FWD. With this configuration, even if a surge voltage or a dynamic avalanche voltage of the Si-switching element is applied to the SiC-FWD in the entire range of the junction temperature in use, the static avalanche voltage of the SiC-SBC is higher than this voltage. SiC-SBD does not break.

It is a circuit block diagram of the power semiconductor module 100 which concerns on one Example of this invention. It is a figure which shows the relationship between static avalanche voltage Vavs1, Vavs2 of Si-IGBT1 and SiC-SBD2, and junction temperature. It is a schematic diagram explaining a static avalanche voltage. It is a schematic diagram explaining the dynamic avalanche voltage Vavd. It is the schematic diagram explaining the mechanism by which the static avalanche voltage Vavs increases as the temperature increases. It is a single phase bridge inverter circuit diagram. FIG. 7 is an output waveform diagram to a load when DC-AC conversion is performed by a PWM method using the single-phase bridge inverter circuit of FIG. 6. It is a schematic diagram explaining the clamp voltage which generate | occur | produces at the time of turn-off of IGBT3A. It is a circuit diagram of one phase 30 of the conventional inverter.

Embodiments will be described in the following examples.
<Example>
FIG. 1 is a circuit configuration diagram of a power semiconductor module 100 according to one embodiment of the present invention. Here, the power semiconductor module 100 is described as an example in which one set of anti-parallel circuits of switching elements and FWDs is stored in a package to form a 1 in 1 module. If two antiparallel circuits are connected in series and stored in one package, a 2-in-1 module is obtained. When two of the above antiparallel circuits are connected in series and two of these series circuits are connected in parallel and stored in one package, a 4-in-1 module is formed and a single-phase inverter is configured. Similarly, when three of the above series circuits are connected in parallel and stored in one package, a 6-in-1 three-phase inverter is configured.

  The power semiconductor module 100 includes a Si-IGBT 1 and a SiC-SBD 2 connected in reverse parallel thereto. The collector 1a of the Si-IGBT 1 and the cathode 2b of the SiC-SBD 2 are connected to each other and further connected to the collector terminal 3. The emitter 1 b of the Si-IGBT 1 and the anode 2 a of the SiC-SBD 2 are connected to each other and further connected to the emitter terminal 4.

  Although not shown, in this example, the collector 1a of the Si-IGBT 1 and the cathode 2b of the SiC-SBD 2 are joined to the circuit pattern of the insulating substrate and connected to the external lead-out terminal (collector terminal 3) via this circuit pattern. Is done. The emitter 1b of the Si-IGBT 1 and the anode 2a of the SiC-SBD 2 are connected by a bonding wire and connected to an external lead-out terminal (emitter terminal 4).

  The SiC-SBD2 is selected in which the static avalanche voltage Vavs2 of the SiC-SBD2 is higher than the static avalanche voltage Vavs1 of the Si-IGBT1 in the entire junction temperature range during use of the power semiconductor module 100.

This selection is performed prior to the assembly process of the power semiconductor module. In addition, various characteristics of the element are measured and selected.
Thereby, even if the dynamic avalanche voltage Vavd generated by the floating inductance of the wiring when the Si-IGBT1 is turned off is applied to the SiC-SBD2, the SiC-SBD2 static avalanche voltage Vavs2 is higher than the voltage Vavd. -SBD2 will not be destroyed. In addition, when an overvoltage such as a surge voltage is applied to the power semiconductor module 100, the SiC-SBD2 enters the avalanche because it is suppressed by the static avalanche voltage Vavs1 of the Si-IGBT1 that is lower than the static avalanche voltage Vavs2 of the SiC-SBD. Without destroying it.

Note that the dynamic avalanche voltage Vavd of the Si-IGBT 1 is lower than the static avalanche voltage Vavs 1 of the Si-IGBT 1.
FIG. 2 is a schematic diagram showing a relationship between the static avalanche voltages Vavs1 and Vavs2 of Si-IGBT1 and SiC-SBD2 and the junction temperature. For reference, the dynamic avalanche voltage Vavd of the Si-IGBT 1 is also indicated by a dotted line. These data were obtained experimentally. Also, the symbol To in the figure is the maximum junction temperature. Here, To is 175 ° C., but this value depends on the element design and may be 200 ° C. or 125 ° C.

  The junction temperature dependence of the static avalanche voltage Vavs2 of SiC-SBD2 is gentler than that of the static avalanche voltage Vavs1 of Si-IGBT1. Further, the static avalanche voltages Vavs1 and Vavs2 increase as the junction temperature Tj increases in both the Si-IGBT1 and the SiC-SBD2.

  FIG. 3 is a schematic diagram for explaining a static avalanche voltage. The vertical axis is current and the horizontal axis is voltage. When a voltage is applied to the element, a leakage current flows. When the applied voltage is increased and the applied voltage reaches the electric field strength that causes an avalanche (when the rising voltage is reached), the number of electrons generated when the electrons collide with the lattice increases avalanche and the leakage current suddenly increases. A rising avalanche current is generated, and the rising voltage is a static avalanche voltage.

  FIG. 4 is a schematic diagram illustrating the dynamic avalanche voltage Vavd. A collector current Ic is passed through the Si-IGBT 1 through the inductance. When the Si-IGBT 1 is turned off, the collector current Ic decreases. In the process of decreasing the collector current Ic (turn-off process), a voltage is generated by L × (di / dt). When this voltage increases, the Si-IGBT enters an avalanche (breakdown) and becomes a constant voltage while flowing an avalanche current. This constant voltage is referred to as a dynamic avalanche voltage Vavd or a clamp voltage. The dynamic avalanche voltage Vavd is lower than the static avalanche voltage Vavs1.

  FIG. 5 is a schematic diagram illustrating a mechanism in which the static avalanche voltage Vavs increases as the temperature increases. Here, a Si crystal is taken as an example, but the same applies to a SiC crystal.

  A voltage Vo is applied across the Si substrate 10. When the temperature of the Si substrate 10 rises, the vibration 12 of the crystal lattice 11 becomes intense. When this lattice vibration becomes intense, the distance D (mean free path) until the electrons 13 collide with the lattice 11 becomes short. Then, the electrons 13 cannot obtain sufficiently high energy before the collision. Therefore, even if the electrons 13 collide with the lattice 11, the electrons 13a restrained by the lattice 11 cannot be blown off, and avalanche hardly occurs. In order to cause avalanche in this state, it is necessary to further increase the applied voltage Vo. Therefore, the temperature dependence of the static avalanche voltage Vavs increases as the temperature increases. Further, according to experiments, the temperature dependence of SiC-SBD2 is smaller than the temperature dependence of Si-IGBT1.

  By selecting an element in which the static avalanche voltage Vavs2 of the SiC-SBD2 is higher than the static avalanche voltage Vavs1 of the Si-IGBT1 at the maximum junction temperature To shown in FIG. 2, the SiC-SBD2 is used over the entire range of the junction temperature in use. The static avalanche voltage Vavs2 can be made higher than the static avalanche voltage Vavs1 of the Si-IGBT1.

  Therefore, the static avalanche voltages Vavs2 and Vavs1 of the SiC-SBD2 and the Si-IGBT1 are measured at one point of the maximum temperature To of the junction temperature in use, and the static avalanche voltage Vavs2 of the SiC-SBD2 is measured as the static avalanche voltage of the Si-IGBT1. If an element higher than the voltage Vavs1 is selected, the static avalanche voltage Vavs2 of the SiC-SBD2 can be made higher than the static avalanche voltage Vavs1 of the Si-IGBT1 over the entire range of the junction temperature in use. Since the dynamic avalanche voltage Vavd generated when the Si-IGBT 1 is turned off is lower than the static avalanche voltage Vavs1 of the Si-IGBT1, the SiC-SBD2 having the static avalanche voltage Vavs2 higher than the static avalanche voltage Vavs1 of the Si-IGBT1 is destroyed. There is nothing. Even when a surge voltage or the like is applied, the voltage applied by the static avalanche voltage Vavs1 of the Si-IGBT1 is suppressed, so that the SiC-SBD2 is not destroyed. The static avalanche voltages Vavs1 and Vavs2 can be easily measured using a withstand voltage measuring device such as a curve tracer.

  As a measure for increasing the static avalanche voltage of SiC-SBD2, the impurity concentration and thickness of the epitaxial layer constituting the substrate may be controlled. That is, it is preferable to increase the thickness of the epitaxial layer, increase the specific resistance, or both.

  Since the dynamic avalanche voltage Vavd generated when the Si-IGBT 1 is turned off is lower than the static avalanche voltage Vavs2 of the SiC-SBC2 in the entire junction temperature range during use of the power semiconductor module 100, the SiC-SBD2 is destroyed. There is no. The applied voltage is suppressed by the static avalanche voltage Vavs1 and the dynamic avalanche voltage Vavd of the Si-IGBT1, and a voltage that does not reach the static avalanche voltage Vavs2 of the SiC-SBD2 is applied to the SiC-SBD2. Therefore, SiC-SBD2 is not destroyed.

  In the above description, the example of the combination of Si-IGBT1 and SiC-SBD2 is given, but the present invention can also be applied to the combination of Si-MOSFET (MOS type field effect transistor) and SiC-SBD2.

1 Si-IGBT
1a collector 1b emitter 2 SiC-SBD
2a anode 2b cathode 3 collector terminal 4 emitter terminal 5 gate terminal 10 substrate 11 crystal lattice 12 lattice vibration 13 electrons 13a blown electrons 100 power semiconductor module Iav avalanche current Vavs1, Vavs2 static avalanche voltage Vavd dynamic avalanche voltage

Claims (7)

In a power semiconductor module having a switching element and a free-wheeling diode connected in reverse parallel to the switching element,
The switching element is formed on a silicon substrate, the free wheel diode is formed on a wide band gap substrate,
The static avalanche voltage of the freewheeling diode is higher than the static avalanche voltage of the switching element at the maximum junction temperature according to the element design, and the static avalanche voltage of the freewheeling diode is the switching element over the entire range of the junction temperature in use. A power semiconductor module characterized by being higher than the static avalanche voltage.   The power semiconductor module according to claim 1, wherein the wide band gap substrate is a semiconductor substrate made of silicon carbide.   3. The power semiconductor module according to claim 1, wherein the switching element is an insulated gate bipolar transistor or a MOS field effect transistor, and the freewheeling diode is a Schottky barrier diode. Prepare the switching element formed on the silicon substrate,
  A method of assembling a power semiconductor module, comprising selecting a freewheeling diode having a static avalanche voltage higher than a static avalanche voltage of the switching element at a maximum junction temperature according to an element design and formed on a wide band gap substrate. 5. The method of assembling a power semiconductor module according to claim 4, wherein the static avalanche voltage of the freewheeling diode is higher than the static avalanche voltage of the switching element over the entire range of the junction temperature in use.   5. The method for assembling a power semiconductor module according to claim 4, wherein the wide band gap substrate is a semiconductor substrate made of silicon carbide.   5. The method of assembling a power semiconductor module according to claim 4, wherein the switching element is an insulated gate bipolar transistor or a MOS field effect transistor, and the freewheeling diode is a Schottky barrier diode.

Images