JP2023103681A - Manufacturing method of nitride semiconductor device - Google Patents

Abstract

To provide a manufacturing method for a nitride semiconductor device capable of realizing a P-type region with high concentration and small concentration variation.SOLUTION: A manufacturing method of a nitride semiconductor device includes the steps of ion-implanting an acceptor element into a nitride semiconductor such that the concentration of the acceptor element in the nitride semiconductor is 1×1019 cm-3 or more and 1×1021 cm-3 or less, forming a first protective film on a region of the nitride semiconductor into which the acceptor element has been ion-implanted, and subjecting the nitride semiconductor on which the first protective film is formed to a first heat treatment to form a P-type region in the nitride semiconductor. The first protective film is a crystalline film having such polarization as to induce electrons in the surface layer of the nitride semiconductor.SELECTED DRAWING: Figure 4

Description

The present invention relates to a method for manufacturing a nitride semiconductor device.

A nitride semiconductor device having a vertical MOS (Metal Oxide Semiconductor) structure is known (see Patent Document 1, for example). Further, in a nitride semiconductor device, P-type conductivity can be controlled by using magnesium (Mg) as a dopant (see, for example, Patent Document 2).

In order to achieve good ohmic contact in a nitride semiconductor device, it is necessary to selectively form a high-concentration P-type region in the nitride semiconductor. As a method for selectively forming the P-type region, ion implantation is desirable from the viewpoint of cost, productivity, and reliability. However, when Mg is ion-implanted into a nitride semiconductor at a high concentration and heat treatment is performed at a high temperature to activate Mg, Mg segregates in a rod shape at a high density. When Mg segregates in a rod shape at a high density, the Mg concentration decreases in regions other than the region where segregation occurs. Therefore, it has been difficult to form a P-type region with high concentration and small concentration variation by ion implantation (see, for example, Non-Patent Document 1).

JP 2019-096744 A JP 2014-086698 A

Kumar et. al. , J. Appl. Phys. 126 (2019) 235704.

In a nitride semiconductor device, it is desired to realize a P-type region with high concentration and small concentration variation.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a nitride semiconductor device capable of realizing a P-type region with high concentration and small concentration variation.

In order to solve the above problems, a method for manufacturing a nitride semiconductor device according to one aspect of the present invention includes ion-implanting an acceptor element into a nitride semiconductor to reduce the concentration of the acceptor element in the nitride semiconductor to 1×10. ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less; forming a first protective film on a region of the nitride semiconductor into which the acceptor element is ion-implanted; performing a first heat treatment on the formed nitride semiconductor to form a P-type region in the nitride semiconductor. The first protective film is a crystalline film having such polarization as to induce electrons in the surface layer of the nitride semiconductor.

According to the present invention, it is possible to provide a method of manufacturing a nitride semiconductor device capable of realizing a P-type region with high concentration and small concentration variation.

FIG. 1 is a plan view showing a configuration example of a GaN semiconductor device according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to an embodiment of the present invention. FIG. 3A is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the embodiment of the present invention in order of steps. FIG. 3B is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the embodiment of the present invention in order of steps. FIG. 3C is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the embodiment of the present invention in order of steps. FIG. 3D is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the embodiment of the present invention in order of steps. FIG. 3E is a cross-sectional view showing the manufacturing method of the GaN semiconductor device according to the embodiment of the present invention in order of steps. FIG. 4 is a flow chart showing the manufacturing method of the GaN semiconductor device according to the embodiment of the present invention in order of steps. FIG. 5 is a cross-sectional view schematically showing polarization of the first protective film and electrons induced in the surface layer of the GaN substrate. FIG. 6 is a band diagram of a surface layer portion in contact with a single-crystal AlN film in a GaN substrate, showing before heat treatment for activating an acceptor element, after heat treatment, and after heat treatment and after removal of the AlN film. , and shows the Fermi level Ef in . FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN.

Embodiments of the present invention are described below. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each device and each member, etc. are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it goes without saying that there are portions with different dimensional relationships and ratios between the drawings.

In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and the Y-axis direction are parallel to the surface 10a of the GaN substrate 10, which will be described later. The X-axis direction and the Y-axis direction are also referred to as horizontal directions. Also, the Z-axis direction is a direction perpendicular to the surface 10 a of the GaN substrate 10 . The X-axis direction, Y-axis direction and Z-axis direction are orthogonal to each other.

Also, in the following description, the positive direction of the Z-axis may be referred to as "up" and the negative direction of the Z-axis may be referred to as "down." "Upper" and "lower" do not necessarily mean perpendicular to the ground. That is, the "up" and "down" directions are not limited to the direction of gravity. "Upper" and "lower" are merely expedient expressions specifying relative positional relationships among regions, layers, films, substrates, etc., and do not limit the technical idea of the present invention. For example, if the paper surface is rotated 180 degrees, it goes without saying that "top" becomes "bottom" and "bottom" becomes "top".

In the following description, + and - attached to P and N indicating conductivity types indicate semiconductor regions with relatively high or low impurity concentrations, respectively, compared to semiconductor regions not marked with + and -. means However, even if the same P and P (or N and N) are attached to the semiconductor regions, it does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

<Embodiment>
(Configuration example)
FIG. 1 is a plan view showing a configuration example of a gallium nitride semiconductor device (an example of the "nitride semiconductor device" of the present invention; hereinafter referred to as a GaN semiconductor device) 100 according to an embodiment of the present invention. FIG. 2 is a cross-sectional view showing a configuration example of a GaN semiconductor device 100 according to an embodiment of the invention. FIG. 2 shows a cross section of the plan view shown in FIG. 1, the illustration of the gate pad 112 and the source pad 114 (see FIG. 2) is omitted in order to show the repeated structure of the vertical MOSFET 1. As shown in FIG.

As shown in FIGS. 1 and 2, the GaN semiconductor device 100 includes a plurality of vertical MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) 1 . In the GaN semiconductor device 100, vertical MOSFETs 1 are repeatedly provided in the Y-axis direction. One vertical MOSFET 1 is a repeating unit structure, and these unit structures are arranged side by side in one direction (for example, the X-axis direction).

As shown in FIGS. 1 and 2, the vertical MOSFET 1 includes an N-type drift region 12, a P-type well region 14, a P+ -type contact region 16 (an example of the "P-type region" of the present invention) and N + -type source region 18, a gate insulating film 21 provided on the surface 10a of the GaN substrate 10, and a gate insulating film 21 provided on the gate insulating film 21. a source electrode 25 provided on the front surface 10a side of the GaN substrate 10 and electrically connected to the contact region 16 and the source region 18; and a drift region 12 provided on the rear surface 10b side of the GaN substrate 10. and a drain electrode 27 electrically connected to the .

GaN substrate 10 includes an N+ type GaN single crystal substrate 11 and an N− type GaN layer (hereinafter also referred to as an epitaxial layer) epitaxially grown on GaN single crystal substrate 11 .

A donor (N-type impurity) contained in the GaN substrate 10 may be one or more elements of Si (silicon), Ge (germanium), and O (oxygen). Also, the acceptor element (P-type impurity) contained in the GaN substrate 10 may be one or more elements of Mg (magnesium), Ca (calcium), Be (beryllium), and Zn (zinc).

The GaN single crystal substrate 11 may be a low dislocation free-standing substrate having a threading dislocation density of less than 1×10 ⁷ cm ⁻² . Since the GaN single crystal substrate 11 is a low-dislocation self-supporting substrate, even when a large-area power device is formed on the GaN substrate 10, leakage current in the power device can be reduced. This makes it possible to manufacture power devices with a high non-defective product rate. Further, in the heat treatment included in the manufacturing process of the vertical MOSFET 1, it is possible to prevent the ion-implanted impurities from diffusing deeply along the dislocations.

A drift region 12, a well region 14, a contact region 16 and a source region 18 are provided in the epitaxial layers of the GaN substrate 10, respectively. The well region 14, the contact region 16, and the source region 18 are regions in which impurities are ion-implanted to a predetermined depth from the surface 10a of the GaN substrate 10, and the impurities are activated by heat treatment.

For example, a contact region 16 is provided on the surface side of the well region 14 . Well region 14 is a P-type region and contact region 16 is a P+ type region. The contact region 16 has a higher P-type impurity concentration than the well region 14 . The well region 14 and contact region 16 contain at least one of Mg and Be as an acceptor element.

For example, well region 14 and contact region 16 contain Mg as an acceptor element. The concentration of Mg in the well region 14 is 1×10 ¹⁶ cm ⁻³ or more and 3×10 ¹⁸ cm ⁻³ or less. The Mg concentration in the contact region 16 is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ⁻³ or less.

Drift region 12 is an N− type region and source region 18 is an N+ type region. The N-type impurity concentration is higher in the source region 18 than in the drift region 12 . The drift region 12 and the source region 18 contain, for example, Si as N-type impurities. For example, the N-type impurity concentration of the drift region 12 is the same as that of the epitaxial layer of the GaN substrate 10 . In this case, N-type impurity ions may not be implanted into the drift region 12 . The concentration of Si in the drift region 12 is 1×10 ¹⁵ cm ⁻³ or more and 1×10 ¹⁷ cm ⁻³ or less.

The source region 18 is provided on the surface side of the well region 14 . The source region 18 is formed by ion-implanting Si into the surface side of the well region 14 and activating Si by heat treatment. The Si concentration in the source region 18 is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²² cm ⁻³ or less.

An upper portion of the source region 18 is exposed on the surface 10a of the GaN substrate 10. As shown in FIG. The source region 18 has one side in the X-axis direction and the other side located on the opposite side in the X-axis direction. One side and bottom of source region 18 contact well region 14 and the other side of source region 18 contacts contact region 16 . One side of the source region 18 is located on the side of a region (hereinafter referred to as channel region) 141 where the channel of the vertical MOSFET 1 is formed. A channel of the vertical MOSFET 1 is formed in the well region 14 .

Contact region 16 is exposed at surface 10 a of GaN substrate 10 . The contact region 16 is in contact with the source region 18 on both sides in the X-axis direction and in contact with the well region 14 at the bottom. The well region 14, contact region 16 and source region 18 have a stripe shape extending in the Y-axis direction.

Drift region 12 functions as a current path between drain electrode 27 and channel region 141 . The contact region 16 is a region for making contact between the well region 14 and an electrode (for example, the source electrode 25). The contact region 16 also functions as a hole extraction path when the gate is turned off.

The gate insulating film 21 is, for example, a silicon oxide film (SiO ₂ film). The gate insulating film 21 is provided, for example, on the flat surface 10a.

The gate electrode 23 is provided above the channel region 141 with the gate insulating film 21 interposed therebetween. For example, the gate electrode 23 is of a planar type provided on the flat gate insulating film 21 . The gate electrode 23 is made of a material different from that of the gate pad 112 . The gate electrode 23 is made of impurity-doped polysilicon, and the gate pad 112 is made of Al or Al--Si alloy.

Source electrode 25 is provided on surface 10 a of GaN substrate 10 . Source electrode 25 is in contact with part of source region 18 and contact region 16 . The source electrode 25 may also be provided on the gate electrode 23 via an interlayer insulating film (not shown). The interlayer insulating film may cover the top and sides of the gate electrode 23 so that the gate electrode 23 and the source electrode 25 are not electrically connected.

The source electrode 25 is made of the same material as the source pad 114 . For example, the source electrode 25 made of Al or an Al—Si alloy also serves as the source pad 114 . Source electrode 25 may have a barrier metal layer between surface 10a of GaN substrate 10 and Al (or Al—Si). Titanium (Ti) may be used as the material for the barrier metal layer. The drain electrode 27 is provided on the back surface 10b side of the GaN substrate 10 and is in contact with the back surface 10b. The drain electrode 27 is also made of the same material as the source electrode 25 .

In FIG. 2, the gate, source and drain terminals are denoted by G, D and S, respectively. For example, when a potential higher than the threshold voltage is applied to the gate electrode 23 via the gate terminal G, an inversion layer is formed in the channel region 141 . When a predetermined high potential is applied to the drain electrode 27 and a low potential (for example, ground potential) is applied to the source electrode 25 in a state in which an inversion layer is formed in the channel region 141, the voltage from the drain terminal D to the source is applied. Current flows to terminal S. Further, when a potential lower than the threshold voltage is applied to the gate electrode 23, no inversion layer is formed in the channel region 141, and the current is cut off. Thereby, the vertical MOSFET 1 can switch the current between the source terminal S and the drain terminal D. FIG.

In the GaN semiconductor device 100 shown in FIGS. 1 and 2, the contact region 16 has a surface layer portion with little Mg segregation. A surface layer part is a part of the surface and its vicinity. The depth of the surface layer portion from the surface 10a is, for example, 1 nm or more and 30 nm or less. The Mg segregation density in the surface layer portion of the contact region 16 is lower than the Mg segregation density in a portion deeper than the surface layer portion (hereinafter referred to as a deep portion) of the contact region 16 .

This is achieved by previously covering the surface of the contact formation region 16' with the crystalline first protective film 60 when activating the Mg ion-implanted into the contact formation region 16' by heat treatment, as will be described later. Realized. Due to the polarization (spontaneous polarization) of the first protective film 60, electrons are induced in the surface layer of the contact forming region 16', and the Fermi level in the surface layer approaches the conduction band. This suppresses Mg segregation in the surface layer of the contact region 16 .

(Production method)
Next, a method for manufacturing the GaN semiconductor device 100 according to the embodiment of the invention will be described. 3A to 3E are cross-sectional views showing the manufacturing method of the GaN semiconductor device 100 according to the embodiment of the present invention in order of steps. FIG. 4 is a flow chart showing the manufacturing method of the GaN semiconductor device 100 according to the embodiment of the present invention in order of steps. 3A to 3E show the manufacturing method for one vertical MOSFET 1 out of the plurality of vertical MOSFETs 1 arranged repeatedly in the X-axis direction in order of steps. Also, the GaN semiconductor device 100 is manufactured by various apparatuses such as a film deposition apparatus, an exposure apparatus, an etching apparatus, an ion implantation apparatus, and a heat treatment apparatus. Hereinafter, these devices will be collectively referred to as manufacturing devices.

In FIG. 3A, a GaN substrate 10 has, for example, an N− type drift region 12, a P type well region 14, and an N+ type source region 18 formed therein. The manufacturing apparatus forms a P-type contact region 16 (see FIG. 2) at a position adjacent to the N + -type source region 18 on the surface 10a side of the GaN substrate 10 . Steps ST 1 to ST 6 shown in FIG. 4 are steps for forming the P-type contact region 16 .

First, the manufacturing apparatus forms a mask M1 on the surface 10a of the GaN substrate 10. As shown in FIG. The mask M1 is a SiO ₂ film or photoresist that is selectively removable with respect to the GaN substrate 10 . The mask M1 has an opening above a region (hereinafter referred to as a contact formation region) 16' where the contact region 16 is to be formed and has a shape that covers the other region above.

Next, the manufacturing apparatus ion-implants Mg as an acceptor element into the contact formation region 16' exposed from the mask M1 on the surface 10a side of the GaN substrate 10 (step ST1). In the ion implantation process of step ST1, the dose amount of Mg and the implantation energy (acceleration voltage) are adjusted so that the Mg concentration in the contact formation region 16′ is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. and other ion implantation conditions are set.

For example, in this ion implantation step, the implantation energy is set such that the depth from the surface 10a of the GaN substrate 10 to the implantation peak position is, for example, 1 nm or more and 30 nm or less. Further, in this ion implantation step, the dose amount of Mg to be ion-implanted is set so that the Mg concentration at the implantation peak position is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less. be.

Alternatively, in this ion implantation step, the Mg implantation energy is adjusted so that the Mg concentration in the entire contact formation region 16′ is 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less, not only at the injection peak position. and dose may be set. This ion implantation step may be performed by single-stage ion implantation with one condition of implantation energy, or may be performed by multi-stage ion implantation with a plurality of conditions of implantation energy.

In this ion implantation step, defects (damages) are caused in the crystal structure of the contact forming region 16' by the ion implantation of Mg. FIG. 3A schematically shows this defect as an implantation damage layer DL. After the ion implantation, the manufacturing equipment removes the mask M1 from the GaN substrate 10 .

Next, the manufacturing apparatus heat-treats the GaN substrate 10 (an example of the "second heat-treatment" of the present invention) to recover the damage caused on the surface side of the contact formation region 16' by the Mg ion implantation. As shown in FIG. 3B, this heat treatment removes the implantation damage layer DL (see FIG. 3A) generated in the contact formation region 16' (step ST2).

The maximum temperature of the heat treatment in step ST2 is lower than the maximum temperature of the activation heat treatment (step ST6), which will be described later, and is, for example, 600°C or higher and lower than 1300°C. An example of the conditions for the heat treatment in step ST2 is an atmosphere of N ₂ at 1 atm, a maximum temperature of 800° C., and a processing time at the maximum temperature of 5 minutes. Note that the atmosphere of the heat treatment in step ST2 is not limited to _N2 . This heat treatment may be performed under an atmosphere containing an inert gas other than _N2 (for example, an Ar atmosphere).

In the embodiment of the present invention, it is preferable to transfer the GaN substrate 10 in an inert gas atmosphere such as _N2 from the heat treatment process of step ST2 to the cleaning process of step ST3 described below. As a result, the surface 10a of the GaN substrate 10 can be prevented from being exposed to oxygen (O ₂ ), and the formation of a natural oxide film on the surface 10a of the GaN substrate 10 can be prevented.

Next, the manufacturing equipment cleans surface 10a of GaN substrate 10 (step ST3). This cleaning treatment is preferably performed in an inert gas atmosphere such as _N2 . As a result, the surface 10a of the GaN substrate 10 can be prevented from being exposed to oxygen (O ₂ ) during cleaning of the GaN substrate 10, and the formation of a natural oxide film on the surface of the GaN substrate 10 can be prevented. can do.

In the embodiment of the present invention, the GaN substrate 10 is transported in an inert gas atmosphere such as N ₂ from the cleaning process of step ST3 to the formation process of the first protective film 60 of step ST4 described below. is preferred. As a result, the surface 10a of the GaN substrate 10 can be prevented from being exposed to oxygen (O ₂ ), and the formation of a natural oxide film on the surface 10a of the GaN substrate 10 can be prevented. It becomes easy to directly form the first protective film 60 on the surface 10a of the GaN substrate 10 without interposing a natural oxide film as much as possible.

Next, as shown in FIG. 3C, the manufacturing apparatus forms the first protective film 60 on the surface 10a of the GaN substrate 10 (step ST4). A first protective film 60 is formed so as to be in direct contact with surface 10a of GaN substrate 10 . The first protective film 60 is a crystalline film having polarization (spontaneous polarization) that induces electrons on the surface 10a of the GaN substrate 10 and its vicinity (that is, surface layer portion). 3C and 3D schematically show the electrons induced in the surface layer portion of the GaN substrate 10 by the spontaneous polarization of the first protective film 60 as an induced electron layer EL.

The first protective film 60 has a polarization greater than that of GaN, and has a polarization greater than that of GaN even at the maximum temperature of the activation heat treatment (step ST6) described later. A single crystal AlN film can be used as the first protective film 60 having such characteristics. Also, the first protective film 60 may be an AlN film oriented in the c-axis direction and polycrystalline in the plane.

In addition, in the embodiment of the present invention, the first protective film 60 is not limited to the AlN film. The first protective film 60 may include an AlN film, an AlGaN film, or an AlInN film. That is, the first protective film 60 may be an AlGaN film made of a mixed crystal of an AlN film and a GaN film, or an AlInN film made of a mixed crystal of an AlN film and an InN film. Alternatively, the first protective film 60 is a laminated film in which an AlGaN film and an AlN film are laminated in this order from the GaN substrate 10 side, or an AlInN film and an AlN film are laminated in this order from the GaN substrate 10 side. It may be a laminated film. Including the AlGaN film or the AlInN film in the first protective film 60 may facilitate lattice matching between the GaN substrate 10 and the first protective film 60 .

The film thickness of the first protective film 60 is preferably thin from the viewpoint of having good crystallinity and polarization characteristics. As a method for forming the first protective film 60 thinly, there is an ALD (Atomic Layer Deposition) method. By the ALD method, it is possible to form a single-crystal AlN film as a thin film having a thickness of 2 nm or more and 50 nm or less as the first protective film 60 .

By forming the AlN film at a high temperature of 450° C. or higher, it is possible to grow an AlN film with excellent crystallinity (that is, the orientation is maintained) on GaN.

In addition, even when the AlN film is formed at a low temperature, plasma treatment is performed layer-by-layer (that is, while growing atomic layers one by one) so that the interface with the GaN substrate 10 has a high concentration. It is possible to grow AlN films that give rise to two-dimensional electron gas (2DEG). For example, it is possible to grow an AlN film at the interface with the GaN substrate 10 where the sheet carrier produces a 2DEG of 1×10 ¹³ cm ⁻² or more.

As an index of the crystallinity (orientation) of the AlN film, the half width of the X-ray diffraction peak of the crystal plane corresponding to the c-plane of GaN is preferably 320 arcsec or less.

Next, as shown in FIG. 3D, the manufacturing apparatus forms a second protective film 65 on the first protective film 60 (step ST5). The second protective film 65 is formed to have a thickness greater than or equal to that of the first protective film 60 . For example, the second protective film 65 is an amorphous ALN film. The film thickness of this AlN is 100 nm or more and 500 nm or less, and its formation method is the sputtering method or the ALD method.

Note that the second protective film 65 is not limited to the AlN film. The second protective film 65 is a nitride film, oxide film, oxynitride film containing at least one of B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta, W, or a high melting point film containing W or Ta. It may be a metal film.

Next, the manufacturing apparatus heat-treats the GaN substrate 10 on which the first protective film 60 and the second protective film 65 have been formed (an example of the "first heat treatment" of the present invention) to generate ions in the contact forming region 16'. The injected Mg is activated (step ST6). The maximum temperature of this heat treatment is, for example, 1300° C. or higher and 2000° C. or lower. As a result, a P+ type contact region 16 is formed on the surface 10a side of the GaN substrate 10, as shown in FIG. 3E.

As described above, the first protective film 60 is, for example, single crystal AlN. Since the first protective film 60 is a crystalline film, it is difficult to form a thick film. Since the first protective film 60 is a thin film, its mechanical strength is not high. However, in the embodiment of the present invention, the first protective film 60 is reinforced by forming the second protective film 65 on the first protective film 60 . By performing the activation heat treatment in step ST6 in this reinforced state, the possibility of cracking or the like occurring in the first protective film 60 is reduced (compared to the case where the second protective film 65 is absent).

Further, in the embodiment of the present invention, the second protective film 65 is formed on the first protective film 60 to increase the thickness of the entire protective film, so that the surface of the GaN substrate 10 is not affected during the activation heat treatment in step ST6. This prevents nitrogen element (N) from escaping from 10a.

Next, the manufacturing equipment sequentially removes the second protective film 65 and the first protective film 60 from the surface 10a of the GaN substrate 10 (step ST7). As a result, electrons induced in the surface layer of the GaN substrate 10 (induced electron layer EL) are eliminated.

Next, the manufacturing equipment forms the gate insulating film 21 (see FIG. 2) on the GaN substrate 10 . Next, the manufacturing equipment forms the gate electrode 23 (see FIG. 2) and the source electrode 25 (see FIG. 2). Next, the manufacturing equipment forms an interlayer insulating film (not shown) on surface 10 a of GaN substrate 10 so as to cover gate electrode 23 and source electrode 25 . Next, the manufacturing equipment forms a gate pad 112 (see FIG. 2) electrically connected to the gate electrode 23 and a source pad 114 (see FIG. 2) electrically connected to the source electrode 25 . After that, the manufacturing apparatus forms the drain electrode 27 (see FIG. 2) on the back surface 10b of the GaN substrate 10. Next, as shown in FIG. Through such steps, the GaN semiconductor device 100 including the vertical MOSFET 1 is completed.

(electron induction)
FIG. 5 is a cross-sectional view schematically showing polarization of the first protective film 60 and electrons induced in the surface layer of the GaN substrate 10. As shown in FIG. The first protective film 60 is, for example, a single crystal AlN film and has a larger polarization than GaN. As a result, electrons e are induced in the surface layer of the GaN substrate 10 when the first protective film 60 contacts the surface 10a of the GaN substrate 10, as shown in FIG. The single-crystal AlN film has a larger polarization than GaN even at the maximum temperature of the activation heat treatment in step ST6 of FIG.

(Fermi level of surface layer of GaN substrate)
FIG. 6 is a band diagram of a surface layer portion in contact with a single-crystal AlN film in a GaN substrate, showing before heat treatment for activating an acceptor element, after heat treatment, and after heat treatment and after removal of the AlN film. , and shows the Fermi level Ef in . Note that Mg is ion-implanted into the GaN shown in FIG. 6 as an acceptor element.

Before heat treatment Ef (with AlN film) in FIG. 6 is the Fermi level of the surface layer of the GaN substrate before the heat treatment for activating Mg and when the surface of the GaN substrate is in contact with the single-crystal AlN film. Ef is shown. In this state, electrons are induced in the surface layer of the GaN substrate due to the polarization of the single-crystal AlN film, so the Fermi level Ef of the GaN substrate is positioned close to the conduction band Ec.

After heat treatment Ef (with AlN film) in FIG. 6 is the Fermi level of the surface layer of the GaN substrate after the heat treatment for activating Mg and when the surface of the GaN substrate is in contact with the single-crystal AlN film. Ef is shown. In this state, the activation of Mg makes the GaN substrate p-type, so the Fermi level Ef of the GaN substrate approaches the valence band Ev.

After heat treatment Ef (after removal of AlN film) in FIG. is shown. In this state, the induction of electrons due to the polarization of the AlN film is canceled, so the Fermi level Ef of the GaN substrate approaches the valence band Ev.

(Suppression of Mg segregation by controlling Fermi level)
FIG. 7 is a graph showing the relationship between the formation energy of Mg acceptors in GaN and the Fermi level of GaN. This graph is data calculated by first-principles calculation. The horizontal axis of FIG. 7 indicates the Fermi level Ef (eV), and the vertical axis of FIG. 7 indicates energy (eV). The solid line (a) in FIG. 7 shows the relationship between the formation energy of Mg acceptors (that is, the energy required to introduce Mg into the Ga sites of GaN) and the Fermi level Ef of GaN. A dashed line (b) in FIG. 7 shows the relationship between the energy required for Ga to enter between lattices of GaN and the Fermi level Ef of GaN.

In FIG. 7, the closer the Fermi level Ef is to 0 (eV) (that is, the closer the Fermi level Ef is to the valence band and the closer the conductivity type of GaN is to the P-type), the greater the Mg acceptor formation energy. . Also, the closer the Fermi level Ef is to 0 (eV), the smaller the energy required for Ga to enter between lattices of GaN.

From the graph of FIG. 7, it can be seen that the closer the Fermi level Ef of GaN is to the valence band and the closer the conductivity type of GaN is to the P-type, the more difficult it is for Mg to be activated and to function as an acceptor. In other words, the closer the Fermi level Ef of GaN is to the conduction band and the closer the conductivity type of GaN is to the N-type, the easier it is for Mg to be activated and to function as an acceptor.

In the embodiment of the present invention, when the heat treatment for activating Mg is performed, the surface of the contact forming region 16' is treated so as to induce electrons on the surface 10a of the GaN substrate 10 and its vicinity (that is, the surface layer portion). contact with the crystalline first protective film 60 having good polarization. Due to the polarization of the first protective film 60, electrons are induced in the surface layer portion of the contact formation region 16', and the Fermi level Ef is positioned close to the conduction band Ec. Since the heat treatment for activating Mg is performed in this state, in the surface layer portion of the contact region 16, Mg is easily activated and easily functions as an acceptor.

(Effect of Embodiment)
As described above, in the method for manufacturing the GaN semiconductor device 100 according to the embodiment of the present invention, Mg is ion-implanted into the GaN substrate 10 so that the Mg concentration in the GaN substrate 10 is 1×10 ¹⁹ cm ⁻³ or more and 1×. forming ^a first protective film 60 on the contact forming region 16' implanted ^with Mg ions in the GaN substrate 10; and forming the first protective film 60 on the GaN substrate. and forming a P+ type contact region 16 in the GaN substrate 10 by subjecting the substrate 10 to heat treatment for Mg activation. The first protective film 60 is a crystalline film (for example, a single crystal AlN film) having such polarization as to induce electrons in the surface layer of the GaN substrate 10 .

According to this, due to the polarization of the first protective film 60, electrons are induced in the surface layer portion of the contact formation region 16', and the Fermi level Ef approaches the conduction band. Further, when the depth of the contact formation region 16' from the surface 10a is sufficiently shallow, electrons are induced not only in the surface layer portion of the contact formation region 16' but also in the entire depth direction of the contact formation region 16'. The Fermi level Ef approaches the conduction band throughout the depth direction.

Thereby, in the contact formation region 16', Mg is easily activated and easily functions as an acceptor, so segregation of Mg is suppressed. Variation in Mg concentration due to segregation can be suppressed. As a result, the contact region 16 with high concentration and small concentration variation can be realized.

That is, in the embodiment of the present invention, as the first protective film 60, a crystal having polarization such as AlN is grown on the surface of GaN (Ga surface). Due to the polarization difference between AlN and GaN, electron carriers are induced at the interface between AlN and GaN. This corresponds to keeping the Fermi level of the surface layer of GaN on the conduction band side, and Mg substituted for the Ga site is stabilized in the surface layer of GaN. As a result, the segregation of Mg can be suppressed without controlling the conductivity of the first protective film 60, and the P+ type contact region 16 can be formed with a high concentration of Mg.

As a comparative example of the present invention, after epitaxial growth of GaN, AlN is continuously grown on GaN by MOCVD or the like, and Mg is ion-implanted into GaN at a high concentration using the AlN layer as a through film. In the method of this comparative example, since Mg ion implantation is performed after AlN growth, the AlN crystal is damaged. AlN with damaged crystals cannot induce electrons in the surface layer of GaN during heat treatment for activating Mg, so it is difficult to suppress the segregation of Mg.

(Other embodiments)
As noted above, the present invention has been described through embodiments and variations thereof, but the statements and drawings forming part of this disclosure should not be understood to limit the present invention. Various alternative embodiments and modifications will become apparent to those skilled in the art from this disclosure.

For example, in the above embodiments, the GaN semiconductor device 100 includes the vertical MOSFET 1 of planar structure. However, vertical MOSFETs are not limited to planar structures. The vertical MOSFET may have a trench gate structure. Also, the MOSFET provided in the GaN semiconductor device 100 may be a horizontal MOSFET in which current flows in the horizontal direction of the GaN substrate instead of the vertical MOSFET in which the current flows in the vertical direction of the GaN substrate.

In addition, in the GaN semiconductor device 100 of the present invention, the element having the P-type region (for example, contact region 16) with high concentration and small concentration variation is not limited to MOSFET, and other elements other than MOSFET (for example, bipolar transistor, PN diode, capacitor, resistor, etc.). The GaN semiconductor device 100 may be a power supply circuit, an inverter, or the like.

In this way, the present technology naturally includes various embodiments and the like that are not described here. At least one of various omissions, replacements, and modifications of components can be made without departing from the gist of the embodiments and modifications described above. Moreover, the effects described in this specification are only examples and are not limited, and other effects may also occur.

1 Vertical MOSFET
10 GaN substrate 10a front surface 10b back surface 11 GaN single crystal substrate 12 drift region 14 well region 16 contact region 16' contact formation region 18 source region 21 gate insulating film 23 gate electrode 25 source electrode 27 drain electrode 60 first protective film 65 second Protective film 100 GaN semiconductor device 112 Gate pad 114 Source pad 141 Channel region D Drain terminal DL Implantation damage layer Ec Conduction band Ef Fermi level EL Induced electron layer eV Fermi level Ev Valence band G Gate terminal M1 Mask S Source terminal

Claims (13)

a step of ion-implanting an acceptor element into a nitride semiconductor to set the concentration of the acceptor element in the nitride semiconductor to 1×10 ¹⁹ cm ⁻³ or more and 1×10 ²¹ cm ^{−3 or} less;
forming a first protective film on a region of the nitride semiconductor into which the acceptor element has been ion-implanted;
performing a first heat treatment on the nitride semiconductor on which the first protective film is formed to form a P-type region in the nitride semiconductor;
The method of manufacturing a nitride semiconductor device, wherein the first protective film is a crystalline film having polarization that induces electrons in a surface layer portion of the nitride semiconductor. 2. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said first protective film has a film thickness of 2 nm or more and 50 nm or less. 3. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said first protective film has an X-ray diffraction peak half width of 320 arcsec or less on a crystal plane corresponding to the c-plane of GaN. 4. The method of manufacturing a nitride semiconductor device according to claim 1, wherein the maximum temperature of said first heat treatment is 1300[deg.] C. or more and 2000[deg.] C. or less. 5. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said first protective film has a larger polarization than said nitride semiconductor at the maximum temperature of said first heat treatment. 6. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said first protective film includes an AlN film, an AlGaN film, or an AlInN film. 7. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said first protective film is formed by an ALD method. further comprising forming a second protective film on the first protective film;
The second protective film is a nitride film, oxide film, or oxynitride film containing at least one of B, Al, Si, Ga, Ti, Y, Zr, Hf, Ta, W, or a high melting point containing W or Ta. is a metal film,
8. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said first heat treatment is performed on said nitride semiconductor having said first protective film and said second protective film formed thereon. . 9. The step of subjecting the nitride semiconductor ion-implanted with the acceptor element to a second heat treatment having a lower maximum temperature than the first heat treatment before forming the first protective film. A method for manufacturing a nitride semiconductor device according to any one of Claims 1 to 3. 10. The method of manufacturing a nitride semiconductor device according to claim 9, wherein said second heat treatment is performed in an inert gas atmosphere. 11. The method of manufacturing a nitride semiconductor device according to claim 1, further comprising the step of cleaning said nitride semiconductor under an inert gas atmosphere before forming said first protective film. 12. The method of manufacturing a nitride semiconductor device according to claim 11, wherein from the step of cleaning said nitride semiconductor to the step of forming said first protective film, said nitride semiconductor is transported under an inert gas atmosphere. 13. The method of manufacturing a nitride semiconductor device according to claim 1, wherein said acceptor element includes at least one of Mg and Be.

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