JP2023062218A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device capable of securing visibility to a gate finger while reducing the potential difference between a plurality of source fingers.SOLUTION: A semiconductor device includes: a semiconductor substrate; a transistor including a plurality of source fingers arranged on the semiconductor substrate, a plurality of drain fingers arranged alternately with the source fingers on the semiconductor substrate, and a plurality of gate fingers provided between the adjacent source finger and drain finger on the semiconductor substrate; a gate wire connecting between the gate fingers; a drain wire connecting between the drain fingers; a source wire connecting ends of the source fingers; and a bridge wire disposed over at least one of the drain fingers and a plurality of lead-out wires extending from the respective drain fingers, and connecting between the other ends of the source fingers.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to semiconductor devices.

Examples of semiconductor devices suitable for amplifying signals in high frequency bands such as microwave bands, quasi-millimeter wave bands, and millimeter wave bands include field effect transistors (FETs) such as high electron mobility transistors (HEMTs). Field Effect Transistors) are known.

As an example of the field effect transistor, Patent Document 1 and Patent Document 2 describe a field effect transistor with a multi-finger structure. The field effect transistor described in Patent Document 1 includes a plurality of gate fingers arranged in parallel with each other, and source fingers and drain fingers arranged to face each other with the gate fingers interposed therebetween.

The field effect transistor described in Patent Document 2 includes a plurality of gate electrodes, a plurality of source electrodes, a plurality of drain electrodes, a ground electrode connecting the plurality of source electrodes, and a plurality of and a bridge wiring that connects the central portions of the source electrodes.

JP-A-8-172104 JP 2008-72027 A

In a field effect transistor having a multi-finger structure as described above, the source potential may vary from source finger to source finger due to variation in source inductance among a plurality of source electrodes. In such a case, the potential difference between the gate and the source varies, the uniform operation of the transistor is disturbed, and an unnecessary wave is generated in the field effect transistor, which is a so-called oscillation phenomenon.

In order to avoid the oscillation phenomenon, it is conceivable to maintain a plurality of source electrodes at the same potential by connecting them with each other by a bridge wiring, like the field effect transistor described in Patent Document 2. However, in the field effect transistor described in Patent Document 2, the gate electrode (gate finger) is covered with the bridge wiring, so the visibility of the gate finger is reduced. As a result, there is a risk of overlooking the discovery of defects in the manufacturing process. In addition, in products that require visual inspection during the manufacturing process, there is also the problem that it is difficult to visually inspect the gate fingers.

The present disclosure has been made in view of such problems, and an object of the present disclosure is to provide a semiconductor device capable of ensuring visibility of gate fingers while reducing the potential difference between a plurality of source fingers.

In order to solve the above-described problems, a semiconductor device according to one embodiment includes a semiconductor substrate, a plurality of source fingers arranged in a first direction on the semiconductor substrate, a plurality of source fingers on the semiconductor substrate, and a plurality of source fingers arranged on the semiconductor substrate. a transistor having a plurality of drain fingers alternately arranged in one direction and a plurality of gate fingers respectively provided between adjacent source fingers and drain fingers in a first direction on a semiconductor substrate; A gate wiring connecting gate fingers together, a drain wiring connecting a plurality of drain fingers together, a source wiring connecting ends of the plurality of source fingers in a second direction intersecting the first direction, and a plurality of drain fingers. and a bridge wiring arranged across at least one of a plurality of lead wirings extending in two directions from each of the plurality of drain fingers and connecting the other ends of the plurality of source fingers in the second direction.

According to the semiconductor device according to the embodiment of the present disclosure, it is possible to ensure the visibility of the gate fingers while reducing the potential difference between the plurality of source fingers.

FIG. 1 is a plan view showing the internal configuration of a high frequency amplifier including an amplifying element as a semiconductor device according to one embodiment. FIG. 2 is a plan view showing an enlarged part of the amplifying element 11 shown in FIG. FIG. 3 is a plan view showing an enlarged part of the transistor 13 shown in FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. FIG. FIG. 5 is a plan view showing an amplifying element 11X according to a comparative example. FIG. 6 is a plan view showing an amplifying element 11Y according to another comparative example. 7 is a cross-sectional view taken along line VII-VII in FIG. 6. FIG. FIG. 8 is a plan view showing an amplifying element 11A according to a modification. FIG. 9 is a plan view showing an amplifying element 11B according to another modification. FIG. 10 is a plan view showing an enlarged part of an amplifying element 11C according to still another modification.

[Description of Embodiments of the Present Disclosure]
First, the contents of the embodiments of the present disclosure will be listed and described. A semiconductor device according to one embodiment includes a semiconductor substrate, a plurality of source fingers arranged on the semiconductor substrate in a first direction, and a plurality of source fingers arranged alternately on the semiconductor substrate in the first direction. and a plurality of gate fingers provided between the source fingers and the drain fingers adjacent to each other in the first direction on the semiconductor substrate; and a gate wiring connecting the plurality of gate fingers. a drain wiring connecting the plurality of drain fingers together; a source wiring connecting ends of the plurality of source fingers in a second direction intersecting the first direction; a plurality of drain fingers; a bridge wiring arranged across at least one of the plurality of lead wirings extending in two directions and connecting the other ends of the plurality of source fingers in the second direction.

In this semiconductor device, a plurality of source fingers are connected to each other by bridge wiring. Therefore, the potential difference between multiple source fingers can be reduced. Also, one ends of the plurality of source fingers in the second direction are connected to each other by the source wiring, and the other ends of the plurality of source fingers in the second direction are connected to each other by the bridge wiring. Therefore, in the central portion of the transistor in the second direction, it is possible to realize a configuration in which the gate finger provided between the source finger and the drain finger is not covered with the bridge wiring. Therefore, it is possible to ensure the visibility of the gate finger.

In the semiconductor device according to one embodiment, the drain wiring has a plurality of first bus lines connecting two drain fingers adjacent to each other in the first direction, a width different from that of the first bus lines, and a plurality of first bus lines. and a second bus line connecting the bus lines. In a configuration in which the other ends of a plurality of source fingers are connected by a bridge wiring, the length (dimension in the second direction) of the output combining circuit tends to increase. When the length of the output combining circuit increases, the impedance in the output combining circuit also changes greatly, so it becomes necessary to greatly change the corresponding matching circuit. In contrast, in the above configuration, the length (dimension in the second direction) of the output combining circuit can be adjusted by making the width of one of the first bus lines and the second bus line smaller than the width of the other. Therefore, according to the above configuration, it is possible to reduce the degree of impedance change in the output combining circuit.

In the semiconductor device according to one embodiment, the width of the first bus line may be smaller than the width of the second bus line. In this case, compared to the case where the length of the output combining circuit is adjusted by making the width of the second bus line smaller than the width of the first bus line, it is possible to further reduce the degree of change in the impedance, and to combine the output. The extent to which the current density increases in the circuit can be reduced.

In the semiconductor device according to one embodiment, the width of the first bus line may be equal to or greater than the width of the bridge wiring. In this case, compared to the case where the width of the first bus line is smaller than the width of the bridge wiring, the current density in the first bus line can be reduced. In addition, the width of the bridge wiring can be made relatively small because the first bus line causes the source current to flow, while the bridge wiring only regulates the potential. By making the width of the bridge wiring equal to or smaller than the width of the first bus line, it is possible to reduce the degree of impedance change in the output synthesis circuit.

In the semiconductor device according to one embodiment, the semiconductor substrate may have an active region and an inactive region surrounding the active region, and the bridge wiring may be arranged on the inactive region. In this case, since the active region is not covered with the bridge wiring, the visibility of the gate finger of the active region can be sufficiently ensured.

In the semiconductor device according to one embodiment, the semiconductor substrate has an active region and an inactive region surrounding the active region, and the gate wiring connects ends of the plurality of gate fingers in the second direction. , the other ends of the plurality of gate fingers in the second direction and the other ends of the plurality of gate fingers in the second direction are located on the inactive regions, and the other ends of the plurality of source fingers in the second direction are: The bridge wiring may be connected at a position farther from the active region than the other ends of the plurality of gate fingers in the second direction. In this case, in the configuration in which the other end of the gate finger in the second direction is located on the inactive region, sufficient visibility of the gate finger can be ensured.

In the semiconductor device according to one embodiment, the bridge wiring does not have to overlap the plurality of gate fingers in plan view. In this case, the visibility of the gate finger can be sufficiently ensured.

In the semiconductor device according to one embodiment, the bridge wiring may overlap with the plurality of gate fingers in plan view. In this case, for example, the visibility of the gate fingers is ensured even in a configuration in which the bridge wiring overlaps with the plurality of gate fingers in a plan view, such as a plurality of gate fingers extending below the bridge wiring on the inactive region. can.

[Details of the embodiment of the present disclosure]
A specific example of a semiconductor device according to an embodiment of the present disclosure will be described below with reference to the drawings. The present disclosure is not limited to these examples, but is indicated by the scope of the claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of the claims. In the following description, the same reference numerals are given to the same elements or elements having the same function, and redundant description may be omitted. In the description, reference may be made to the XYZ orthogonal coordinate system shown in the drawings.

A semiconductor device according to one embodiment is, for example, an amplifying element used in a high-frequency amplifier. FIG. 1 is a plan view showing the internal configuration of a high frequency amplifier 1 including an amplifying element 11 according to an embodiment of the present disclosure. As shown in FIG. 1, the high-frequency amplifier 1 includes one input terminal 2, one output terminal 3, an amplifying element section 10, a branch circuit board 20, a combining circuit board 30, a matching circuit 40, and a matching circuit 50. . The high-frequency amplifier 1 includes two matching circuits 40 and 50, for example. Further, the amplifying element section 10 includes two amplifying elements 11 . The output of each amplifying element 11 is 30 W, for example, and the output of the entire amplifying element section 10 is 60 W, for example. A high-frequency amplifier 1 includes a package 4 that accommodates an amplification element section 10 , a branch circuit board 20 , a combining circuit board 30 , and matching circuits 40 and 50 .

Package 4 is made of metal and is connected to a reference potential. The planar shape of the package 4 is substantially rectangular. The package 4 has end walls 4c, 4d facing each other in a first direction and side walls 4a, 4b facing each other in a second direction. The first direction and the second direction intersect each other, and in one example are orthogonal to each other. In this embodiment, the first direction is the X-axis direction and the second direction is the Y-axis direction.

The package 4 has a rectangular flat bottom plate 4e. The bottom plate 4e extends along a plane defined by the Y-axis direction and the X-axis direction. The side walls 4a and 4b stand along a pair of sides (sides extending along the Y-axis direction) of the bottom plate 4e, and the end walls 4c and 4d stand along another pair of sides (sides extending along the X-axis direction) of the bottom plate 4e. It is set up along the side extending along the The package 4 further has a lid (not shown). The lid seals the upper opening formed by the side walls 4a, 4b and the end walls 4c, 4d.

The input terminal 2 is a wiring pattern made of metal, and inputs a high frequency signal from the outside of the high frequency amplifier 1 . The high-frequency signal is a signal based on a multi-carrier transmission system, and is formed by superimposing a plurality of signals having different carrier signal frequencies. The frequency band of the carrier signal is, for example, 500 MHz or less. The input terminal 2 is provided at the center of the end wall 4c in the X-axis direction and extends from the outside of the package 4 to the inside.

The amplifying element section 10 is arranged on the bottom plate 4e of the package 4 and substantially in the center of the package 4 in the Y-axis direction. Each amplifying element 11 of the amplifying element section 10 includes a semiconductor substrate 12, a transistor 13 provided on the semiconductor substrate 12, and a plurality of wirings. Transistor 13 is, for example, a field effect transistor (FET), and in one embodiment is a high electron mobility transistor (HEMT). The planar shape of the semiconductor substrate 12 is a rectangular shape whose longitudinal direction is the X-axis direction. The semiconductor substrate 12 extends along a plane defined by the Y-axis direction and the X-axis direction. The semiconductor substrate 12 has a pair of 12a and 12b (see FIG. 2) extending along the X-axis direction. The edge 12 a faces the input terminal 2 and the edge 12 b faces the output terminal 3 . For example, a plurality of transistors 13 are provided on the semiconductor substrate 12 .

FIG. 2 is a plan view showing an enlarged part of the amplifying element 11 shown in FIG. FIG. 3 is a plan view showing an enlarged part of the transistor 13 shown in FIG. As shown in FIGS. 2 and 3, the semiconductor substrate 12 has an active region R1 and inactive regions R2 and R3 provided around the active region R1. In each figure, for convenience of illustration, a slight gap is provided between the active region R1 and the inactive regions R2 and R3. in contact with

The active region R1 is a region that operates as a transistor. The inactive regions R2, R3 are electrically inactivated regions. The inactive regions R2 and R3 are provided for electrical isolation between the transistors 13 adjacent to each other and for limiting the operating region of the transistors 13 . The inactive region R2 is located on one side (input terminal 2 side in FIG. 1) of the active region R1 in the Y-axis direction. The inactive region R3 is located on the other side (output terminal 3 side in FIG. 1) in the Y-axis direction with respect to the active region R1. That is, the inactive region R2, the active region R1, and the inactive region R3 are arranged in this order along the Y-axis direction.

Transistor 13 has a plurality of source fingers 61 , a plurality of drain fingers 62 and a plurality of gate fingers 63 . A plurality of source fingers 61, a plurality of drain fingers 62, and a plurality of gate fingers 63 are conductors provided on the active region R1 and extending in the Y-axis direction. In this embodiment, one transistor 13 has five source fingers 61 , four drain fingers 62 and eight gate fingers 63 as an example.

A plurality of source fingers 61 are provided side by side in the X-axis direction on the active region R1 of the semiconductor substrate 12 . Each source finger 61 forms a source electrode 61 a on the back surface facing the semiconductor substrate 12 . Each source electrode 61a is located inside the active region R1 on the semiconductor substrate 12 . One end 61b of each source finger 61 in the Y-axis direction is located on the edge 12a side, and the other end 61c of each source finger 61 in the Y-axis direction is located on the edge 12b side. Each source finger 61 extends from one end to the other end of the active region R1 in the Y-axis direction.

The plurality of drain fingers 62 are arranged alternately with the plurality of source fingers 61 in the X-axis direction on the active region R1 of the semiconductor substrate 12 . Each drain finger 62 forms a drain electrode 62 a on the back surface facing the semiconductor substrate 12 . Each drain electrode 62a is located inside the active region R1 on the semiconductor substrate 12 . One end 62b of each drain finger 62 in the Y-axis direction is located on the edge 12a side, and the other end 62c of each drain finger 62 in the Y-axis direction is located on the edge 12b side. Each drain finger 62 extends from one end to the other end of the active region R1 in the Y-axis direction.

A plurality of gate fingers 63 are provided between the source fingers 61 and the drain fingers 62 adjacent to each other in the X-axis direction on the active region R1 of the semiconductor substrate 12 . The gate finger 63 and the source finger 61 adjacent to the gate finger 63 are arranged with a predetermined interval in the X-axis direction. Similarly, the gate finger 63 and the drain finger 62 adjacent to the gate finger 63 are arranged with a predetermined interval in the X-axis direction. Each gate finger 63 forms a gate electrode 63a (see FIG. 3) on the back surface facing the semiconductor substrate 12. As shown in FIG. One end 63b of each gate finger 63 in the Y-axis direction is located on the edge 12a side, and the other end 63c of each gate finger 63 in the Y-axis direction is located on the edge 12b side.

Each gate finger 63 extends from one end to the other end of the active region R1 in the Y-axis direction on the semiconductor substrate 12 and extends to the inactive regions R2 and R3. In other words, each of the plurality of gate fingers 63 has a portion located on the active region R1, a portion located on the inactive region R2, and a portion located on the inactive region R3. That is, each of the plurality of gate electrodes 63a also has a portion located on the active region R1, a portion located on the inactive region R2, and a portion located on the inactive region R3. In this embodiment, one end 63b of each gate finger 63 is located on the inactive region R2, and the other end 63c is located on the inactive region R3.

The plurality of wirings includes source wirings 64 , drain wirings 65 and gate wirings 66 . The source wiring 64 is a conductive wiring, and electrically connects the one ends 61b of the plurality of source fingers 61 in the Y-axis direction. Also, the source wiring 64 is electrically connected to a plurality of source pads 14 provided on the semiconductor substrate 12 . The source wiring 64 has a source bus line 64a and a plurality of connection wirings 64b. The source bus line 64a is provided on the inactive region R2 in the semiconductor substrate 12 and extends in the X-axis direction. The plurality of connection wirings 64b are respectively provided between the source bus lines 64a in the semiconductor substrate 12 and the ends 61b of the source fingers 61, and extend in the Y-axis direction. Each connection wiring 64 b electrically connects the source bus line 64 a and the source finger 61 .

The drain wiring 65 is a conductive wiring and electrically connects the other ends 62c of the plurality of drain fingers 62 to each other. Also, the drain wiring 65 is electrically connected to the drain pad 16 as a signal output terminal provided on the semiconductor substrate 12 . The drain wiring 65 has a plurality of intermediate bus lines 65a (first bus lines) and drain bus lines 65b (second bus lines). The number of intermediate bus lines 65a is half the number of drain fingers 62, for example.

Each intermediate bus line 65a electrically connects two drain fingers 62 adjacent in the X-axis direction. Each intermediate bus line 65a has a bus line portion 651a (first bus line), two lead portions 652a (lead wiring), and a lead portion 653a. The bus line portion 651a is provided on the inactive region R3 and extends in the X-axis direction. Each lead portion 652a is provided between the bus line portion 651a in the semiconductor substrate 12 and the other end 62c of the drain finger 62, and extends in the Y-axis direction from the other end 62c. Each lead portion 652 a electrically connects the bus line portion 651 a and the drain finger 62 . Each lead portion 653a is provided between the bus line portion 651a and the drain bus line 65b in the semiconductor substrate 12 and extends in the Y-axis direction. Each lead portion 653a electrically connects the bus line portion 651a and the drain bus line 65b. During operation of the high-frequency amplifier 1, a current corresponding to two drain fingers (that is, four gate fingers) flows through each lead-out portion 653a.

The drain bus lines 65b electrically connect the plurality of intermediate bus lines 65a. Also, the drain bus line 65 b is electrically connected to a plurality of drain pads 16 provided on the semiconductor substrate 12 . The drain bus line 65b has a bus line portion 651b (second bus line) and a lead portion 652b. The bus line portion 651b is provided on the inactive region R3 and extends in the X-axis direction. The bus line portion 651b has a width D2 (here, dimension in the Y-axis direction) different from the width D1 (here, dimension in the Y-axis direction) of the bus line portion 651a in the intermediate bus line 65a. Specifically, the width D1 is smaller than the width D2. In this embodiment, the width D1 is 15 μm and the width D2 is 35 μm. Each lead portion 652b is provided between the bus line portion 651b and the drain pad 16 on the semiconductor substrate 12 and extends in the Y-axis direction. Each lead portion 652 b electrically connects the bus line portion 651 b and the drain pad 16 . During the operation of the high-frequency amplifier 1, a current for all fingers (in this embodiment, four drain fingers and eight gate fingers) flows through the lead-out portion 652b.

The gate wiring 66 is a conductive wiring, and electrically connects the ends 63b of the plurality of gate fingers 63 to each other. The gate wiring 66 is also electrically connected to a gate pad (not shown) as a signal input terminal provided on the semiconductor substrate 12 . The gate wiring 66 is provided on the inactive region R2 on the semiconductor substrate 12 and is configured by a gate bus line extending in the X-axis direction. The gate wiring 66 is sandwiched in the Y-axis direction by some source fingers 61 (three source fingers 61 in this embodiment) and source bus lines 64a, and is sandwiched by some connection wirings 64b (in this embodiment, three source fingers 61). , and extend in the X-axis direction under the three connection wirings 64b). In other words, a portion of the connection wiring 64 b in the source wiring 64 has a portion overlapping with the gate wiring 66 .

The source pads 14 and the gate pads are alternately arranged on the inactive region R2 of the semiconductor substrate 12 along the edge 12a. The drain pads 16 are arranged on the inactive region R3 of the semiconductor substrate 12 along the edge 12b. Each source pad 14 is electrically connected to the bottom plate 4e (see FIG. 1) of the package 4 (see FIG. 1) through a via hole 15 penetrating through the amplifying element 11 in the thickness direction (here, Z-axis direction). , is used as a reference potential. Each amplifying element 11 amplifies the high frequency signal input to each gate pad and outputs the amplified high frequency signal from each drain pad 16 .

In the amplifying element 11, an input circuit to the transistor 13 is formed between the active region R1 and the edge 12a, and an output synthesizing circuit from the transistor 13 is formed between the active region R1 and the edge 12b. ing. As shown in FIG. 2, the length D3 of the output combining circuit (here, the dimension in the Y-axis direction) is determined by the position closest to the edge 12b in the Y-axis direction in the boundary of the active region R1 and the drain wiring 65. and the position farthest from the active region R1 in the Y-axis direction in the bus line portion 651b of the drain bus line 65b. In this embodiment, the length D3 is 85 μm.

Continuing, further reference is made to FIG. 4 is a cross-sectional view taken along line IV-IV in FIG. 3. FIG. As shown in FIGS. 2, 3 and 4, the amplifying element 11 further comprises a source airbridge 67. As shown in FIG. The source air bridge 67 is a conductive wiring included in the output combining circuit of the amplifying element 11, and electrically connects the plurality of source fingers 61 together. The source air bridge 67 has an air bridge wiring 671 (bridge wiring) and a plurality of connection wirings 672 .

Each connection wiring 672 extends along the Y-axis direction over the inactive region R3 from each of the other ends 61c of the plurality of source fingers 61 in the Y-axis direction. The air bridge wiring 671 is arranged on the inactive region R3 and extends in the X-axis direction. The air bridge wiring 671 is arranged across the plurality of lead portions 652 a and has an air bridge structure joined to each connection wiring 672 . The air bridge wiring 671 connects the other ends 61 c of the plurality of source fingers 61 in the Y-axis direction via each connection wiring 672 . As shown in FIG. 3, each connection wiring 672 extends to a position farther from the active region R1 than the other end 63c of each gate finger 63 in the Y-axis direction. Each connection wiring 672 is connected to the air bridge wiring 671 at a position farther from the active region R1 than the other end 63c of each gate finger 63 on the inactive region R3. In other words, the other end 61c of each source finger 61 is connected to the air bridge wiring 671 at a position farther from the active region R1 than the other end 63c of each gate finger 63 on the inactive region R3. That is, the air bridge wiring 671 is arranged at a position not overlapping with the plurality of gate fingers 63 in plan view. The width D4 (here, the dimension in the Y-axis direction) of the air bridge wiring 671 is less than or equal to the width D1 of the bus line portion 651a of the intermediate bus line 65a. In this embodiment, the width D4 is the same as the width D1, which is 15 μm.

The air bridge wiring 671 has a plurality of connection portions 67a and a plurality of relay portions 67b (see FIG. 4). The number of connecting portions 67a is the same as the number of source fingers 61. FIG. The plurality of connection portions 67a are portions that are joined to the plurality of connection wirings 672, respectively. The plurality of relay portions 67b are portions positioned between two connecting portions 67a adjacent to each other in the X-axis direction and connecting the two connecting portions 67a. The air bridge wiring 671 straddles the lead-out portion 652a at each relay portion 67b. Each of the plurality of relay portions 67b protrudes further from the semiconductor substrate 12 than the connection portion 67a, and is separated from the lead portion 652a.

Refer to FIG. 1 again. The branch circuit board 20 is arranged on the bottom plate 4 e of the package 4 . The branch circuit board 20 is arranged side by side with the input terminal 2 and the amplifying element section 10 along the Y-axis direction and positioned between the input terminal 2 and the amplifying element section 10 . The branch circuit board 20 has a substrate 21 made of ceramic and a branch circuit 22 provided on the main surface of the substrate 21 . The planar shape of the substrate 21 is, for example, a rectangle. The back surface of the substrate 21 faces the bottom plate 4 e of the package 4 . One short side 21c of the substrate 21 is located near the side wall 4a of the package 4, and the other short side 21d of the substrate 21 is located near the side wall 4b of the package 4. As shown in FIG. That is, the substrate 21 extends from near one end of the package 4 to near the other end in the X-axis direction.

Branch circuit 22 includes a wiring pattern 23 provided on the main surface of substrate 21 . The wiring pattern 23 is electrically connected to the input terminal 2 via the bonding wire 9a. A high-frequency signal is input to the wiring pattern 23 from the central portion of the substrate 21 in the X-axis direction. The wiring pattern 23 has a line-symmetrical shape with respect to the center line of the substrate 21 along the Y-axis direction. The wiring pattern 23 repeats bifurcation starting from the connection point with the bonding wire 9a, and finally reaches eight metal pads 23a. The eight metal pads 23a are arranged side by side along the long side 21b. The metal pads 23a adjacent to each other are connected to each other via film resistors to form a Wilkinson coupler. As a result, the input impedance of the amplifying element section 10 as viewed from the input terminal 2 is matched while ensuring the isolation between the plurality of gate pads of the amplifying element section 10 . In addition, only one film resistor 23b is shown in the drawing as a representative. The eight metal pads 23a are electrically connected to the matching circuit 40 via bonding wires 9b.

The matching circuit 40 is arranged on the bottom plate 4e of the package 4 and arranged between the branch circuit board 20 and the amplifying element section 10 in the Y-axis direction. The matching circuit 40 is, for example, a die capacitor and has a plurality of metal pads (not shown) on the main surface of the dielectric substrate. The number of metal pads is, for example, the same number as the metal pads 23a. A plurality of metal pads are arranged in a row along the X-axis direction. Each metal pad is electrically connected to the corresponding metal pad 23a through the bonding wire 9b, and is also electrically connected to the corresponding gate pad of the amplifying element section 10 through the bonding wire 9c. .

In the matching circuit 40, the inductance component by the bonding wires 9b and 9c and the capacitance of the metal pad connected between the node between these inductance components and the reference potential (bottom plate 4e) form a T-type filter circuit. is configured. The matching circuit 40 performs impedance conversion with this T-type filter circuit. Normally, in the amplifier element section 10, the impedance of the inside of the transistor viewed from the gate pad is different from the characteristic impedance (for example, 50Ω) of the transmission line. The matching circuit 40 converts this impedance to 50Ω from the input terminal 2 to the inside of the package 4 by the T-type filter circuit.

The matching circuit 50 is arranged on the bottom plate 4e of the package 4 and arranged between the amplifying element section 10 and the combining circuit board 30 in the Y-axis direction. Similar to the matching circuit 40, the matching circuit 40 is, for example, a parallel plate capacitor (die capacitor) and has a plurality of metal pads (not shown) on the main surface of the dielectric substrate. The number of metal pads is, for example, the same number as the metal pads 23a. A plurality of metal pads are arranged in a row along the X-axis direction. Each metal pad is electrically connected to the corresponding drain pad 16 of the amplifying element section 10 via the bonding wire 9d, and to the corresponding metal pad 33a (described later) of the composite circuit board 30 via the bonding wire 9e. ) are electrically connected.

Also in the matching circuit 50, the inductance component by the bonding wires 9d and 9e and the capacitance of the metal pad connected between the node between these inductance components and the reference potential (bottom plate 4e) form a T-type filter circuit. is configured. The matching circuit 50 performs impedance conversion with this T-type filter circuit. Normally, the impedance of the amplifier element section 10 looking into the inside of the transistor from the drain pad 16 is different from the characteristic impedance (for example, 50Ω) of the transmission line, and generally has a value smaller than 50Ω. The matching circuit 50 converts this impedance to 50Ω from the output terminal 3 to the inside of the package 4 by the T-type filter circuit.

The composite circuit board 30 is arranged on the bottom plate 4 e of the package 4 . The composite circuit board 30 is arranged side by side with the amplifying element section 10 and the output terminal 3 along the Y-axis direction and positioned between the amplifying element section 10 and the output terminal 3 . The composite circuit board 30 has a substrate 31 made of ceramic and a composite circuit 32 provided on the main surface of the substrate 31 . The planar shape of the substrate 31 is, for example, a rectangle. The back surface of the substrate 31 faces the bottom plate 4 e of the package 4 . One short side 31c of the substrate 31 is located near the side wall 4a of the package 4, and the other short side 31d of the substrate 31 is located near the side wall 4b of the package 4. As shown in FIG. That is, the substrate 31 extends from near one end of the package 4 to near the other end in the X-axis direction.

The synthesizing circuit 32 synthesizes the signals output from the plurality of drain pads 16 of the amplifying element section 10 into one output signal. The composite circuit 32 includes wiring patterns 33 provided on the main surface of the substrate 31 . The wiring pattern 33 has a line-symmetrical shape with respect to the center line of the substrate 31 along the Y-axis direction. The wiring pattern 33 includes four metal pads 33a. The four metal pads 33a are arranged side by side along the long side 31a. The metal pads 33a adjacent to each other are connected to each other via film resistors to form a Wilkinson coupler. As a result, while ensuring isolation between the plurality of drain pads 16 of the amplifying element section 10, matching of the output impedance of the amplifying element section 10 viewed from the output terminal 3 is achieved. In addition, only one film resistor 33b is shown in the drawing as a representative. Each metal pad 33a is electrically connected to two corresponding metal pads of the matching circuit 50 via bonding wires 9e. The wiring pattern 33 repeats coupling from the four metal pads 33a and finally reaches a connection point with the bonding wire 9f. The wiring pattern 33 is electrically connected to the output terminal 3 via the bonding wire 9f. The amplified high-frequency signal is output to the output terminal 3 from the central portion of the substrate 31 in the X-axis direction.

The output terminal 3 is a wiring pattern made of metal, and outputs the amplified high-frequency signal to the outside of the high-frequency amplifier 1 . The output terminal 3 is provided at the center of the end wall 4d in the X-axis direction and extends from the inside of the package 4 to the outside.

[Effect]
The effects of the amplifying element 11 described above will be described. First, a comparative example will be explained. FIG. 5 is a plan view showing an amplifying element 11X according to a comparative example. The amplifying element 11X is different from the amplifying element 11 in that the drain wiring 65X is provided instead of the drain wiring 65X. Also, the amplifying element 11X does not include the source air bridge 67 . The amplifying element 11X is configured similarly to the amplifying element 11 in other respects. Differences will be mainly described below.

The drain wiring 65X differs from the drain wiring 65 in that it has an intermediate bus line 65c instead of the intermediate bus line 65a, and is configured similarly to the drain wiring 65 in other respects. The intermediate bus line 65c is different from the intermediate bus line 65a in that it has a bus line portion 651c instead of the bus line portion 651a, and is configured similarly to the intermediate bus line 65a in other respects. The bus line portion 651c is different from the bus line portion 651a in that it has the same width D11 (here, the dimension in the Y-axis direction) as the width D2 of the bus line portion 651b in the drain bus line 65b. It is configured in the same manner as the portion 651a. Note that the length D13 (here, the dimension in the Y-axis direction) of the output combining circuit in the amplifying element 11X is the same as the length D3 of the output combining circuit in the amplifying element 11X.

In the amplifying element 11X as described above, the source potential may differ for each source finger 61 due to variations in source inductance among the plurality of source electrodes 61a. In such a case, the potential difference between the gate and the source may vary, the uniform operation of the transistor may be disturbed, and unnecessary waves may occur in the transistor 13, that is, a so-called oscillation phenomenon may occur. In order to avoid this oscillation phenomenon, it is conceivable to connect the plurality of source fingers 61 to maintain the plurality of source electrodes 61a at the same potential.

Also, FIG. 6 is a plan view showing an amplifying element 11Y according to another comparative example. 7 is a cross-sectional view taken along line VII-VII in FIG. 6. FIG. The amplifying element 11Y differs from the amplifying element 11X in that it includes a source air bridge 67Y, and is configured similarly to the amplifying element 11X in other respects.

Like the source air bridge 67, the source air bridge 67Y is a conductive wiring and electrically connects the plurality of source fingers 61 together. The source air bridge 67Y has a plurality of connection portions 67a and a plurality of relay portions 67b, like the air bridge wiring 671 in the source air bridge 67 (see FIG. 7). However, unlike the source air bridge 67, the source air bridge 67Y is wiring that is not included in the output combining circuit in the amplifying element 11Y.

The source air bridge 67Y is arranged on the active region R1 and connects central portions of the plurality of source fingers 61 in the Y-axis direction. Therefore, the source air bridge 67Y straddles both the gate finger 63 and the drain finger 62 . The width D14 of the source air bridge 67Y (here, the dimension in the Y-axis direction) is smaller than the width D11 of the bus line portion 651c of the intermediate bus line 65c. For example, the width D14 is 20 μm.

By connecting the plurality of source electrodes 61a (source fingers 61) to each other by the source air bridge 67Y (air bridge wiring) as in the amplification element 11Y described above, it is possible to maintain the plurality of source electrodes 61a at the same potential. In this case, there is an advantage in that an increase in capacitance between the source and the drain can be suppressed. On the other hand, since the central portion of each gate finger 63 is covered by the source air bridge 67Y, the visibility of each gate finger 63 is reduced. As a result, there is a risk of overlooking the discovery of defects in the manufacturing process. Also, for example, when the amplifying element 11Y is used in a product for an application requiring high reliability, visual inspection of a plurality of (for example, all) gate fingers 63 is required in the manufacturing process or the finished product. can be considered. However, in the amplifying element 11Y, when such visual inspection is required in the manufacturing process or the finished product, there arises a problem that it is difficult to visually inspect all the gate fingers 63. FIG.

On the other hand, in the amplifying element 11 according to this embodiment, the plurality of source fingers 61 are connected to each other by the air bridge wiring 671 of the source air bridge 67 . Therefore, the potential difference between the plurality of source fingers 61 can be reduced. One ends 61 b of the plurality of source fingers 61 are connected to each other by source wiring 64 , and the other ends 61 c of the plurality of source fingers 61 are connected to each other by air bridge wiring 671 . Therefore, in the central portion of the transistor 13 in the Y-axis direction, the gate finger 63 provided between the source finger 61 and the drain finger 62 is not covered with the air bridge wiring 671 . Therefore, the visibility of the gate finger 63 can be ensured.

Further, as in the present embodiment, the drain wiring 65 has a plurality of bus line portions 651a connecting two adjacent drain fingers 62 in the X-axis direction and a width D2 different from that of the bus line portions 651a. and a bus line portion 651b connecting the bus line portions 651a. In the configuration in which the other ends 61c of the plurality of source fingers 61 are connected by the air bridge wiring 671, the length D3 of the output combining circuit in the amplifying element 11 is compared with the length D13 of the output combining circuit in the amplifying elements 11X and 11Y. tends to grow. As the length D3 of the output combining circuit increases, the impedance in the output combining circuit also increases, so that the corresponding matching circuit (for example, the matching circuit 50 in FIG. 1) may also need to be significantly changed.

In contrast, in the above configuration, the length D3 of the output combining circuit is adjusted by making the width of one of the bus line portion 651a and the bus line portion 651b smaller than the width of the other. Therefore, according to the above configuration, it is possible to reduce the degree of impedance change in the output combining circuit. Also, in the above embodiment, the length D3 is the same as the length D13. Therefore, it is possible to replace the amplifying elements 11X and 11Y with the amplifying element 11 in a product (for example, a high-frequency amplifier) using the amplifying elements 11X and 11Y without changing other configurations.

As in this embodiment, the width D1 of the bus line portion 651a in the intermediate bus line 65a may be smaller than the width D2 of the bus line portion 651b in the drain bus line 65b. According to this configuration, it is possible to further reduce the degree of change in impedance compared to the case where the length D3 of the output combining circuit is adjusted by making the width D2 smaller than the width D1. As described above, during operation of the high-frequency amplifier 1, a current corresponding to two drain fingers (that is, four gate fingers) flows through each lead-out portion 653a of each intermediate bus line 65a, and each of the drain bus lines 65b flows. A current corresponding to all fingers (in this embodiment, corresponding to 4 drain fingers and 8 gate fingers) flows through the lead-out portion 652b. That is, a current corresponding to two gate fingers flows through each bus line portion 651a, and a current corresponding to four gate fingers flows through the bus line portion 651b. Therefore, since the width D2 of the bus line portion 651b through which a larger amount of current flows is larger than the width D1, the degree of change in the impedance in the output synthesis circuit is reduced as compared with the case where the width D2 is smaller than the width D1. obtain.

The width D1 of the bus line portion 651a may be equal to or greater than the width D4 of the air bridge wiring 671 as in the present embodiment. According to this configuration, the current density in the bus line portion 651a can be reduced compared to the case where the width D1 is smaller than the width D4. In addition, the width D4 can be made relatively small because the air bridge wiring 671 only regulates the potential while the bus line portion 651a causes the source current to flow. By making the width D4 equal to or smaller than the width D1, it is possible to reduce the extent to which the impedance in the output combining circuit changes.

As in this embodiment, the semiconductor substrate 12 may have an active region R1 and inactive regions R2 and R3 surrounding the active region R1. The air bridge wiring 671 may be arranged on the inactive region R3. As described above, since the active region R1 is a region operated as a transistor, the gate finger 63 in particular needs to be visually inspected in the active region R1. According to the above configuration, since the active region R1 is not covered with the air bridge wiring 671, the visibility of the gate finger 63 can be sufficiently ensured in the active region R1.

As in this embodiment, the gate wiring 66 may connect the ends 63b of the plurality of gate fingers 63 to each other. The other ends 61c of the plurality of source fingers 61 and the other ends 63c of the plurality of gate fingers 63 may be positioned on the inactive region R3. The other ends 61c of the plurality of source fingers 61 may be connected to the air bridge wiring 671 at positions farther from the active region R1 than the other ends 63c of the plurality of gate fingers 63 are. According to this configuration, the visibility of the gate finger 63 can be sufficiently ensured in the configuration in which the other end 63c of the gate finger 63 is located on the inactive region R3.

As in the present embodiment, the air bridge wiring 671 does not have to overlap the plurality of gate fingers 63 in plan view. According to this configuration, the visibility of the gate finger 63 can be sufficiently ensured.

[Modification]
The above embodiment describes one embodiment of the semiconductor device according to the present disclosure. The semiconductor device according to the present disclosure can be made by arbitrarily changing each of the above-described embodiments.

FIG. 8 is a plan view showing an amplifying element 11A according to a modification. The amplifying element 11A differs from the amplifying element 11 in that it has a drain wiring 65A instead of the drain wiring 65, and is configured similarly to the amplifying element 11 in other respects. The drain wiring 65A differs from the drain wiring 65 in that an intermediate bus line 65d is provided instead of the intermediate bus line 65a and a drain bus line 65e is provided instead of the drain bus line 65b. is configured similarly.

The intermediate bus line 65d is different from the intermediate bus line 65a in that it has a bus line portion 651d instead of the bus line portion 651a, and is configured similarly to the intermediate bus line 65a in other respects. The bus line portion 651d has a width D5 (here, dimension in the Y-axis direction) different from the width D1 of the bus line portion 651a. The drain bus line 65e is different from the drain bus line 65b in that it has a bus line portion 651e instead of the bus line portion 651b, and is configured similarly to the drain bus line 65b in other respects. The bus line portion 651e has a width D6 (here, the dimension in the Y-axis direction) different from the width D2 of the bus line portion 651b. The bus line portion 651d and the bus line portion 651e are configured similarly to the bus line portion 651a and the bus line portion 651b in other respects. Width D5 is greater than width D6, unlike width D6. As an example, the width D5 is 35 μm and the width D6 is 15 μm.

Also in this amplifying element 11A, as in the amplifying element 11, the other ends 61c of the plurality of source fingers 61 are connected to each other by an air bridge wiring 671. FIG. Therefore, the potential difference between the plurality of source fingers 61 can be reduced, and the visibility of the gate fingers 63 can be ensured. Thus, according to the amplifying element 11A, by providing the same configuration as the amplifying element 11, each effect described above can be obtained.

Further, according to the above configuration, the length D3 of the output combining circuit is adjusted by making the width D6 of the bus line portion 651e smaller than the width D5 of the bus line portion 651d. Therefore, according to the above configuration, similarly to the amplifying element 11, it is possible to reduce the extent to which the impedance in the output combining circuit changes. Also in the modified example, the output combining circuit in the amplifying element 11A has the same length D3 as the length D13. Therefore, in a product (for example, a high-frequency amplifier) using the amplifying elements 11X and 11Y, it becomes possible to replace the amplifying elements 11X and 11Y with the amplifying element 11A without changing other configurations.

FIG. 9 is a plan view showing an amplifying element 11B according to another modification. The amplifying element 11B differs from the amplifying element 11 in that it includes a drain wiring 65B instead of the drain wiring 65, and is configured similarly to the amplifying element 11 in other respects. The drain wiring 65B differs from the drain wiring 65 in that an intermediate bus line 65f is provided instead of the intermediate bus line 65a, and is configured similarly to the drain wiring 65 in other respects.

The intermediate bus line 65f is different from the intermediate bus line 65a in that it has a bus line portion 651f instead of the bus line portion 651a, and is configured similarly to the intermediate bus line 65a in other respects. The bus line portion 651f has a width D7 (here, the dimension in the Y-axis direction) different from the width D1 of the bus line portion 651a. The bus line portion 651f is configured similarly to the bus line portion 651a in other respects. Width D7 is the same as width D2. For example, the width D7 is 35 μm.

Also in this amplifying element 11B, as in the amplifying element 11, the other ends 61c of the plurality of source fingers 61 are connected to each other by an air bridge wiring 671. FIG. Therefore, the potential difference between the plurality of source fingers 61 can be reduced, and the visibility of the gate fingers 63 can be ensured. Thus, according to the amplifying element 11B, by providing the same configuration as the amplifying element 11, each effect described above can be obtained.

FIG. 10 is a plan view showing an enlarged part of an amplifying element 11C according to still another modification. The amplifying element 11C differs from the amplifying element 11 in that it has a plurality of gate fingers 63C instead of the plurality of gate fingers 63, and is configured similarly to the amplifying element 11 in other respects. The gate finger 63C differs from the gate finger 63 in that it has a length longer than the length of the gate finger 63 in the Y-axis direction. The other end 63c of each gate finger 63C protrudes in the Y-axis direction more than the other end 61c of the source finger 61 and the other end 62c of the drain finger 62. As shown in FIG. Above the inactive region R3, the other end 63c of each gate finger 63C extends to below the air bridge wiring 671 in the Y-axis direction. In other words, the air bridge wiring 671 overlaps at least part of the gate finger 63C in plan view.

Also in this amplifying element 11C, as in the amplifying element 11, the other ends 61c of the plurality of source fingers 61 are connected to each other by an air bridge wiring 671. FIG. Therefore, the potential difference between the plurality of source fingers 61 can be reduced, and the visibility of the gate finger 63C can be ensured. Thus, according to the amplifying element 11C, the plurality of gate fingers 63C extend to below the air bridge wiring 671 on the inactive region R3, and the air bridge wiring 671 overlaps the plurality of gate fingers 63C in plan view. Also in this case, the visibility of the gate finger can be ensured.

In addition, in the above embodiment and each modified example, the air bridge wiring 671 is arranged on the inactive region R3, but for example, at least part of the air bridge wiring 671 may be arranged on the active region R1. . On the inactive region R3, the other end 61c of each source finger 61 and the other end 63c of each gate finger 63 may extend to the same position in the Y-axis direction. In addition, in the above embodiment and each modified example, the air bridge wiring 671 straddles the plurality of lead portions 652a, but the air bridge wiring 671 may straddle at least part of each of the plurality of drain fingers 62. . The air bridge wiring 671 may straddle both the plurality of drain fingers 62 and the plurality of lead portions 652a. Further, in the above-described embodiment and each modified example, the air bridge wiring 671 has been exemplified as the bridge wiring, but the bridge wiring does not have to have an air bridge structure. For example, an insulator may be interposed between at least one of the plurality of drain fingers 62 and the plurality of lead portions 652a and the bridge wiring.

DESCRIPTION OF SYMBOLS 1... High frequency amplifier 2... Input terminal 3... Output terminal 4... Package 4a, 4b... Side wall 4c, 4d... End wall 4e... Bottom plate 9a, 9b, 9c, 9d, 9e, 9f... Bonding wire 10... Amplifier element part 11, 11A, 11B, 11C, 11X, 11Y... Amplification element (semiconductor device)
DESCRIPTION OF SYMBOLS 12... Semiconductor substrate 12a, 12b... Edge side 13... Transistor 14... Source pad 15... Via hole 16... Drain pad 20... Branch circuit board 21... Substrates 21a, 21b... Long side 21c, 21d... Short side 22... Branch circuit 23... Wiring pattern 23a Metal pad 23b Film resistor 30 Composite circuit board 31 Substrates 31a, 31b Long sides 31c, 31d Short side 32 Composite circuit 33 Wiring pattern 33a Metal pad 33b Film resistors 40, 50 Matching circuit 61 Source finger 61a Source electrode 61b One end 61c Other end 62 Drain finger 62a Drain electrode 62b One end 62c Other end 63, 63C Gate finger 63a Gate electrode 63b One end 63c Other end 64 Source wires 64a Source bus lines 64b Connection wires 65, 65A, 65B, 65X Drain wires 65a, 65c, 65d, 65f Intermediate bus lines 65b, 65e Drain bus lines 66 Gate wires 67, 67Y Source air Bridge 67a... Connection part 67b... Relay part 651a, 651c, 651d, 651f... Bus line part (first bus line)
651b, 651e... bus line section (second bus line)
652a... Drawer portion (drawer wiring)
652b, 653a... Drawer portion 671... Air bridge wiring (bridge wiring)
672... Connection wirings D1, D2, D4, D5, D6, D7, D11, D14... Widths D3, D13... Lengths R1... Active regions R2, R3... Inactive regions

Claims (8)

a semiconductor substrate;
a plurality of source fingers aligned in a first direction on the semiconductor substrate; a plurality of drain fingers alternately aligned in the first direction with the plurality of source fingers on the semiconductor substrate; a transistor having a plurality of gate fingers respectively provided between the source fingers and the drain fingers adjacent to each other in the first direction on a semiconductor substrate;
a gate wiring that connects the plurality of gate fingers;
a drain wire connecting the plurality of drain fingers;
a source wiring that connects one ends of the plurality of source fingers in a second direction that intersects with the first direction;
arranged across at least one of the plurality of drain fingers and a plurality of lead wires extending from each of the plurality of drain fingers in the second direction; Bridge wiring to connect,
comprising a
semiconductor equipment. The drain wiring has a plurality of first bus lines connecting two of the drain fingers adjacent to each other in the first direction, and has a width different from that of the first bus lines, and connects the plurality of first bus lines. a connecting second bus line;
A semiconductor device according to claim 1 . the width of the first bus line is smaller than the width of the second bus line;
3. The semiconductor device according to claim 2. The width of the first bus line is equal to or greater than the width of the bridge wiring.
4. The semiconductor device according to claim 2 or 3. the semiconductor substrate has an active region and an inactive region surrounding the active region;
The bridge wiring is arranged on an inactive region,
5. The semiconductor device according to claim 1. the semiconductor substrate has an active region and an inactive region surrounding the active region;
the gate wiring connects ends of the plurality of gate fingers in the second direction;
the other ends of the plurality of source fingers in the second direction and the other ends of the plurality of gate fingers in the second direction are located on the inactive region;
The other ends of the plurality of source fingers in the second direction are connected to the bridge wiring at positions farther from the active region than the other ends of the plurality of gate fingers in the second direction,
6. The semiconductor device according to claim 1. wherein the bridge wiring does not overlap the plurality of gate fingers in plan view;
7. The semiconductor device according to claim 1. the bridge wiring overlaps the plurality of gate fingers in plan view;
6. The semiconductor device according to claim 1.

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