JPH07335673A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce temperature rise due to internal heat generation and to improve the characteristics of a field effect semiconductor device by so disposing the gate electrodes of all unit semiconductor elements that the signal input directions of the electrodes are not aligned in the same direction in the device in which a plurality of the unit elements are arrayed in parallel. CONSTITUTION:A semiconductor device comprises a plurality of unit semiconductor elements 1 each having a gate electrode 3, a drain electrode 2 and a source electrode 4 and arrayed in parallel, wherein all the elements 1 are so disposed that the signal input directions of the electrodes 3 are not aligned in the same direction. For example, in a FET array having two unit FETs 1, the fine wirelike gate electrodes 3a, 3b of the unit FETs 1 are disposed in parallel. The one end of the one electrode 3a is connected to the other end of the other electrode 3b with a lead 10B wired so as to be round about the outer periphery of an electrode forming area so that the directions of signals to be input to the electrodes 3a, 3b are different at 180 degrees.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device. Specifically, the present invention relates to a field effect semiconductor device including a plurality of unit semiconductor elements.

[0002]

2. Description of the Related Art FIG. 1 shows a plurality of unit FETs (electric fields) formed on one substrate by using a gate finger electrode 52 having a comb structure, a drain finger electrode 57 having a comb structure, and a source finger electrode 55 having a comb structure. FIG. 11 is a plan view showing a conventional semiconductor device G having an effect transistor 59 formed therein. More specifically, first, the semiconductor substrate 5
One comb-shaped gate finger electrode 52 is formed on the semiconductor substrate 51, and a plurality of gate electrodes 53 formed in parallel with each other at the tip of the gate finger electrode 52 are provided on the semiconductor substrate 51.
Is located on the upper surface of the gate region. Then, as shown in FIG. 2, an insulating layer 54 is formed between the gate finger electrode 52 and the insulating layer 54.
By interposing, the source finger electrodes 55 having a comb shape are formed on the semiconductor substrate 51 from above the gate finger electrodes 52 while achieving insulation from the gate finger electrodes 52, and the source finger electrodes 55 are parallel to each other at the tips thereof. The formed source electrodes 56 are extended in the same direction between the gate electrodes 53 so as to be meshed with every other gate electrode 53, and each source electrode 56 is formed in the semiconductor substrate 5.
1 is provided on the upper surface of the source region. In addition, the semiconductor substrate 5
1 is provided with a comb-shaped drain finger electrode 57, and the drain electrodes 58 formed in parallel with each other at the tips of the drain finger electrodes 57 are interdigitated with the gate electrodes 53 so that the drain electrodes 58 are interposed between the gate electrodes 53. The drain electrodes 58 are extended from the opposite side and the drain electrodes 58 are formed on the semiconductor substrate 51.
Located on the drain region of. Therefore, in this semiconductor device G, the source electrodes 56 and 1
A unit FET 59 (a region of one unit FET 59 is surrounded by a broken line in FIG. 1) is formed in a region including one gate electrode 53 and one half drain electrode 58, and each unit FET 59 is the same. The semiconductor devices G are arranged with the unit FETs 59 arranged in an array as shown in FIG. 3 as a whole.

[0003]

In the field effect type semiconductor device G having such a structure, the RF signal is inputted from the gate electrode 53 and outputted to the drain electrode 58. The gate electrode 53 is thinner than the other drain electrode 58 and the source electrode 56 in order to shorten the gate length, and thus has a larger resistance and a larger amount of heat generation than the drain electrode 58 and the like. Moreover, even in the region along the gate electrode 53, the current flows out from the base end portion having a relatively small alongside resistance to the semiconductor substrate 51, so that the heat generation amount at the base end portion of the gate electrode 53 is large. In particular, when a large signal is input from the gate electrode 53 by a power FET or the like, the signal is concentrated at the base end portion of each gate electrode 53, that is, a portion near the feeding point, and the temperature rise of that portion increases.

However, in the conventional semiconductor device G as shown in FIG. 1, since the unit FETs 59 are oriented in the same direction, the region 60 where the temperature rise of each unit FET 59 is large.
(The area surrounded by the one-dot chain line in FIG. 1) will be concentrated in a line. In such a structure, the temperature rise of the adjacent unit FETs 59 has a synergistic effect and the semiconductor device G
However, there is a problem in that the maximum temperature rise of the semiconductor device G is increased and the mobility and noise figure (NF) characteristics of the semiconductor device G are deteriorated.

The present invention has been made in view of the above-mentioned drawbacks of the conventional example, and an object thereof is to reduce a temperature rise due to internal heat generation in a semiconductor device including a plurality of unit semiconductor elements. , To improve the characteristics of a field effect semiconductor device.

[0006]

The semiconductor device of the present invention comprises:
In a semiconductor device in which a plurality of unit semiconductor elements each having a gate electrode, a drain electrode and a source electrode are arranged in parallel, the signal input directions of the gate electrodes of all the unit semiconductor elements are arranged so as not to be aligned in the same direction. Is characterized by.

In particular, the semiconductor device of the present invention is a semiconductor device in which a plurality of unit semiconductor elements each having a gate electrode, a drain electrode, and a source electrode are arranged in parallel. It is characterized in that the input directions are opposite to each other.

[0008]

In the semiconductor device of the present invention, the unit electrodes of all the unit semiconductor elements arranged in parallel are arranged so that the signal input directions of the respective gate electrodes are not aligned in the same direction. Since the signal input directions of the respective gate electrodes are arranged to be opposite to each other, the base end portions of the gate electrodes are dispersed without being arranged in a line, and a region with a large temperature rise is not concentrated in a line. The temperature rise due to the synergistic effect between the adjacent unit semiconductor elements can be reduced. Therefore, the temperature rise of the semiconductor device can be reduced and its characteristics can be improved.

[0009]

1 is a plan view showing a basic embodiment of a field effect type semiconductor device (FET array) A according to an embodiment of the present invention. This is FE consisting of two unit FET1
In the T-array, the thin-line gate electrodes 3a and 3b of each unit FET 1 are arranged in parallel on the semiconductor substrate 5, the drain electrode 2 is arranged in parallel between both gate electrodes 3a and 3b, and the gate electrodes 3a and 3b. Source electrodes 4 and 4 are provided outside 3b.
Are arranged in parallel. Therefore, the drain electrode 2 is commonly used and one unit F is formed in a region including the gate electrode 3a and the source electrode 4 and the drain electrode 2 on both sides thereof.
ET1 is formed, and the other unit FE is formed in a region including the gate electrode 3b and the source electrode 4 and the drain electrode 2 on both sides thereof.
T1 is configured. The drain electrode 2 is connected to the drain pad 6A by a lead portion 6B extending in a direction orthogonal to the arrangement direction of these electrodes. Further, the source electrodes 4 and 4 at both ends are electrically connected to each other by a bridge structure constituted by the conductive post 7 and the bridge electrode 8, and one source electrode 4 is provided with a source pad 9. Further, one end of the gate electrode 3a (left end in the drawing) and the other end of the other gate electrode 3b (right end in the drawing) are wired so as to bypass the outer periphery of the electrode formation region. Are connected to each other by a lead 10B, and the lead 10B is provided with a gate pad 10A. Therefore, the gate electrodes 3a and 3b, the lead 10B, and the gate pad 10A form a comb-shaped gate finger electrode 11, and the directions of signals input to the two gate electrodes 3a and 3b are different by 180 degrees. ing.

The gate electrode 3 of such a semiconductor device A
In a and 3b, the signal is input from the base end side toward the tip side, but the gate electrodes 3a and 3b
Are opposite to each other and the signal input directions are different by 180 degrees. Even with such a structure, the temperature rise at the base end portions of the gate electrodes 3a and 3b near the feeding point (gate pad 10A) is the same as in the conventional example, but the base end portions of the gate electrodes 3a and 3b near the feeding point are the same. Are dispersed without being arranged adjacent to each other, the region 12 having a large temperature increase surrounded by the one-dot chain line in FIG. It is possible to suppress the maximum temperature rise due to, and to reduce the decrease in mobility and the deterioration of noise figure characteristics.

It is easy to construct a semiconductor device composed of a large number of unit FETs 1 based on the above-mentioned basic embodiment. For example, what is shown in FIG. 5 is the semiconductor device A shown in FIG.
On the basis of the above, a semiconductor device B composed of six unit FETs 1 is constructed by alternately inverting the directions of the gate electrodes 3a and 3b. Thus, many units F
When ET1s are arranged in parallel, for example, the gate finger electrode 11 and the lead 6B of the drain electrode 2 intersect, but in this embodiment, the lead 6B of the drain electrode 2 is formed.
The insulating layer 13 is sandwiched between the gate electrode 3a and the lead 10B of the gate electrode 3a and 3b to electrically insulate the gate electrode 3a and 3b from the drain electrode 2.

In the semiconductor device C shown in FIG. 6, two adjacent gate electrodes 3a and 3b are aligned in the same direction. In this case, the area 12 with large heat generation is 2
It can be said that the embodiment of FIG. 4 is more preferable from the viewpoint of preventing the temperature rise due to heat generation, since the parts come close to each other side by side.
Compared with (FIG. 1), it is effective in sufficiently dissipating heat and preventing the temperature rise of the semiconductor device C. Therefore, considering the allowable upper limit temperature of the semiconductor device C, several adjacent gate electrodes 3a and 3b may be aligned in the same direction. In addition, there may be a portion where the direction of the gate electrode is aligned only in a part of the semiconductor device.

FIG. 7 is a plan view showing a state in which a semiconductor device D according to still another embodiment of the present invention is mounted on a mounting surface 14 such as a package or a mounting substrate. In this semiconductor device D, separate gate pads 10A are provided at the ends of the respective gate electrodes 3a and 3b on the opposite sides without arranging the leads 10B of the gate electrodes 3a and 3b. As a result,
Lead 10B of gate electrodes 3a and 3b and drain electrode 2
No longer intersects with the lead 6B. Then, the drain pad 6A is connected to the drain electrode 15 on the mounting surface 14 by the bonding wire 16, and one of the gate pads 10A is separated by the bonding wire 17a so that the electrode forming region is straddled by the one bonding wire 17a. , 17b are connected to the gate electrode 18 on the mounting surface 14. In addition, each source electrode 4, 4
Are also provided with source pads 9 and 9, respectively.
It is connected to the source electrode (earth line) 20 on the mounting surface 14 by 19. Since the source electrodes 4 and 4 are electrically connected by the bridge structure including the conductive posts 7 and the bridge electrodes 8, one source electrode 4 is provided.
It is also possible to provide the source pad 9 only at this point and connect it to the source electrode 20 by the bonding wire 19, which makes it possible to reduce the mounting area of the semiconductor device D.

Also in this semiconductor device D, since the signal input directions of the gate electrodes 3a and 3b are different by 180 degrees, the positions of the regions 12 where the temperature rise is large are dispersed, and the maximum temperature rise of the semiconductor device D can be suppressed. it can. In addition,
It is also easy to extend the semiconductor device D having the two unit FETs 1 to a semiconductor device having three or more unit FETs 1 as a basis. That is, although not shown, even if the number of unit FETs 1 increases, the respective gate electrodes 3a, 3b
The gate pad 10A may be individually provided in the above, and each gate pad 10A may be connected to the gate electrode 18 on the mounting surface 14 by a bonding wire.

8 and 9 are a plan view showing a semiconductor device E according to still another embodiment of the present invention and a cross-sectional view showing a part of it in an enlarged manner. In the semiconductor device E, the narrow gate electrodes 3a and 3b are arranged at a constant pitch, and the source electrodes 4 are formed between the gate electrodes 3a and 3b and at every other end. Same gate electrode 3
every other drain electrode 2 between a and 3b and at the other end
Are formed. The source electrodes 4 are electrically connected to each other by a bridge structure including a conductive post 7 and a bridge electrode 8 as in the above embodiment, and a source pad 9 is provided at an end of the bridge electrode 8. Further, a via hole 21 penetrating from the upper surface to the lower surface of the semiconductor substrate 5 is provided at a position facing each drain electrode 2 of the semiconductor substrate 5, and wiring is provided inside the via hole 21 and on the lower surface of the semiconductor substrate 5. Each drain electrode 2 is electrically connected by the connecting electrode portion 22. Further, the drain pad 6 is formed on the drain electrode 2 at the end on the upper surface of the semiconductor substrate 5.
Is provided. Each of the gate electrodes 3a and 3b has a lead 10 in which every other gate electrode 3a or 3b is wired left and right.
A gate pad 10A is provided on each lead 10B and is connected to B, and a comb-shaped gate finger electrode 11a having a gate electrode 3a and a comb-shaped gate finger electrode 11b having a gate electrode 3b are provided. ing.

By doing so, the intersection of the electrodes can be eliminated except for the bridge structure of the source electrode 4, the reliability of the semiconductor device E can be improved, and noise and signal leakage can be reduced. Therefore, the characteristics of the semiconductor device E can be improved. Further, the regions 12 where the temperature rises at the base end portions of the gate electrodes 3a and 3b are also alternately distributed to the left and right, so that the heat dissipation is improved and the maximum rise temperature can be suppressed low.

[0017]

According to the present invention, in a semiconductor device in which unit semiconductor elements are arranged in parallel, it is possible to mitigate the concentration of a large heat generation region of each gate electrode and reduce the temperature rise of the semiconductor device. The maximum temperature rise of the semiconductor device can be reduced. Therefore, deterioration of the mobility and noise figure (NF) characteristics of the semiconductor device can be prevented.

Further, the high frequency characteristics are improved as compared with the conventional semiconductor device such as FET, and the matching circuit can be easily constructed. Further, since the maximum temperature rise is small, the input power can be increased as compared with the conventional semiconductor device, and the reliability of the semiconductor device is improved.

[Brief description of drawings]

FIG. 1 is a plan view showing a conventional field effect semiconductor device.

FIG. 2 is a cross-sectional view showing an insulating structure between a gate finger electrode and a source finger electrode in the above semiconductor device.

FIG. 3 is an equivalent circuit diagram of the above semiconductor device.

FIG. 4 is a plan view showing the structure of a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a plan view showing a structure of a semiconductor device according to another embodiment of the present invention.

FIG. 6 is a plan view showing the structure of a semiconductor device according to still another embodiment of the present invention.

FIG. 7 is a plan view showing the structure of a semiconductor device according to still another embodiment of the present invention.

FIG. 8 is a plan view showing the structure of a semiconductor device according to still another embodiment of the present invention.

FIG. 9 is an enlarged sectional view showing a part of the above-mentioned embodiment.

[Explanation of symbols]

 1 unit FET 2 drain electrodes 3a, 3b gate electrode 4 source electrode 5 semiconductor substrate 11 gate finger electrode 12 large temperature rise region

Claims (2)

[Claims] 1. In a semiconductor device in which a plurality of unit semiconductor elements each having a gate electrode, a drain electrode and a source electrode are arranged in parallel, the signal input directions of the respective gate electrodes of all the unit semiconductor elements are not aligned in the same direction. A semiconductor device characterized in that the semiconductor devices are arranged as described above. 2. In a semiconductor device in which a plurality of unit semiconductor elements each having a gate electrode, a drain electrode and a source electrode are arranged in parallel, the signal input directions of the respective gate electrodes are opposite to each other between adjacent unit semiconductor elements. A semiconductor device characterized in that