JP2023003495A - multilayer printed wiring board - Google Patents

Abstract

To realize suppression of ion migration and high-density arrangement of a plurality of wirings.SOLUTION: A wiring pattern 19A provided on the surface 8a of a substrate 8 includes wirings 9B and 9C adjacent to each other. A multilayer printed wiring board 100 is configured such that a voltage can be applied between the wirings 9B and 9C. An insulator 3zb exists between the wiring 9B and the wiring 9C. A water-impermeable barrier layer 7A covers the insulator 3zb between the wirings 9B and 9C of the wiring pattern 19A.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a multi-layer printed wiring board that includes multiple traces that are adjacent to each other.

Multilayer printed wiring boards used in power electronics equipment generally have a configuration for suppressing the occurrence of ion migration. The configuration is, for example, a configuration in which the electric field intensity between the plurality of wirings is reduced by extending the distance between the plurality of mutually adjacent wirings provided in the inner layer of the multilayer printed wiring board.

Hereinafter, multilayer printed wiring boards used in power electronics equipment are also referred to as "power multilayer boards". Also, hereinafter, the distance between a plurality of mutually adjacent wirings provided in the inner layer of the power multilayer substrate is also referred to as "interwiring distance" or "insulation distance".

For the power multilayer board, miniaturization of the power multilayer board, cost reduction of the power multilayer board, and the like are required. In order to reduce the size of a power multi-layer board, for example, it is required to shorten the distance between wirings and arrange the wirings at a high density. Further, in order to reduce the cost of the power multilayer board, for example, it is required to reduce the weight of the power multilayer board.

Substances that ionize metals are hereinafter also referred to as “ionic substances”. Ionic substances are, for example, halogens.

Ion migration is a phenomenon that tends to occur in the presence of three elements: an electric field, ionic substances, and moisture. Ion migration is a phenomenon in which the following events occur.

For example, when a liquid such as an electrolytic solution exists between a plurality of wirings having different potentials, metals forming the wirings with a high ionization tendency are eluted as metal ions. The metal ions are deposited by moving within the insulator existing between the plurality of wirings due to the Coulomb force of the electric field. Thereby, a conductive path is formed between the plurality of wirings.

Patent Literature 1 discloses a configuration for suppressing the occurrence of ion migration (hereinafter also referred to as “related configuration A”). In related configuration A, a film as a migration suppression layer is formed directly on each of a plurality of wirings formed on a substrate.

In the following, the area between two adjacent wirings is also referred to as "inter-wiring area". Moreover, below, the wiring which faces the area|region between wirings is also called "facing wiring." Each of two adjacent wirings is a facing wiring. In the following description, the area of the facing wiring that faces the inter-wiring area is also referred to as the "facing area". The facing area of the facing wiring is, for example, the side surface of the facing wiring. Each of two adjacent wirings has a facing region as a side surface.

In related configuration A, each of a plurality of mutually adjacent wirings formed on a substrate has a facing region as a side surface.

Japanese Patent No. 5667927

In the related configuration A that suppresses the occurrence of ion migration, a film as a migration suppressing layer is also formed on facing regions as side surfaces of each of a plurality of interconnects that are adjacent to each other. Therefore, in related configuration A, it is difficult to shorten the distance between the plurality of wirings. In other words, the related configuration A has a problem that it is impossible to realize a high-density arrangement of the plurality of wirings.

The present disclosure has been made to solve such problems, and provides a multilayer printed wiring board capable of suppressing the occurrence of ion migration and realizing high-density arrangement of a plurality of wirings. The purpose is to

To achieve the above object, a multilayer printed wiring board according to one aspect of the present disclosure includes a substrate having a main surface, a wiring pattern provided on the main surface of the substrate, and a barrier layer impermeable to water. , the wiring pattern includes a plurality of wirings adjacent to each other, the multilayer printed wiring board is configured so that a voltage can be applied between the plurality of wirings, and an insulator exists between the plurality of wirings. and the barrier layer covers the insulator between the wires of the wiring pattern.

According to the present disclosure, the wiring pattern provided on the main surface of the substrate includes multiple wirings adjacent to each other. A multilayer printed wiring board is configured so that a voltage can be applied between a plurality of wirings. An insulator exists between the plurality of wires. A water impermeable barrier layer covers the insulation between the wires of the wiring pattern.

Accordingly, it is possible to suppress water from entering the insulator between the wirings adjacent to each other. Therefore, it is possible to suppress the occurrence of ion migration in a situation where a voltage is applied between the plurality of wirings.

Also, an insulator exists between a plurality of wirings adjacent to each other. Therefore, by using an insulator having a small size, it is possible to shorten the distance between the plurality of wirings.

As described above, suppression of ion migration and high-density arrangement of a plurality of wirings can be realized.

1 is a cross-sectional view of a multilayer printed wiring board according to Embodiment 1; FIG. It is a figure for demonstrating the manufacturing method of a multilayer printed wiring board. It is a figure which mainly shows the structure of the barrier layer shown by FIG. FIG. 4 is a diagram mainly showing the structure of a barrier layer in Modified Structure A of Embodiment 1; FIG. 4 is a diagram mainly showing the structure of a barrier layer in modified structure B of Embodiment 1; 1 is a cross-sectional view of a multilayer printed wiring board having a barrier layer configuration; FIG. 1 is a cross-sectional view of a multilayer printed wiring board without a barrier layer configuration; FIG.

Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, the same components are given the same reference numerals. Components with the same reference numerals have the same names and functions. Therefore, detailed descriptions of some of the components denoted by the same reference numerals may be omitted.

Note that the dimensions, materials, shapes, and relative arrangement of the components illustrated in the embodiments may be appropriately changed depending on the configuration of the substrate, various conditions, and the like. Also, the dimensions of components in the drawings may differ from the actual dimensions.

<Embodiment 1>
FIG. 1 is a cross-sectional view of a multilayer printed wiring board 100 according to Embodiment 1. FIG. In FIG. 1, the X, Y and Z directions are orthogonal to each other. The X, Y and Z directions shown in the following figures are also orthogonal to each other. Hereinafter, the direction including the X direction and the direction opposite to the X direction (−X direction) is also referred to as the “X-axis direction”. Also, hereinafter, the direction including the Y direction and the direction opposite to the Y direction (−Y direction) is also referred to as the “Y-axis direction”. Also, hereinafter, the direction including the Z direction and the direction opposite to the Z direction (−Z direction) is also referred to as the “Z-axis direction”.

Also, hereinafter, a plane including the X-axis direction and the Y-axis direction is also referred to as an "XY plane". Also, hereinafter, a plane including the X-axis direction and the Z-axis direction is also referred to as an "XZ plane". Also, hereinafter, a plane including the Y-axis direction and the Z-axis direction is also referred to as a "YZ plane".

As shown in FIG. 1, the multilayer printed wiring board 100 includes a substrate 8, insulating layers 3A and 3B, wiring pattern layers E10A and E10B which are conductor layers, and resist layers 5A and 5B.

The substrate 8 is, for example, a laminated plate. The substrate 8 is made of resin material A containing halogen. The resin material A is a material obtained by impregnating a glass cloth with an epoxy resin containing halogen. The halogen is, for example, bromine.

The substrate 8 has a front surface 8a as a principal surface and a back surface 8b as a principal surface. The back surface 8b is the surface of the substrate 8 opposite to the front surface 8a. Each of the front surface 8a and the rear surface 8b is flat.

On the surface 8a of the substrate 8, the insulating layer 3A, the wiring pattern layer E10A and the resist layer 5A are laminated in the order of the insulating layer 3A, the wiring pattern layer E10A and the resist layer 5A. The insulating layer 3B, the wiring pattern layer E10B and the resist layer 5B are laminated on the rear surface 8b of the substrate 8 in the order of the insulating layer 3B, the wiring pattern layer E10B and the resist layer 5B.

A wiring pattern 19 is provided on each of the front surface 8a and the back surface 8b of the substrate 8. As shown in FIG. The wiring pattern 19 is an inner layer wiring pattern provided in the inner layer of the multilayer printed wiring board 100 . The wiring pattern 19 is made of a conductive metal. A conductive metal is, for example, copper. The wiring pattern 19 includes a plurality of wirings 9 adjacent to each other.

The shape of the cross section of each wiring 9 along the vertical direction is rectangular. Therefore, the wiring 9 has a top surface, side surfaces and a bottom surface. Note that the cross-sectional shape of each wiring 9 along the vertical direction is not limited to a rectangle. The cross-sectional shape of each wiring 9 may be, for example, an ellipse. In a situation where the shape of the cross section of each wiring 9 is an ellipse, the side surface of the wiring 9 is a curved surface.

Each of the wirings 9 of the wiring pattern 19 is made of copper as a metal. Each of the plurality of wirings 9 is an electrode. The plurality of wirings 9 of the wiring pattern 19 are arranged so that the plurality of wirings 9 do not contact each other. The plurality of wirings 9 of the wiring pattern 19 includes two adjacent wirings 9 . Two adjacent wirings 9 included in the wiring pattern 19 are hereinafter also referred to as "adjacent wirings". The wiring pattern 19 includes adjacent wirings.

In the following, the distance from one wiring 9 of two wirings 9 that are adjacent wirings to the other wiring 9 of two wirings 9 that are adjacent wirings is referred to as "distance between wirings" or "insulation distance." ” is also called. Also, hereinafter, the region between two wirings 9 that are adjacent wirings is also referred to as an “interwiring region” or an “insulating region”.

An insulator exists in an insulating region, which is an inter-wiring region between two wirings 9 that are adjacent wirings. In the following, the wiring 9 facing the inter-wiring area is also referred to as "facing wiring". Each of the two wirings 9, which are adjacent wirings, are facing wirings. In the following, the area facing the inter-wiring area, which the facing wiring has, is also referred to as the "facing area". The facing area of the facing wiring is, for example, the side surface of the facing wiring. Each of the two wirings 9 that are adjacent wirings has a facing region as a side surface.

Hereinafter, the wiring pattern 19 provided on the surface 8a of the substrate 8 is also referred to as "wiring pattern 19A". In the following, the wiring pattern 19 provided on the back surface 8b of the substrate 8 is also referred to as "wiring pattern 19B". That is, the wiring pattern 19A and the wiring pattern 19B are provided on the front surface 8a and the rear surface 8b of the substrate 8, respectively.

The wiring pattern 19A includes four wirings 9 as an example. The four wirings 9 included in the wiring pattern 19A are hereinafter also referred to as wirings 9A, 9B, 9C, and 9D. For example, the wirings 9A and 9B are adjacent wirings. Also, for example, the wirings 9B and 9C are adjacent wirings.

A region between the wirings 9A and 9B, which are adjacent wirings, is an inter-wiring region as an insulating region. A region between the wirings 9B and 9C, which are adjacent wirings, is an inter-wiring region as an insulating region.

The number of wirings 9 included in the wiring pattern 19A is not limited to 4, and may be 2, 3, or 5 or more. Further, the arrangement form of the plurality of wirings 9 included in the wiring pattern 19A is not limited to the arrangement form of the plurality of wirings 9 included in the wiring pattern 19A in FIG.

The wiring pattern 19B includes two wirings 9 as an example. The two wirings 9 included in the wiring pattern 19B are hereinafter also referred to as wirings 9E and 9F. The wirings 9E and 9F are adjacent wirings. The number of wirings 9 included in the wiring pattern 19B is not limited to two, and may be three or more. Further, the arrangement form of the plurality of wirings 9 included in the wiring pattern 19B is not limited to the arrangement form of the plurality of wirings 9 included in the wiring pattern 19B in FIG. For example, the wiring 9F may be arranged at a square position represented by a dotted line.

Each of the insulating layers 3A and 3B is a sheet-like insulating material. The sheet-shaped insulating material is resin material A containing halogen. The resin material A is a material obtained by impregnating a glass cloth with an epoxy resin containing halogen and drying the glass cloth. The halogen is, for example, bromine. Each of insulating layers 3A and 3B contains halogen.

A core substrate 20 is composed of the substrate 8, the wiring pattern 19A and the wiring pattern 19B. The core base material 20 is configured such that a wiring pattern 19A is provided on the front surface 8a of the substrate 8 and a wiring pattern 19B is provided on the back surface 8b of the substrate 8. As shown in FIG.

An insulating layer 3A is provided on the core base material 20 . Specifically, the insulating layer 3A is provided so as to cover the wiring pattern 19A on the surface 8a of the substrate 8. As shown in FIG. Further, the insulating layer 3A is provided so that the insulating material, which is the insulating layer 3A, exists in an inter-wiring region between two wirings 9 that are adjacent wirings included in the wiring pattern 19A.

In the following description, the insulating material present in the inter-wiring region between two adjacent wirings 9 is also referred to as "insulator 3z". The insulator 3z is, for example, part of the insulating layer 3A containing halogen. Therefore, the insulator 3z contains halogen.

An insulator 3z exists between two wirings 9 that are adjacent wirings. Specifically, the insulator 3z exists between the two wirings 9 so that the insulator 3z is in contact with the two wirings 9 that are adjacent wirings. The insulator 3z is sandwiched between two wirings 9 that are adjacent wirings.

Here, it is assumed that adjacent wirings are wirings 9B and 9C. In this case, the insulator 3z exists in the interwiring region between the wiring 9B and the wiring 9C. That is, the insulator 3z exists between the wiring 9B and the wiring 9C so that the insulator 3z is in contact with the wiring 9B and the wiring 9C.

An insulating layer 3B is provided under the core base material 20 . Specifically, the insulating layer 3B is provided so as to cover the wiring pattern 19B on the back surface 8b of the substrate 8. As shown in FIG. Further, the insulating layer 3B is provided so that the insulating material, which is the insulating layer 3B, exists in the inter-wiring region between two wirings 9 that are adjacent wirings included in the wiring pattern 19B.

Here, it is assumed that adjacent wirings are wirings 9E and 9F. In this case, the insulator 3z exists in the interwiring region between the wiring 9E and the wiring 9F. That is, the insulator 3z exists between the wiring 9E and the wiring 9F so that the insulator 3z is in contact with the wiring 9E and the wiring 9F.

In the following, the insulator 3z present between the wiring 9A and the wiring 9B is also referred to as "insulator 3za". In the following description, the insulator 3z present between the wiring 9B and the wiring 9C is also referred to as "insulator 3zb". In the following description, the insulator 3z present between the wiring 9C and the wiring 9D is also referred to as "insulator 3zc". In the following description, the insulator 3z present between the wiring 9E and the wiring 9F is also referred to as "insulator 3ze".

Further, hereinafter, a member through which water cannot pass is also referred to as a "water impermeable member". Water cannot pass through the water impermeable member. That is, the water impermeable member is a member impermeable to water. The water impermeable member is, for example, metal such as copper. Hereinafter, a member through which water can pass is also referred to as a "water passing member". Water can pass through the water passage member.

Each of the wiring pattern layers E10A and E10B is a surface layer of the multilayer printed wiring board 100. FIG. Each of the wiring pattern layers E10A and E10B has a horizontal connection structure for electrically connecting a plurality of conductive members in the horizontal direction.

Each of the wiring pattern layers E10A and E10B is made of a water impermeable member. Each of the wiring pattern layers E10A and E10B is made of a conductive metal foil. The metal foil is, for example, copper foil. The wiring pattern layer E10A is provided on the surface 8a side of the substrate 8 . Further, the wiring pattern layer E10B is provided on the back surface 8b side of the substrate 8. As shown in FIG.

The insulating layer 3A has a surface 3a. A wiring pattern layer E10A covering the wiring pattern 19A is provided on the surface 3a of the insulating layer 3A. That is, the multilayer printed wiring board 100 has the wiring pattern layer E10A. The wiring pattern layer E10A is composed of a plurality of wiring patterns E1 and a barrier layer 7A. That is, the barrier layer 7A is part of the wiring pattern layer E10A.

The barrier layer 7A is provided on the surface 8a side of the substrate 8. As shown in FIG. A barrier layer 7A is provided above the substrate 8 . Also, the barrier layer 7A is provided on the surface 3a of the insulating layer 3A. Each wiring pattern E1 is made of copper foil.

Insulating layer 3B also has back surface 3b. A wiring pattern layer E10B that covers the wiring pattern 19B provided on the back surface 8b of the substrate 8 is provided on the back surface 3b of the insulating layer 3B. That is, the multilayer printed wiring board 100 has the wiring pattern layer E10B. The wiring pattern layer E10B is composed of a plurality of wiring patterns E1 and a barrier layer 7B. That is, the barrier layer 7B is part of the wiring pattern layer E10B.

The barrier layer 7B is provided on the back surface 8b side of the substrate 8 . A barrier layer 7B is provided below the substrate 8 . Also, the barrier layer 7B is provided on the rear surface 3b of the insulating layer 3B. Each of the wiring pattern layers E10A and E10B is hereinafter also referred to as "wiring pattern layer E10".

Each of the barrier layers 7A, 7B is composed of a water impermeable member. That is, the barrier layer 7A is a layer impermeable to water. The expression "water-impermeable layer" includes the meaning of "a layer impermeable to water at all" and the meaning of "a layer permeable to a small amount of water". The barrier layer 7B is also a water impermeable layer.

Each of the barrier layers 7A, 7B is made of copper foil. Each of the barrier layers 7A and 7B has a sheet shape. As described above, the barrier layer 7A is provided on the surface 8a side of the substrate 8. As shown in FIG. Also, the barrier layer 7B is provided on the back surface 8b side of the substrate 8 .

Each of the barrier layers 7A and 7B is hereinafter also referred to as "barrier layer 7". In other words, the barrier layer 7 is provided on each of the front surface 8a side and the rear surface 8b side of the substrate 8 . Also, the barrier layer 7 is provided above the substrate 8 and below the substrate 8 . Barrier layer 7 A extends along surface 3 a of substrate 8 . The barrier layer 7B extends along the back surface 3b of the substrate 8. As shown in FIG.

Hereinafter, the configuration of the barrier layer 7 is also referred to as "barrier layer configuration". The barrier layer configuration is also a configuration using the barrier layer 7 . Multilayer printed wiring board 100 has a barrier layer configuration.

Each of resist layers 5A and 5B is a surface layer of multilayer printed wiring board 100 . The resist layer 5A is provided on the surface 3a of the insulating layer 3A. The resist layer 5B is provided on the rear surface 3b of the insulating layer 3B. Each of the resist layers 5A and 5B is composed of a water passage member through which water can pass.

In the present embodiment, multilayer printed wiring board 100 is configured such that a voltage can be applied between multiple wires 9 of wiring pattern 19 . In the following description, the configuration capable of applying voltage between the wirings 9 of the wiring pattern 19 is also referred to as "voltage application configuration". A voltage application configuration is a configuration for applying a voltage between a plurality of wirings 9 . The multilayer printed wiring board 100 has a voltage application configuration. The voltage application configuration is a configuration using through holes H1a and H1b as via holes.

The multilayer printed wiring board 100 is provided with through holes H1a and H1b. Each of through holes H1a and H1b extends along the thickness direction of multilayer printed wiring board 100 . Each of through holes H1a and H1b is provided over insulating layer 3A, substrate 8 and insulating layer 3B. Each of through holes H1a and H1b is a component for interlayer connection.

In the voltage application configuration, the through holes H1a and H1b are configured such that a voltage can be applied between the through holes H1a and H1b. Further, in the voltage application configuration, the through holes H1a, H1b, And, the plurality of wirings 9 are configured.

A plurality of wiring patterns E1 provided on surface 3a of insulating layer 3A includes wiring patterns E1 electrically connected to through holes H1a. The wiring pattern E1 electrically connected to the through hole H1a is hereinafter also referred to as "wiring pattern E1a".

A plurality of wiring patterns E1 provided on back surface 3b of insulating layer 3B include wiring patterns E1 electrically connected to through holes H1b. Hereinafter, the wiring pattern E1 electrically connected to the through hole H1b is also referred to as "wiring pattern E1b".

In the voltage application configuration, the wiring pattern E1a and the wiring pattern E1b are configured so that a voltage can be applied between the wiring pattern E1a and the wiring pattern E1b. By applying a voltage between the wiring pattern E1a and the wiring pattern E1b, a voltage is applied between the through holes H1a and H1b, and a voltage is applied between the wirings 9 of the wiring pattern 19. be done.

Hereinafter, the state in which voltage is applied to multilayer printed wiring board 100 is also referred to as "voltage application state." Further, hereinafter, the state in which no voltage is applied to the multilayer printed wiring board 100 is also referred to as "no voltage applied state". The status of the multilayer printed wiring board 100 includes a voltage application status and a voltage non-application status.

A voltage application state is a state in which a voltage is applied between the through hole H1a and the through hole H1b. Also, the voltage application state is a state in which a voltage is applied between the wirings 9 of the wiring pattern 19 . The voltage application state is generated by applying a voltage between the wiring patterns E1a and E1b by an external power supply (not shown) having a configuration for applying a voltage between the wiring patterns E1a and E1b, for example. The external power supply is not included in multilayer printed wiring board 100 .

Hereinafter, a portion of the multilayer printed wiring board 100 where ion migration may occur under voltage application conditions is also referred to as a “probable portion”. In this embodiment, the insulator 3zb is assumed to be the possible portion. As described above, the multiple wirings 9 are made of copper. Therefore, the ion migration that can occur in the insulator 3z, which is the portion that can occur, adjacent to the wiring 9 is copper ion migration.

In the voltage application state, for example, a voltage is applied between the wirings 9A and 9B, between the wirings 9B and 9C, and between the wirings 9C and 9D in the wiring pattern 19A. That is, in a voltage application state, a voltage is applied between the wiring 9B and the wiring 9C of the wiring pattern 19A. In the voltage application state, for example, voltage is applied between the wiring 9E and the wiring 9F of the wiring pattern 19B.

The barrier layer 7A is constructed such that the potential of the barrier layer 7A is not fixed at a specific potential. For example, the barrier layer 7A is separated from the wiring pattern 19A. Specifically, the barrier layer 7A is not electrically connected to the wirings 9A, 9B, 9C, 9D of the wiring pattern 19A. The wirings 9A, 9B, 9C, and 9D are wirings to which voltage can be applied. Also, the barrier layer 7A is not electrically connected to, for example, the wiring pattern E1 present on the surface 3a.

Also, the barrier layer 7B is configured so that the potential of the barrier layer 7B is not fixed at a specific potential. For example, the barrier layer 7B is separated from the wiring pattern 19B. Specifically, the barrier layer 7B is not electrically connected to the wirings 9E and 9F of the wiring pattern 19B. The wirings 9E and 9F are wirings to which a voltage can be applied. Also, the barrier layer 7B is not electrically connected to, for example, the wiring pattern E1 present on the back surface 3b.

In the present embodiment, each of the barrier layers 7A and 7B is designed to prevent moisture from penetrating from the resist layers 5A and 5B, which are water passage members, into the insulator 3zb, which is the portion where water can be generated. It covers the insulator 3zb which is the part. The barrier layer 7A locally covers the wiring pattern 19A.

Specifically, the barrier layer 7A covers the insulator 3zb between the wiring 9B and the wiring 9C of the wiring pattern 19A. The barrier layer 7A is separated from the insulator 3zb and does not contact the insulator 3zb. The barrier layer 7A covers the top of the insulator 3zb and the top surfaces of the wirings 9B and 9C.

Also, the barrier layer 7A does not exist in the region between the wiring 9B and the wiring 9C. Therefore, the barrier layer 7A is not formed in the facing regions as side surfaces of the wirings 9B and 9C. That is, the barrier layer 7A does not come into contact with the facing regions as side surfaces of the wirings 9B and 9C.

The barrier layer 7A covers the insulator 3zb from above. Moreover, the barrier layer 7A covers the insulator 3zb and the wirings 9B and 9C, which are adjacent wirings, from above the insulator 3zb.

Hereinafter, of the main surface of the substrate 8, the region in which the generatable portion and the two wirings 9 sandwiching the generatable portion are provided is also referred to as "region A". The main surface of the substrate 8 is the front surface 8a or the back surface 8b. Also, hereinafter, a region different from the region A on the main surface of the substrate 8 is also referred to as a “region B”. A main surface of the substrate 8 has a region A and a region B. FIG.

In addition, hereinafter, of the wiring pattern 19 in which a possible part exists, a region in which the possible part and the two wirings 9 sandwiching the possible part do not exist is also referred to as "area B".

A barrier layer 7B covers the insulator 3zb from below. The barrier layer 7B is separated from the insulator 3zb and does not contact the insulator 3zb.

Moreover, the barrier layer 7B covers the insulator 3zb and the wirings 9B and 9C from below the insulator 3zb. Specifically, the barrier layer 7B covers the lower part of the insulator 3zb and the lower surfaces of the wirings 9B and 9C from below the insulator 3zb.

Barrier layer 7B does not exist in the region between wiring 9B and wiring 9C. Therefore, the barrier layer 7B is not formed in the facing regions as side surfaces of the wirings 9B and 9C. That is, the barrier layer 7B does not come into contact with the facing regions as side surfaces of the wirings 9B and 9C.

The barrier layer structure in FIG. 1 corresponds to the following situation St. Situation St is a situation in which the possible part exists on the surface 8a as the main surface. Situation St is a situation in which the possible part is the insulator 3zb. Situation St is a situation in which two wirings 9 sandwiching the possible occurrence part are wirings 9B and 9C.

In the barrier layer configuration of FIG. 1 corresponding to the situation St, the barrier layer 7A locally covers the wiring pattern 19A in which the insulator 3zb exists from above the insulator 3zb. Specifically, the barrier layer 7A covers the insulator 3zb and the wirings 9B and 9C from above the insulator 3zb. That is, the barrier layer 7A covers at least the insulator 3zb from above. Barrier layer 7A does not cover area B from above insulator 3zb.

The region B in the situation St is a region different from the region A on the surface 8a of the substrate 8. FIG. The region A in the situation St is a region of the surface 8a of the substrate 8 where the insulator 3zb and the wirings 9B and 9C are provided. Further, the area B in the situation St is also an area in the wiring pattern 19A in which the insulator 3zb and the wirings 9B and 9C do not exist.

Further, in the barrier layer configuration corresponding to the situation St, the barrier layer 7B locally covers the wiring pattern 19A in which the insulator 3zb exists from below the insulator 3zb. Specifically, the barrier layer 7B covers the insulator 3zb and the wirings 9B and 9C from below the insulator 3zb. That is, the barrier layer 7B covers at least the insulator 3zb from below the insulator 3zb. The barrier layer 7B does not cover the area B from below the insulator 3zb.

The wiring pattern layer E10A exists above the wiring pattern 19A in which the insulator 3zb, which is a possible part, exists. As described above, the barrier layer 7A is part of the wiring pattern layer E10A. The wiring pattern layer E10B exists below the wiring pattern 19A in which the insulator 3zb, which is a possible part, exists. As mentioned above, the barrier layer 7B is part of the wiring pattern layer E10B.

In the following description, the direction in which the voltage is applied is also referred to as "direction D". Direction D is, for example, the direction from through hole H1a to through hole H1b. For example, direction D in FIG. 1 is along the X-axis.

The width of the barrier layer 7A is longer than the distance between the wirings 9B and 9C. Specifically, the length of the barrier layer 7A in the direction D is longer than the distance between the wires 9B and 9C. In addition, in the direction D, the barrier layer 7A covers the entire insulator 3zb, which can be generated, and the entire wiring 9B and wiring 9C.

Also, the width of the barrier layer 7B is longer than the distance between the wires 9B and 9C. Specifically, the length of the barrier layer 7B in the direction D is longer than the distance between the wires 9B and 9C. In addition, in the direction D, the barrier layer 7B covers the entire insulator 3zb that can be generated, the entire wiring 9B, and the entire wiring 9C.

In the following description, an adjacent wiring having a potential difference in a voltage application state is also referred to as a "voltage application adjacent wiring". The voltage application adjacent wirings are, for example, the wirings 9B and 9C in the voltage application state. Also, hereinafter, the electric field strength between two wirings 9 that are adjacent wirings for voltage application is also referred to as "electric field strength E".

Here, the voltage applied between two wirings 9, which are adjacent wirings for voltage application, is expressed as "voltage V". Also, the insulation distance, which is the distance between two wirings 9 that are adjacent wirings for voltage application, is expressed as "insulation distance d".

In this case, the "electric field intensity E" is obtained by the formula A expressed as "voltage V/insulation distance d". According to the formula A, ion migration is more likely to occur as the electric field intensity E of the voltage-applied adjacent wiring is stronger. Further, according to the formula A, the shorter the insulation distance d between adjacent wirings to which a voltage is applied, the more easily ion migration occurs.

The insulation distance d of the wirings 9B and 9C, which are adjacent voltage application wirings, is shorter than the insulation distance d of the wirings 9A, 9B which are adjacent voltage application wirings. Therefore, the electric field intensity E of the wirings 9B and 9C under the voltage application condition is stronger than the electric field intensity E of the wirings 9A and 9B under the voltage application condition. That is, in the voltage application state, the electric field strength E applied to the insulator 3zb between the wirings 9B and 9C is stronger than the electric field strength E applied to the insulator 3za between the wirings 9A and 9B.

Ion migration can occur when moisture and ionic substances are present in inter-wiring regions between multiple wirings where potential differences exist. That is, ion migration may occur when moisture and ionic substances are present in the insulator 3z provided in the inter-wiring region of the voltage application adjacent wiring.

Further, ion migration is more likely to occur as the electric field intensity E of the voltage-applied adjacent wiring is stronger. As described above, in the voltage application state, the electric field strength E applied to the insulator 3zb present between the wirings 9B and 9C is equal to the electric field strength E applied to the insulator 3za present between the wirings 9A and 9B. stronger. Therefore, the insulator 3zb is a portion where ion migration is more likely to occur than the insulator 3za.

Therefore, in the present embodiment, the water impermeable barrier layer 7A covers the insulator 3zb, which is the portion that can be generated, between the wiring 9B and the wiring 9C, which are adjacent voltage application wirings. Therefore, the presence of the barrier layer 7A can prevent moisture from entering the insulator 3zb, which can occur. For example, it is possible to prevent moisture from entering the insulator 3zb, which is a possible part, from above the resist layer 5A, which is a water passage member.

Also, the water-impermeable barrier layer 7B covers the insulator 3zb from below. Therefore, due to the presence of the barrier layer 7B, penetration of moisture into the insulator 3zb, which can occur, can be suppressed. For example, it is possible to prevent moisture from penetrating from below the resist layer 5B, which is a water passage member, into the insulator 3zb, which is a possible portion.

The multilayer printed wiring board 100 having the above structure can suppress the occurrence of ion migration under voltage application conditions.

(Production method)
Next, a method for manufacturing the multilayer printed wiring board 100 will be described with reference to FIGS. 1 and 2. FIG. FIG. 2 is a diagram for explaining a method of manufacturing the multilayer printed wiring board 100. FIG. Hereinafter, the method for manufacturing the multilayer printed wiring board 100 is also referred to as “manufacturing method Pr”.

In the manufacturing method Pr, first, a wiring pattern forming step is performed on the substrate 8 . In the wiring pattern forming step, an inner conductor layer is formed on the surface 8 a of the substrate 8 . Next, by etching the inner conductor layer, a wiring pattern 19A including wirings 9A, 9B, 9C, and 9D shown in FIG. 2 is formed.

An inner conductor layer is formed on the back surface 8 b of the substrate 8 . Next, the wiring pattern 19B including the wirings 9E and 9F is formed by etching the inner conductor layer. Thereby, the core substrate 20 composed of the substrate 8, the wiring pattern 19A and the wiring pattern 19B is formed.

Next, a lamination process is performed. In the laminating step, in summary, the insulating layer 3A and the conductor layer 4A are laminated on the surface 8a of the substrate 8 in the core base material 20 in the order of the insulating layer 3A and the conductor layer 4A. Moreover, the insulating layer 3B and the conductor layer 4B are laminated in the order of the insulating layer 3B and the conductor layer 4B on the rear surface 8b of the substrate 8 in the core base material 20 .

Specifically, in the laminating step, the insulating layer 3A, which is a sheet-like insulating material, is adhered to the surface 8a of the substrate 8 so as to cover the wiring pattern 19A on the surface 8a. Further, the insulating layer 3B, which is a sheet-shaped insulating material, is adhered to the back surface 8b of the substrate 8 so as to cover the wiring pattern 19B on the back surface 8b.

Next, metal foil is laminated on each of the front surface 3a of the insulating layer 3A and the rear surface 3b of the insulating layer 3B. The metal foil is, for example, copper foil. Then, the metal foil on the front surface 3a and the metal foil on the back surface 3b are each subjected to heating and pressure molding. Thereby, conductor layers 4A and 4B are formed.

Next, a wiring pattern layer forming step is performed. In the wiring pattern layer forming step, the conductor layer 4A is etched to form a wiring pattern layer E10A composed of a plurality of wiring patterns E1 and a barrier layer 7A shown in FIG. That is, the barrier layer 7A and the plurality of wiring patterns E1 are formed at the same time.

Also, the conductor layer 4B is etched to form a wiring pattern layer E10B composed of a plurality of wiring patterns E1 and a barrier layer 7B. That is, the barrier layer 7B and the plurality of wiring patterns E1 are formed at the same time.

Next, a through-hole forming step is performed. In the through hole forming step, a boring step and a plating step are performed to form through holes H1a and H1b shown in FIG. In the plating step, for example, plating is performed so that the wiring pattern E1a existing on the front surface 3a of the insulating layer 3A and the wiring pattern E1a existing on the back surface 3b of the insulating layer 3B shown in FIG. 1 are electrically connected. is formed. A plurality of layers in multilayer printed wiring board 100 are connected between layers by through holes H1a and H1b.

Next, a resist formation process is performed. In the resist forming step, the resist layer 5A is laminated on the surface 3a of the insulating layer 3A so that the resist layer 5A covers the plurality of wiring patterns E1 and the barrier layer 7A in FIG. be done. Moreover, the resist layer 5B is laminated on the back surface 3b of the insulating layer 3B so that the resist layer 5B covers the plurality of wiring patterns E1 and the barrier layer 7B in FIG. 1 existing on the back surface 3b of the insulating layer 3B. Thus, the manufacturing of the multilayer printed wiring board 100 is completed.

(Barrier layer configuration)
Various configurations such as those shown in FIGS. 3, 4 and 5 are conceivable for the barrier layer configuration in this embodiment. FIG. 3 is a diagram mainly showing the barrier layer configuration in FIG. FIG. 3 does not show the wiring pattern E1, through holes H1a, H1b, etc. in the multilayer printed wiring board 100 of FIG.

Hereinafter, the barrier layer configuration in FIG. 1 or FIG. 3 is also referred to as "barrier layer configuration N". The multilayer printed wiring board 100 of FIG. 1 has a barrier layer configuration N. As shown in FIG. In summary, the barrier layer configuration N is a configuration in which the barrier layer 7 covers the insulator 3z, which is the portion that can be generated, and the two wirings 9 that sandwich the portion that can be generated. The detailed configuration of the barrier layer configuration N is the configuration described above with reference to FIG.

Further, hereinafter, the configuration obtained by modifying the barrier layer configuration N of FIG. 3 will also be referred to as "modified configuration A" or "modified configuration B". Each of variant A and variant B is a configuration in which the size of barrier layer 7 of FIG. 3 is increased.

FIG. 4 is a diagram mainly showing the configuration of the barrier layer 7 in the modified configuration A of the first embodiment. The configuration of FIG. 4 is a configuration in which the modified configuration A is applied to the barrier layer configuration N of FIG. FIG. 5 is a diagram mainly showing the structure of the barrier layer 7 in the modified structure B of the first embodiment. The configuration of FIG. 5 is a configuration in which a modified configuration B is applied to the barrier layer configuration N of FIG. The size of the barrier layer 7 in variant A of FIG. 4 is larger than the size of the barrier layer 7 in variant B of FIG.

The barrier layer configuration N of FIG. 3, the modified configuration A of FIG. 4, and the modified configuration B of FIG. 5 are configurations corresponding to the aforementioned situation St. Situation St is a situation in which the possible part exists on the surface 8a as the main surface. Situation St is a situation in which the possible part is the insulator 3zb. Situation St is a situation in which two wirings 9 sandwiching the possible occurrence part are wirings 9B and 9C.

Instead of barrier layer configuration N, multilayer printed wiring board 100 may have variant configuration A of FIG. 4 or variant configuration B of FIG.

As described above, of the main surface of the substrate 8, the region where the generatable portion and the two wirings 9 sandwiching the generatable portion are provided is also referred to as "region A". The main surface of the substrate 8 is the front surface 8a or the back surface 8b. Moreover, as described above, a region different from the region A on the main surface of the substrate 8 is also called a “region B”. Further, as described above, of the wiring pattern 19 having a possible occurrence portion, a region where the occurrence possible portion and the two wirings 9 sandwiching the occurrence possible portion do not exist is also referred to as “region B”.

First, the modified configuration A of FIG. 4 corresponding to the aforementioned situation St will be described. In variant A, the barrier layer 7 covers the entire area of the main surface of the substrate 8 where the wiring pattern 19 is provided. The main surface is the front surface 8a or the back surface 8b. The expression "the barrier layer 7 covers the entire area of the major surface of the substrate 8" also includes the meaning that "the barrier layer 7 covers substantially the entire area of the major surface of the substrate 8".

Specifically, in the modified configuration A corresponding to situation St, the barrier layer 7A covers the entire area of the surface 8a of the substrate 8 from above. The barrier layer 7B covers the entire area of the back surface 8b of the substrate 8 from below.

Further, in the modified configuration A, the barrier layer 7A covers the entire region of the wiring pattern 19A where the insulator 3zb exists from above the insulator 3zb, which is the portion that can be generated. Specifically, the barrier layer 7A covers the insulators 3za, 3zb, 3zc, the wirings 9A, 9B, 9C, 9D, and the region B from above the insulator 3zb. That is, the barrier layer 7A covers the insulator 3zb, the wirings 9B and 9C, and the region B from above the insulator 3zb. That is, the barrier layer 7A covers at least the insulator 3zb and the region B from above the insulator 3zb.

The region B in the situation St is a region different from the region A on the surface 8a of the substrate 8. FIG. The region A in the situation St is a region of the surface 8a of the substrate 8 where the insulator 3zb and the wirings 9B and 9C are provided. Further, the area B in the situation St is also an area in the wiring pattern 19A in which the insulator 3zb and the wirings 9B and 9C do not exist.

Moreover, the barrier layer 7B covers the entire region of the wiring pattern 19A where the insulator 3zb exists from below the insulator 3zb. Specifically, the barrier layer 7B covers the insulators 3za, 3zb, 3zc, the wirings 9A, 9B, 9C, 9D, and the region B from below the insulator 3zb. That is, the barrier layer 7B covers the insulator 3zb, the wirings 9B and 9C, and the region B from below the insulator 3zb. That is, the barrier layer 7B covers at least the insulator 3zb and the region B from below the insulator 3zb.

Next, a modified configuration B of FIG. 5 corresponding to the situation St will be described. Variant B differs from variant A in FIG. 4 in the size of the barrier layers 7A, 7B. Other configurations of the modified configuration B are the same as those of the modified configuration A, so detailed description thereof will not be repeated.

The size of barrier layer 7A of variant configuration B is smaller than the size of barrier layer 7A of variant configuration A of FIG. The size of the barrier layer 7B of the modified configuration B is smaller than the size of the barrier layer 7B of the modified configuration A. The barrier layer 7A of FIG. 5 is a layer obtained by etching the conductor layer 4A of FIG. The barrier layer 7B in FIG. 5 is a layer obtained by etching the conductor layer 4B in FIG.

In the modified configuration B corresponding to the situation St, the barrier layer 7 covers the entire area of the wiring pattern 19 where the insulator 3zb, which is the possible part, is present.

Specifically, the barrier layer 7A covers the entire region of the wiring pattern 19A where the insulator 3zb exists from above the insulator 3zb, which is the portion that can be generated. Also, the barrier layer 7A is locally provided on the surface 3a of the insulating layer 3A so that the barrier layer 7A covers the insulator 3zb from above. The barrier layer 7A covers the insulators 3za, 3zb, 3zc, the wirings 9A, 9B, 9C, 9D, and the region B from above the insulator 3zb. That is, the barrier layer 7A covers the insulator 3zb, the wirings 9B and 9C, and the region B from above the insulator 3zb. That is, the barrier layer 7A covers at least the insulator 3zb and the region B from above the insulator 3zb.

Moreover, the barrier layer 7B covers the entire region of the wiring pattern 19A where the insulator 3zb exists from below the insulator 3zb. Moreover, the barrier layer 7B is locally provided on the rear surface 3b of the insulating layer 3B so that the barrier layer 7B covers the insulator 3zb from below. The barrier layer 7B covers the insulators 3za, 3zb, 3zc, the wirings 9A, 9B, 9C, 9D, and the region B from below the insulator 3zb. That is, the barrier layer 7B covers the insulator 3zb, the wirings 9B and 9C, and the region B from below the insulator 3zb. That is, the barrier layer 7B covers at least the insulator 3zb and the region B from below the insulator 3zb.

Also in the barrier layer structure N of FIG. 3, the barrier layer 7A is locally provided on the surface 3a of the insulating layer 3A so that the barrier layer 7A covers the insulator 3zb from above. . Moreover, the barrier layer 7B is locally provided on the rear surface 3b of the insulating layer 3B so that the barrier layer 7B covers the insulator 3zb from below. In the following, each of the barrier layer configuration N and the modified configuration B is also referred to as a "local arrangement configuration".

As described above, in any of the barrier layer configuration N, the modified configuration A, and the modified configuration B, which are localized arrangements, moisture from the resist layers 5A and 5B, which are water passage members, can be generated at the portions where water can be generated. Intrusion into a certain insulator 3zb can be suppressed.

(experiment)
The inventors of the present disclosure conducted an experiment (hereinafter also referred to as "experiment J1") for confirming the effectiveness of the barrier layer configuration using the barrier layer 7. FIG. Experiment J1 is a comparative experiment for confirming that the barrier layer structure suppresses the occurrence of ion migration. In experiment J1 as a comparative experiment, multilayer printed wiring board 100A and multilayer printed wiring board 100N were used.

The multilayer printed wiring board 100N is a board without a barrier layer structure. FIG. 7 is a cross-sectional view of a multilayer printed wiring board 100N without a barrier layer configuration. The multilayer printed wiring board 100N of FIG. 7 is mainly different from the multilayer printed wiring board 100 of FIG. The difference is that the wiring pattern E1 is not provided.

Other configurations of the multilayer printed wiring board 100N are the same as those of the multilayer printed wiring board 100 of FIG. The configuration of the components included in multilayer printed wiring board 100N is the same as the configuration of the components included in multilayer printed wiring board 100 . For example, the material forming the insulating layer 3A included in the multilayer printed wiring board 100N is the same as the material forming the insulating layer 3A included in the multilayer printed wiring board 100. FIG.

The wiring pattern 19A of the multilayer printed wiring board 100N is a comb-shaped electrode. The wiring pattern 19A, which is a comb-shaped electrode, has a comb-like shape in plan view. A wiring pattern 19A, which is a comb-shaped electrode, includes six wirings 9 having the same width. The six wirings 9 are arranged at intervals. Therefore, the six wirings 9 have five inter-wiring regions.

The five insulation distances corresponding to the five inter-wiring regions are the same. Five insulators 3z are present in each of the five inter-wiring regions. That is, there are five insulators 3z in the wiring pattern 19A, which is a comb-shaped electrode. The size of each of the five insulators 3z is the same as the size of insulator 3zb in FIG. That is, each of the five insulators 3z is a generatable portion.

The multilayer printed wiring board 100A is a board having a barrier layer structure. FIG. 6 is a cross-sectional view of a multilayer printed wiring board 100A having a barrier layer configuration. The multilayer printed wiring board 100A differs from the multilayer printed wiring board 100N in FIG. 7 in that it further includes barrier layers 7A and 7B. Other configurations of the multilayer printed wiring board 100A are the same as those of the multilayer printed wiring board 100N.

The configuration and position of the barrier layers 7A and 7B in the multilayer printed wiring board 100A are similar to the configuration and position of the barrier layers 7A and 7B in the multilayer printed wiring board 100 of FIG. 1, for example. For example, barrier layer 7A is provided on surface 3a of insulating layer 3A. Also, the barrier layer 7B is provided on the back surface 3b of the insulating layer 3B.

The barrier layer 7A covers the five insulators 3z of the wiring pattern 19A, which is the comb-shaped electrode, from above the five insulators 3z. Moreover, the barrier layer 7B covers the five insulators 3z of the wiring pattern 19A from below the five insulators 3z.

6 and 7, the plurality of wirings 9 of the wiring pattern 19 may be provided on the rear surface 8b of the substrate 8 instead of the front surface 8a of the substrate 8. FIG. For example, the six wirings 9 in FIG. 6 may be arranged at six square positions represented by dotted lines.

In Experiment J1, a DC voltage is applied to the target substrate. The target substrate is the multilayer printed wiring board 100N or the multilayer printed wiring board 100A. Hereinafter, the DC voltage applied to the target substrate is also referred to as "applied DC voltage".

Specifically, in Experiment J1, a DC voltage was applied from an external power supply to five inter-wiring regions of the wiring pattern 19A, which are comb-shaped electrodes, using through holes H1a and H1b and wiring patterns E1a and E1b. be. That is, a DC voltage is applied to the five insulators 3z present in the wiring pattern 19A, which are comb-shaped electrodes. Hereinafter, the resistance value of each insulator 3z present in the wiring pattern 19A, which is the comb-shaped electrode, included in the target substrate is also referred to as "insulation resistance value".

In Experiment J1, the inventors conducted an ion migration accelerated test according to the following conditions Jk. The ion migration promotion test is a test for promoting the occurrence of ion migration. The accelerated ion migration test is a high temperature and high humidity bias test. The high-temperature and high-humidity bias test is a test in which a DC voltage is applied to a target substrate under high-temperature and high-humidity conditions. Hereinafter, the ion migration acceleration test is also referred to as "test Ts".

The test Ts was performed with the target substrate housed in a box-shaped test chamber. The target substrate is the multilayer printed wiring board 100N or the multilayer printed wiring board 100A.

Under condition Jk, the temperature of the test chamber is 85 [°C]. Moreover, under condition Jk, the relative humidity in the test chamber is 85[%]. Hereinafter, the time during which the test Ts is continuously performed is also referred to as "test time". Also, under condition Jk, the test time is 1000 hours. Also, under condition Jk, the applied DC voltage is 1000 [V].

In experiment J1, changes in insulation resistance values were recorded as the test Ts continued. Hereinafter, the insulation resistance value before the test Ts is performed is also referred to as "initial resistance value". Also, hereinafter, the period during which the test Ts is performed is also referred to as the "test period." Further, hereinafter, traces indicating a situation in which a short circuit has occurred in the inter-wiring region of the wiring pattern 19A due to the occurrence of ion migration are also referred to as "short circuit traces".

Determination of the occurrence of ion migration was performed as follows. When the insulation resistance value decreased to 10 ⁶ [Ω] or less during the test implementation period and did not return to the initial resistance value after the test Ts was completed, it was determined that ion migration occurred. In addition, even if the insulation resistance value is greater than 10 ⁶ [Ω] during the test implementation period, if the insulation resistance value does not return to the initial resistance value after the test Ts is completed and short-circuit marks can be confirmed, ion migration occurs. It was determined that

In Experiment J1, when the inventors performed the test Ts on the multilayer printed wiring board 100N, the insulation resistance value decreased several hundred hours after the start of the test Ts. Further, short-circuit traces were confirmed in the multilayer printed wiring board 100N after the test Ts was completed.

On the other hand, when the inventors performed the test Ts on the multilayer printed wiring board 100A, no decrease in the insulation resistance value was confirmed even after 1000 hours.

From the above results, the inventors found that the barrier layers 7A and 7B inhibited the entry of water from the resist layers 5A and 5B, which are water-permeable members, into the insulator 3z, which is a portion where water can be generated. confirmed. That is, the inventors confirmed the effectiveness of the barrier layer configuration in the multilayer printed wiring board 100A.

(summary)
As described above, according to the present embodiment, the wiring pattern 19A provided on the surface 8a of the substrate 8 includes the wirings 9B and 9C adjacent to each other. The multilayer printed wiring board 100 is configured so that a voltage can be applied between the wirings 9B and 9C. An insulator 3zb exists between the wiring 9B and the wiring 9C. A water-impermeable barrier layer 7A covers the insulator 3zb between the wires 9B and 9C of the wiring pattern 19A.

This can prevent water from entering the insulator between the wirings. Therefore, it is possible to suppress the occurrence of ion migration in a situation where a voltage is applied between a plurality of wirings.

Also, an insulator exists between the plurality of wirings. Therefore, by using an insulator having a small width, it is possible to shorten the distance between a plurality of wirings.

As described above, suppression of ion migration and high-density arrangement of a plurality of wirings can be achieved.

In addition, as described above, ion migration is a phenomenon that tends to occur in situations where there are three elements: an electric field, an ionic substance, and moisture. An ionic substance is a substance that ionizes metals. Ionic substances are, for example, halogens. Ion migration is a phenomenon in which the following events occur.

When an electrolytic solution is generated by moisture and an ionic substance between a plurality of wirings to which a DC voltage is applied, metals constituting the wirings are eluted as metal ions due to an electrochemical reaction. The metal ions are deposited by moving within the insulator existing between the wirings due to the Coulomb force of the electric field. Thereby, conductive paths are formed between the plurality of wirings.

Hereinafter, the multilayer printed wiring board 100 of FIG. 1 from which the barrier layers 7A and 7B have been removed is also referred to as a "multilayer printed wiring board N1". The multilayer printed wiring board N1 is not shown. Further, hereinafter, the portion of the multilayer printed wiring board N1 where ion migration may occur is also referred to as a "probable portion". The multilayer printed wiring board N1 includes an insulator 3z that is a possible part.

Here, it is assumed that ion migration occurs in the wiring pattern 19 of the multilayer printed wiring board N1. In this case, deposition of metal ions is repeated in the insulator 3z, which is a possible part, and exists between the plurality of wirings 9 having different potentials, and there is a possibility that a short circuit will occur.

Therefore, in order to suppress the occurrence of ion migration, it is necessary to reduce the amount of any one of the electric field, the ionic substance, and the moisture in the insulator 3z where ion migration can occur. Hereinafter, the configuration in which the inter-wiring distance, which is the insulation distance between two adjacent wirings 9, is extended will also be referred to as an "extended configuration". The elongated configuration is used, for example, to weaken the electric field strength in the inter-wiring region under voltage application conditions.

In order to achieve miniaturization of multilayer printed wiring boards, it is necessary to suppress the occurrence of ion migration without using an elongated configuration. In this case, it is necessary to prevent ionic substances, water, and the like from entering the insulator 3z existing between the plurality of wirings 9 .

Substrate 8 and insulating layers 3A and 3B are in contact with wiring pattern 19 . As described above, each of substrate 8 and insulating layers 3A and 3B is made of resin material A containing halogen.

Therefore, in the present embodiment, each of the barrier layers 7A and 7B is arranged so as to prevent the moisture from the resist layers 5A and 5B, which are water passage members, from entering the insulator 3zb, which is a portion where water can be generated. be done. As a result, it is possible to suppress the intrusion of moisture into the insulator 3zb, which can occur. Therefore, it is possible to suppress the occurrence of ion migration under voltage application conditions. Therefore, sufficient insulation reliability can be ensured in the multilayer printed wiring board 100 .

Moreover, in the present embodiment, the length of the barrier layers 7A and 7B in the direction D is longer than the distance between the wirings 9B and 9C. Therefore, even if the barrier layers 7A and 7B are misaligned in the step of forming the barrier layers 7A and 7B in the manufacturing method Pr, the intrusion of moisture into the insulator 3zb, which can occur, is suppressed. can do.

In addition, in the modified configuration A of FIG. 4 or the modified configuration B of FIG. 5 in the present embodiment, the barrier layer 7A is formed from above the insulator 3zb, which is the portion that can be generated, from the wiring in which the insulator 3zb exists. It covers the entire area of pattern 19A. The barrier layer 7B covers the entire region of the wiring pattern 19A where the insulator 3zb exists from below the insulator 3zb.

Therefore, in Modified Configuration A or Modified Configuration B, it is possible to sufficiently prevent water from the resist layers 5A and 5B, which are water passage members, from entering the insulator 3zb, which is a possible generation portion. In modified configuration A or modified configuration B, it is possible to sufficiently suppress the occurrence of ion migration under voltage application conditions.

In addition, in the barrier layer configuration N or the modified configuration B, which is the local arrangement configuration, in the present embodiment, the barrier layer 7A covers the insulator 3zb, which is the portion that can be generated, from above the insulator 3zb. The barrier layer 7A is locally provided on the surface 3a of the insulating layer 3A. The barrier layer 7B is locally provided on the rear surface 3b of the insulating layer 3B so that the barrier layer 7B covers the insulator 3zb from below.

Therefore, even in the barrier layer configuration N or the modified configuration B, which are local arrangement configurations, it is possible to suppress moisture from the resist layers 5A and 5B, which are water passage members, from entering the insulator 3zb, which is a possible generation portion. can. Therefore, it is possible to suppress the occurrence of ion migration under voltage application conditions.

Further, in the present embodiment, the barrier layer 7 and the plurality of wiring patterns E1 are simultaneously formed in the wiring pattern layer forming step of the manufacturing method Pr. Accordingly, it is not necessary to add a separate step for forming the barrier layer 7 in the manufacturing method Pr. Therefore, for example, the number of layers forming the multilayer printed wiring board 100 in FIG. 1 is the same as the number of layers forming the multilayer printed wiring board 100N having no barrier layer structure in FIG. Also, for example, the number of steps required for manufacturing the multilayer printed wiring board 100 in FIG. 1 is the same as the number of steps required for manufacturing the multilayer printed wiring board 100N.

Therefore, it is possible to provide a multilayer printed wiring board that suppresses the occurrence of ion migration without increasing the number of layers constituting the multilayer printed wiring board and the number of processes required for manufacturing the multilayer printed wiring board. can. Therefore, it is possible to prevent the tact time for manufacturing the multilayer printed wiring board from becoming long, and to realize the cost reduction of the multilayer printed wiring board.

Moreover, in the present embodiment, the barrier layer 7A is part of the wiring pattern layer E10A. The wiring pattern layer E10A is composed of the wiring pattern E1 and the barrier layer 7A. Each of the wiring pattern E1 and the barrier layer 7A is made of copper foil. That is, the material forming the wiring pattern E1 is the same material as the material forming the barrier layer 7A. Therefore, it is not necessary to separately prepare a material for forming the barrier layer. Therefore, it is possible to prevent the takt time for manufacturing the multilayer printed wiring board from becoming longer, and to reduce the cost of the multilayer printed wiring board. Moreover, in the multilayer printed wiring board 100, sufficient ion migration resistance performance for suppressing the occurrence of ion migration can be ensured. That is, sufficient insulation reliability can be ensured in the multilayer printed wiring board 100 .

Moreover, in the present embodiment, the barrier layer 7A covering the insulator 3zb, which is the portion that can be generated, is locally provided on the surface 3a of the insulating layer 3A. As a result, various forms of wiring patterns E1 can be formed in the wiring pattern layer E10A including the barrier layer 7A. Moreover, in the wiring pattern layer forming step in the manufacturing method Pr of the multilayer printed wiring board 100, the barrier layer 7A and the wiring pattern E1 can be formed at the same time.

As described above, in the present embodiment, it is possible to suppress the occurrence of ion migration in a voltage application state without using the extended configuration. Therefore, it is possible to shorten the inter-wiring distance between the two wirings 9 sandwiching the insulator 3z, which is the part that can occur. Therefore, miniaturization of the multilayer printed wiring board 100 can be realized. Moreover, high-density mounting of electronic components on the multilayer printed wiring board 100 can be achieved.

By the way, in the aforementioned power multi-layer substrate, a momentary short circuit occurs when insulation between a plurality of wirings having different electric potentials cannot be maintained due to precipitation of metal ions accompanying ion migration. A high voltage is applied to the power multilayer substrate. Therefore, even in a situation where a short circuit occurs momentarily, there is a high possibility that problems associated with the short circuit will occur. The problem is, for example, carbonization of the insulator due to heat generated by the short circuit. Therefore, in the conventional power multilayer board, there is a problem that it is difficult to reduce the size of the power multilayer board by significantly shortening the distance between wirings.

Further, in related configuration A, a film as a migration suppressing layer is formed directly on each of the plurality of wirings formed on the substrate. Therefore, in related configuration A, in manufacturing a printed wiring board that is a multilayer printed wiring board, in addition to the step of forming the plurality of wirings, a step of forming a migration suppression layer is further added. In addition, a separate material is required for forming the migration suppression layer.

As described above, in related configuration A, there is a problem that the tact time for manufacturing the multilayer printed wiring board increases, and the manufacturing cost of the multilayer printed wiring board increases.

Therefore, multilayer printed wiring board 100 of the present embodiment has a configuration for achieving the above effects. Therefore, the multilayer printed wiring board 100 of the present embodiment can solve the above problems.

(Modification)
In addition, it is possible to modify or omit the embodiments as appropriate.

For example, in the embodiment described above, the barrier layer 7 is provided above and below the insulator 3z, which is the portion that can be generated, but the present invention is not limited to this. The barrier layer 7 may be provided only above or below the insulator 3z, which is the portion that can be generated. A multilayer printed wiring board to which this configuration is applied is, for example, the multilayer printed wiring board 100 obtained by removing the barrier layer 7B from the multilayer printed wiring board 100 of FIG.

Further, for example, in the above embodiment, the wiring pattern 19 is provided on each of the front surface 8a and the back surface 8b of the substrate 8, but the present invention is not limited to this. The wiring pattern 19 may be provided only on one of the front surface 8a and the rear surface 8b of the substrate 8. FIG.

Further, for example, in the above-described embodiment, the wiring pattern 19 having the insulator 3z, which is the portion that can be generated, is provided on the surface 8a of the substrate 8, but the present invention is not limited to this. The wiring pattern 19 in which the insulator 3z, which can be generated, exists may be provided on the back surface 8b of the substrate 8. FIG.

Further, for example, in the above-described embodiment, the barrier layer 7 is configured not to contact the insulator 3z, which is the portion that can be generated, but the present invention is not limited to this. The barrier layer 7 may be configured to contact the insulator 3z, which is the portion that can be generated.

Further, for example, in the above-described embodiment, the wiring pattern 19 has one insulator 3z, which is the portion that can be generated, but the present invention is not limited to this. The number of insulators 3z, which are potential portions, present in the wiring pattern 19 may be two or more.

For example, as shown in FIG. 6, the wiring pattern 19A may have five insulators 3z, which may be generated. In this configuration, the barrier layer 7A is arranged so as to cover all of the five insulators 3z from above the five insulators 3z, which are the portions that can be generated. Also, the barrier layer 7B is arranged so as to cover all the five insulators 3z from below the five insulators 3z.

Further, for example, in the above-described embodiment, the barrier layer 7 is formed on the wiring pattern layer E10, which is a conductor layer as the surface layer of the multilayer printed wiring board 100, but it is not limited to this.

Now assume that multilayer printed wiring board 100 has configuration C below. In the configuration C, a wiring pattern 19 as a wiring layer is formed on the main surface of the substrate 8 and has a possible portion. The main surface of the substrate 8 is the front surface 8a or the back surface 8b. Further, in configuration C, a plurality of layers overlap on the main surface of the substrate 8 . The plurality of layers are configured by alternately stacking insulating layers and conductive layers. Also, the plurality of layers are composed of a plurality of insulating layers and a plurality of conductor layers.

In the multilayer printed wiring board 100 having the configuration C described above, the barrier layer 7 may be formed on any one of the plurality of layers. For example, the barrier layer 7 may be formed in a layer as an inner layer of a multilayer printed wiring board, included in the plurality of layers.

Further, for example, in the above embodiments, the substrate 8 and the insulating layers 3A and 3B are made of the resin material A containing halogen, but the present invention is not limited to this. Substrate 8 and insulating layers 3A and 3B may be made of resin material B or resin material C. As shown in FIG. The resin material B is a material obtained by impregnating a glass cloth with an epoxy resin containing no halogen. The resin material C is a material obtained by impregnating a glass cloth with an epoxy resin containing a flame retardant component different from halogen.

Further, for example, in the above-described embodiments, as barrier layer configurations, barrier layer configuration N, modified configuration A, and modified configuration B are shown, but the barrier layer configuration is not limited to these configurations. The barrier layer configuration N is a configuration in which the barrier layer 7 covers the insulator 3z, which is the portion that can be generated, and the two wirings 9 that sandwich the portion that can be generated. The modified configuration A and the modified configuration B are configurations in which the barrier layer 7 covers the entire area of the wiring pattern 19 .

For example, the barrier layer 7 may be configured to cover only the insulator 3z, which is the portion that can be generated. Further, for example, the barrier layer 7 may be configured to cover only a partial region of the wiring pattern 19 and a region including a region where the insulator 3z, which is a possible portion, exists. Further, for example, in a situation where a plurality of insulators 3z exist in the wiring pattern 19, the plurality of barrier layers 7 may each cover only the plurality of insulators 3z. The plurality of insulators 3z are components to which a voltage is applied in a voltage application state. Further, for example, the plurality of barrier layers 7 may be configured to cover only a partial region of the wiring pattern 19 and the region including the plurality of insulators 3z.

Further, for example, the barrier layer 7 is not electrically connected to the wiring pattern E<b>1 and the plurality of wirings 9 of the wiring pattern 19 in the above embodiment. That is, although the barrier layer 7 is configured so that the potential of the barrier layer 7 is not fixed at a specific potential, the present invention is not limited to this. The potential of the barrier layer 7 may be fixed at a specific potential. For example, the barrier layer 7 may be configured to be electrically connected to the wiring pattern E1.

Also, for example, in the above embodiment, the barrier layer 7 is separated from the wiring pattern 19, but the invention is not limited to this. The barrier layer 7 may be configured as a part of the wiring pattern 19 . In this configuration, for example, the barrier layer 7 is configured by the wiring included in the wiring pattern 19 so that the barrier layer 7 covers the insulator 3z that is the portion that can be generated in the wiring pattern 19 . The wiring is a wiring to which a voltage can be applied.

Further, for example, in the wiring pattern layer E10, which is a conductor layer including the barrier layer 7, the wiring pattern E1 included in the wiring pattern layer E10 may be used as a signal line for transmitting signals.

Also, in the above embodiment, the barrier layer 7 is made of copper foil, but the present invention is not limited to this. The barrier layer 7 may be composed of a metallic material other than copper foil, for example. Also, the barrier layer 7 may be composed of, for example, an inorganic material. Also, the barrier layer 7 does not have to be electrically conductive.

3A, 3B insulating layer, 3z, 3za, 3zb, 3zc, 3ze insulator, 4A, 4B conductor layer, 5A, 5B resist layer, 7, 7A, 7B barrier layer, 8 substrate, 9, 9A, 9B, 9C, 9D , 9E, 9F wiring, 19, 19A, 19B, E1, E1a, E1b wiring pattern, 20 core substrate, 100, 100A, 100N, N1 multilayer printed wiring board, E10, E10A, E10B wiring pattern layer, H1a, H1b through hole.

Claims (9)

A multilayer printed wiring board,
a substrate having a major surface;
a wiring pattern provided on the main surface of the substrate;
and a water impermeable barrier layer,
The wiring pattern includes a plurality of wirings adjacent to each other,
The multilayer printed wiring board is configured so that a voltage can be applied between the plurality of wirings,
An insulator is present between the plurality of wires,
the barrier layer covers the insulator between the plurality of wires of the wiring pattern;
Multilayer printed wiring board. The shape of the barrier layer is sheet-like,
The multilayer printed wiring board according to claim 1. The barrier layer is made of copper foil,
3. The multilayer printed wiring board according to claim 1 or 2. the barrier layer is not electrically connected to the plurality of wirings to which the voltage can be applied;
The multilayer printed wiring board according to any one of claims 1 to 3. The main surface of the substrate is
a first region in which the insulator and the plurality of wirings are provided;
and a second region that is a different region from the first region on the main surface,
the barrier layer covers at least the insulator and the second region;
The multilayer printed wiring board according to any one of claims 1 to 4. The main surface of the substrate is
a first region in which the insulator and the plurality of wirings are provided;
and a second region that is a different region from the first region on the main surface,
the barrier layer covers at least the insulator;
the barrier layer does not cover the second region;
The multilayer printed wiring board according to any one of claims 1 to 4. The multilayer printed wiring board has a wiring pattern layer covering the wiring pattern,
The barrier layer is part of the wiring pattern layer,
The multilayer printed wiring board according to any one of claims 1 to 6. the barrier layer is provided above the substrate and below the substrate;
a first barrier layer, which is the barrier layer provided above the substrate, covers the insulator from above the insulator;
a second barrier layer, which is the barrier layer provided below the substrate, covers the insulator from below the insulator;
The multilayer printed wiring board according to any one of claims 1 to 6. The multilayer printed wiring board has a first wiring pattern layer existing above the wiring pattern and a second wiring pattern layer existing below the wiring pattern,
the first barrier layer is part of the first wiring pattern layer;
wherein the second barrier layer is part of the second wiring pattern layer;
The multilayer printed wiring board according to claim 8.

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